Community Newsletter: May 2019
IN THIS ISSUE:
- Message from the Chair
Highlights of activities around the globe
- Accellera at the 56th DAC
A luncheon with experts discussing IP Security Assurance issues, and a Designer Track Session on SystemC in the Real World
- UVM-AMS Proposed Working Group
Join the discussion at the kick-off meeting in Munich!
- Conferences Throughout the Year
Four DVCon’s and SystemC Evolution Day
- Cliff Cummings on UVM Tips & Tricks
Tutorial from DVCon U.S. 2019 now available
Panel discussion from DVCon U.S. 2019 now available
As the DVCon brand continues to grow around the globe, it is inspiring to see the enthusiasm from the attendees at each conference.
I recently attended the third annual DVCon China in Shanghai, and I am proud to see the interest continue to grow in that region. The full-day conference was very well attended with many arriving early and staying well into the evening. The onsite registrations exceeded our expectations. It was evident by the large gatherings of engineers connecting with colleagues in meeting spaces throughout the day that this was an important opportunity to network and discuss design and verification issues and solutions. With the great interest we continue to see in China, we are looking forward to expanding the program and increasing participation next year.
We are excited about DVCon India and the redesigned two-day program coming in September in Bangalore. The call for abstracts garnered many outstanding submissions, and the Program Committee will be working very hard in the coming weeks to select the best and most beneficial papers for attendees.
One of the greatest benefits of the DVCon conferences is that they provide an opportunity to give input on the issues and challenges you face in your day-to-day work. At DVCon events users have proposed the need for analog/mixed-signal (AMS) extensions for the Universal Verification Methodology (UVM) standard. As a result of these ongoing discussions, the Accellera Board of Directors recently approved the UVM-AMS Proposed Working Group to determine the level of commitment in this area. We encourage anyone interested in a standard for UVM-AMS to join the proposed working group and make your voice heard. We welcome your input and participation.
Our IP Security Assurance Working Group continues to make good progress and the topic certainly has a lot of interest from the industry. We’ve assembled a panel of experts for our luncheon at the Design Automation Conference (DAC) next month to discuss the challenges and approaches for IP Security. You’ll have an opportunity to ask questions of the panelists from companies and organizations focused on these issues, including DARPA, Intel, and Tortuga Logic. We hope you’ll join us for what’s sure to be a very informative session.
I look forward to seeing you at DAC in a few weeks as well as our other events coming this fall such as DVCon India, DVCon Europe, and SystemC Evolution Day.
Lu Dai, Accellera Systems Initiative Chair
Accellera Luncheon Focusing on IP Security Assurance Issues Led by Panel of Industry Experts
We invite you to join us at DAC for a luncheon with a brief update on Accellera activities from our Chair Lu Dai, followed by an informative and thought-provoking panel addressing IP security issues. Security is as important to electronic systems as functionality is. This statement is bold, but it is reality. While the need is obvious in mission-critical applications such as automotive, communications, defense, industrial, and medical, no one wants to see their cell phone compromised or have their robotic lawnmower run amok. Complicating the challenge is that security concerns exist in all levels of these systems; these concerns need to be addressed at all phases of product development and throughout the product lifecycle.
The security experts on the panel will discuss the challenge and approaches needed to address it. Topics to be explored include:
- Responsibilities of system architects, program managers, and engineers
- Requirements for a trusted development process across the design chain
- Assessing security levels of IP blocks and sustaining security through SoC integration
- Sustainability of security for deployed products as new threats arise
- Lei Poo, Analog Devices, Inc.
- Brent Sherman, Intel and IP Security Assurance (IPSA) Working Group Chair
- Andrew Dauman, Tortuga Logic
- Serge Leef, DARPA
- Adam Sherer, Cadence and IPSA Working Group Secretary
We’ll start with a series of questions from our panel moderator and will open the discussion to audience questions. Please join us for this lively discussion as we address a broad topic impacting every electronic system.
The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.
DAC Designer Track Session: SystemC in the Real World
Wednesday, June 5
Room N260, Las Vegas Convention Center
SystemC has been widely used for almost two decades as the medium of choice for building abstract, transaction-level models. Architects and designers use these high-level models for architectural exploration and coarse-grained performance or throughput modeling. In production flows it’s important to incorporate the information contained in those abstract models into downstream, concrete portions of the flow. Connecting transaction-level modeling flows with RTL flows has long been ignored. In this DAC session, interactions between the two will be explored. How the two modeling environments can work together, each complimenting the other, to form flows that span the entire lifetime of a design from architectural exploration to coverage closure and timing closure will be discussed.
Registration with the Design Automation Conference is required to attend this presentation. Find out more about this session here.
Wednesday, May 22
Schatzbogen 7, 81829
Accellera has formed a Proposed Working Group (PWG) to focus on the standardization of analog/mixed-signal extensions (AMS) for the Universal Verification Methodology (UVM) standard.
“Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” stated Martin Barnasconi, Accellera Technical Committee Chair. “The UVM-AMS PWG will assess the benefits of creating analog and mixed-signal extensions to UVM and determine if a path to standardization is feasible. We encourage all interested companies to join our initial PWG meeting and provide input for standardization.”
The initial meeting will cover presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. Attendance is open to everyone, but registration is required. Seats are limited. Find out more about the UVM-AMS PWG.
DVCon U.S. concluded its 31st annual event earlier this year with attendees filling rooms to learn more about machine learning, Portable Stimulus, multi-platform verification, what "digital twin" means, and more. More than 1,100 attendees and exhibitors participated in the conference and exhibition this year.
“We are very pleased with the increased turnout and the positive reception of our program at DVCon U.S. 2019,” stated Aparna Dey, DVCon U.S. General Chair. “Our evolving program continues to be a strong resource for the latest information, tips, and tricks for the practicing design and verification engineer. We are very proud that our technical program, tutorials, short workshops, and panels not only covered key verification topics, but also included a number of new topics that attracted standing-room-only attendance. Our exhibition was a major draw for both attendees and exhibitors and was a gathering place each afternoon for the DV engineers and their peers to discuss the latest in technology and design.”
Save the date! DVCon U.S. 2020 will be held March 2-5 at the DoubleTree Hotel in San Jose, California.
DVCon China concluded its third annual event last month with a full-day conference that opened with three morning keynotes given by executives from Cadence, Siemens PLM Software, and Synopsys. The technical program offered six technical papers, six short workshops, three tutorials, and 16 poster presentations for attendees to choose from. The exhibition was also busy gathering place for attendees throughout the day. The award for Best Paper Presentation, as voted by conference attendees, went to Yan Wu, Yaping Yue, and Wei Ma of Intel Corp. for their paper titled, “The Power Of Testbench Automation Shortening the Verification Gap for IP Integration.” Best Poster honors went to Chenguang Guo, Yibo Liu, Hao Feng, and Zhe Chen of Allwinner Tech. for their poster, “A SystemC RTL Co-sim Platform for Architecture Exploration.”
With 225 attendees this year and the growing interest in DVCon China from the local design and verification community, the Program Committee is looking into expanding the program for DVCon China 2020. Stay tuned!
Letter from DVCon India 2019 General Chair Sanjay Muchini
After its successful launch in 2014, DVCon India has become a well-established technical conference which is made by users for users. It is where experts meet to share knowledge, experience, and best practices covering Electronic System Level Design & Verification for IP and SOC, VIP development, and Virtual Prototyping for Embedded Software development and debug. It is truly a privilege to present the DVCon 2019 India conference and exhibition that will provide an excellent platform to survey and learn the latest in design and verification technologies, methodologies, and tools from the best in the industry.
The DVCon India 2019 conference, sponsored by Accellera Systems Initiative, provides multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions, and exhibits from ecosystem partners.
I look forward to seeing further developments and practical use cases for the Portable Stimulus Standard (PSS) in this conference, as well as companies demonstrating interesting applications that combine AI data learning with verification-related databases. Attendees will also get the latest information on various Accellera standards for system design, modeling, and verification. The two-day event will be attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers, and firmware engineers.
For 2019, our ambition remains unchanged: to offer a compelling event where technical experts active in system-level design and verification can interact, share best practices, and learn the latest design and verification methodologies, languages, and standards.
Mark your calendar: DVCon India 2019 takes place September 25 & 26 in Bangalore at the Radisson Blu Hotel. The DVCon India steering committee and Accellera wish you a warm welcome and an enjoyable DVCon India 2019!
The sixth annual DVCon Europe will be held October 29 & 30 in Munich, Germany at the Holiday Inn Munich City Centre. The focus of this highly technical conference is on the industrial application of specialized design, verification, and validation methodologies; design and verification languages such as C, SystemC, SystemVerilog, UVM, formal, and assertion-based verification; the use of AMS languages; design automation using IP-XACT; and the use of other general purpose languages.
DVCon Europe 2019 will include two keynote speeches, panel sessions, a broad range of papers and posters, 16 tutorials, and an exhibition with demonstrations from leading tool, IP, and service providers. For more information on the conference please visit dvcon-europe.org.
To view the papers and presentations from DVCon Europe 2018, visit here.
SystemC Evolution Day will be co-located with DVCon Europe again this year and will follow the conference on October 31 at the Holiday Inn Munich City Centre. The fourth SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion.
The Call for Contributions for Lightening Talks and Focus Sessions is open. The deadline to submit an abstract is May 22. Submission of new topics related to the SystemC modeling requirements from user experience and application domains, such as next generation automotive, 5G wireless, and Internet-of-things is encouraged. For more information on SystemC Evolution day visit here.
Cliff Cummings' tutorial, “Gain Valuable Insight into — and Make the Most Out of — the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM,” presented at DVCon U.S. 2019 is now available. The tutorial addresses the changes and features that are part of the new IEEE 1800.2 standard for UVM. Cliff provides his favorite UVM tips and tricks, and offers clarification and guidelines for UVM messaging and verbosities. He also explains the origins of the two different techniques to define UVM transactions and execute sequences, including the advantages and disadvantages of each. With this knowledge, viewers will have a greater understanding of all publicly available UVM examples. Register to view the tutorial >
At the annual Accellera Luncheon at DVCon U.S. 2019, Laurie Balch from Pedestal Research moderated a SystemC-focused panel that explored what’s next and what should be next for the SystemC standard. Panelists participating: Stuart Swan, Mentor, A Siemens Business; Filip Thoen, Synopsys, Inc.; Mike Meredith, Cadence Design Systems, Inc.; Mark Glasser, NVIDIA Corp.; and Martin Barnasconi, NXP. Listen to the panel >
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