SystemVerilog Mixed-Signal Interface Types Working Group


The charter of the Mixed-Signal Interface (MSI) Working Group is to document a SystemVerilog-compatible language extension to permit interconnect, conversion, and resolution among dissimilar net types in SystemVerilog, including bidirectional connections.

Chair: Tom Fitzpatrick, Siemens DISW
Vice Chair: Peter Grove, Renesas


To develop additional capability integral to the SystemVerilog language to support uni- and bi-directional net connections between logic/UDN (User-Defined Net) and analog/electrical/real signals. This standard will be a strict addition to IEEE 1800 and will not otherwise change the syntax or semantics of SystemVerilog. This will provide vendors a standard on which they can build implementations of this new functionality, and provide users a reliable platform with which to model and simulate complex mixed-signal design and verification environments.

The WG will produce a formal Language Reference Model (LRM) for this new functionality that may be considered an addendum to IEEE 1800.


The Accellera UVM-AMS and SystemVerilog-AMS Working Groups have illustrated that there is a fundamental need for support of bidirectional net connections between logic/UDN (User-Defined Nets) and analog/electrical/real signals as an integral part of IEEE P1800.Unfortunately, this need was not identified in time to include it in the upcoming IEEE 1800-2023. Past efforts to add similar functionality outside of IEEE 1800, such as Verilog-AMS connect modules, have proven unable to address the complexity and usability requirements that have arisen in typical System-on-Chip designs.

Join this Working Group

If you are an employee of an Accellera member company and wish to participate in the SystemVerilog MSI WG, please log in or create an account in the Accellera Workspace. Once you are logged in to the Workspace, select "View Workgroups", select SystemVerilog-MSI Working Group, and click the Join button.