Design & Verification Conference and Exhibition
Around the Globe
The Design and Verification Conference (DVCon) and Exhibition provides attendees around the globe with the industry’s most comprehensive technical program focused on the design and verification of electronic systems. DVCon attracts engineers and industry technologists across many design disciplines including systems, standard IC, ASIC, DSP, microprocessor, FPGA, library, analog/mixed-signal and SoC. From its beginning as a combination of the OVI Users Group and VHDL Users Group in the U.S. more than 25 years ago, DVCon has grown to include DVCon Europe and DVCon India in 2014 and DVCon China in 2017. Each conference is tailored to its specific region with involvement from local companies.
At all DVCon Conferences and Exhibitions:
- Attendees gain insight from users on standards and languages. DVCon selects the best user experiences, high quality papers and presentations detailing best practices on the application of standardized languages, tools and methodologies for design and verification such as UVM, SystemC (and its variants such as SystemC-AMS, SCV, CCI, Synthesis subset), SystemVerilog, PSL, Assertions for AMS, Verilog, IP-XACT, OCP and many more.
- Learn from the experts. DVCon organizes technical workshops and tutorials on emerging EDA and IP standards, with highly educational and applicable content. Experts in the industry share on topics such as UVM, SystemC and IP-XACT, with the fundamental concepts and practical usage of these standards explained along with examples and demonstrations.
- Connect to standardization developments. DVCon is hosted by Accellera Systems Initiative, the recognized organization with the mission to develop and deploy EDA and IP standards. Experts are available throughout the conference to discuss standards development and user needs.
- Network with peers. DVCon is the place to meet experts from various industries and connect with peers to discuss the latest practices and trends in design and verification. Networking events provide attendees with an opportunity to interact with colleagues, share techniques and learn how other users tackle their latest challenges.
- Find out the latest EDA and IP vendor offerings. Each conference hosts a compact exhibition where the industry can meet to discuss EDA and IP tool and service solutions. Attendees can visit the exhibition for demonstrations, interactive discussions and top vendor offerings.
DVCon U.S., held in San Jose, California, offers attendees a full four-day technical conference that kicks off with "Accellera Day," a day filled with information-packed technical tutorials focused on design challenges and the future of efficient design. The program also offers panels, poster sessions, a keynote address, evening networking receptions and an exhibition.
DVCon Europe, held in Munich, Germany, provides attendees with a comprehensive two-day technical program and exhibition. Its technical program is targeted toward local interests and each year it provides its attendees with in-depth technical papers, tutorials, keynote speeches, a networking reception and an exhibition.
DVCon India, held in Bangalore, India, offers attendees a two-day technical conference and exhibition. The conference provides two parallel tracks for its in-depth technical program: ESL and Design & Verification. Attendees can choose among a wide variety of technical papers, tutorials and keynotes, a networking reception and an exhibition.
DVCon China is a one-day event held in Shanghai, China. The conference brings industry, academia and standards development organizations together for a day full of technical presentations and networking. General topic areas on Electronic System Level (ESL), Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low Power design and verification are highlighted in tutorials, papers, and poster sessions.
DVCon Japan will be held at the Kawasaki City Industrial Promotion Hall and is focused on functional verification, which is an extremely important issue in this region. Topics include IEEE standards, SystemVerilog, UVM, UPF, Accellera Portable Test and Stimulus Standard, formal verification methodologies, analog mixed signal, IP-XACT, functional safety and security.