UVM-MS - Frequently Asked Questions

What is the focus of the new working group?

The charter of the new working group is to develop a standard that will provide a unified analog/mixed-signal verification methodology based on UVM to improve the verification of AMS integrated circuits and systems.

What value will the UVM-AMS standard bring to the community?

The UVM-AMS WG envisions the availability of an industry-agreed analog/mixed-signal verification methodology based on its planned UVM-AMS standard. This will encourage support by tool and IP providers, offering ready-to-use analog/mixed-signal verification IP that can be integrated easily into a UVM-AMS testbench. It will raise the productivity and quality of analog/mixed-signal verification across projects and applications, thanks to the reuse of proven verification components and stimuli.

What is the working group activity in the first 6 to 12 months?

We will initially focus on consolidating the industry requirements of UVM-AMS and develop a whitepaper that will help define the scope of the standardization effort. This whitepaper will be shared with the AMS verification community to benchmark the ideas of the working group with the expectations of the industry.

What will be defined in the UVM-AMS standard?

Similar to UVM, the UVM-AMS standard will define a set of application programming interfaces (APIs) to enable the development of modular, scalable, and reusable AMS verification components and testbenches. To this purpose, the standard will define the language constructs and execution semantics supporting an AMS verification methodology based on simulation techniques.

Will the working group develop a reference implementation?

The primary focus of the working group is to develop the UVM-AMS standard. To assure that the standard can be implemented, the development of a reference implementation is considered, but dependent on potential contributions of the Accellera member companies active in the working group. We encourage member companies to donate their prototypes and examples, which could serve as a starting point for the development of such a reference implementation.

What will be the foundation language for UVM-AMS?

There are various languages used for AMS verification, such as Verilog-AMS, SystemVerilog, and also SystemC-AMS. The aim is to define a standard API that is language-agnostic to enable the creation of a reference implementation in any of these languages.

My EDA tool provider offers AMS extensions for UVM. Is this compatible with the planned UVM-AMS standard?

As UVM-AMS is not defined as a standard yet, existing EDA solutions are independent from this standardization initiative. We encourage EDA solution providers to participate in the UVM-AMS Working Group and share their experiences so industry usage and methodologies can be incorporated into this future standard.

I currently use Interface Verification IP which only supports digital signals. Should I replace them with AMS Verification IP?

The objective of the UVM-AMS standard is to introduce dedicated capabilities that enable making AMS extensions to digital-centric verification IP. As UVM offers the foundation technology, we could benefit from using testbench configuration, factory-based component overrides, and virtual interfaces to seamlessly insert AMS components, signals, and analysis in an existing digital-centric verification IP. Obviously, this extension heavily depends on the flexibility and configurability offered in the digital VIP itself.

Will UVM-AMS support multi-language verification?

The main focus of UVM-AMS is to standardize the API to drive and monitor analog/mixed-signal nets within UVM, including stimulus, scoreboarding, and analysis. The multi-language aspects are out-of-scope for the UVM-AMS Working Group. There is another Accellera working group active with the objective to develop a standard for multi-language verification.

Will the UVM-AMS Working Group develop specific AMS verification IP?

The primary objective of the UVM-AMS Working Group is to develop a standard that forms the framework to develop AMS verification components or testbenches. As such, the working group itself will not develop these elements. The internal functionality to drive, monitor, or analyze AMS signals should be developed by the verification team. However, to explain how to create an AMS verification IP or testbenches to the AMS verification community, it is expected that there will be basic examples available as part of the deployment of the UVM-AMS standard.