Community Newsletter: August 2022
IN THIS ISSUE:
- Message from the Chair
- We’ve been busy! We look forward to seeing you at an event soon
- Recent News
- Lynn Garibaldi Receives the Accellera 2022 Leadership Award
- Accellera Proposed Working Group to Explore CDC Standard
- Upcoming Events
- DVCon India 2022 (September 5-6)
- SystemC Evolution Fika (September 15)
- DVCon Europe (December 6-7)
- SystemC Evolution Day (December 8)
- Post-Event Summary: DAC 2022
- Videos and More
- DVCon U.S. Videos Now Available – and many more on-demand
- SystemC.org – a resource for the SystemC Community
- Recent Media Coverage
- Accellera Chair Lu Dai provides insight into recent standards efforts
- Lynn Garibaldi discusses Accellera’s history in a SemiWiki podcast
- IEEE Get Program Update
- More than 150,000 downloads!
Message from the Chair
I hope everyone has enjoyed the summer months, especially after a busy Design Automation Conference (DAC) in July. Accellera sponsored a lunch panel at DAC focused on analog/mixed-signal (AMS) design. For the first time in many years AMS is back at the forefront of discussion. Many interesting ideas were raised during the panel, and our working group members will integrate some of them into the upcoming UVM-AMS whitepaper. We also have ongoing development in our SystemVerilog AMS and SystemC AMS working groups where the topics discussed during the panel are also applicable.
At DAC we announced that our Executive Director, Lynn Garibaldi, is the recipient of our 2022 Leadership Award. Lynn has been an integral part of the Accellera leadership team for 30 years and is well-deserving of this recognition and award.
We also recently announced the formation of a Proposed Working Group (PWG) to focus on defining standard Clock Domain Crossing (CDC) input/output collateral to facilitate cross-platform CDC verification. This newest PWG is a direct result of a need brought to our board of directors by member companies. It demonstrates the value of looking for opportunities where challenges exist and working to find solutions in an industry standard.
New standards efforts also bring about membership growth in Accellera. We’d like to welcome our newest members Allegro Microsystems, Ansys, Juniper Networks, Renesas, Scientific Analog, and Optima. Our membership represents a broad range of worldwide electronics organizations including SoC companies, tool vendors, intellectual property suppliers, and embedded software developers.
If you have a new idea for a design or verification standard, we welcome your input. If you are facing a problem in your daily work that you think a collaborative industry standard could help and your company is an Accellera member, you can reach out to your company’s Accellera representative. You can also join our working groups or participate in our online discussion forums. For more information about our standards and their benefits, our working groups have many sessions you may want to attend at our DVCon conferences, as well as various Accellera-sponsored panel discussions.
Our first DVCon Japan was held virtually in June, and we are back to in-person with DVCon India next month and DVCon Europe and SystemC Evolution Day in December. The last couple of years we have been able to connect with our community through online events, but I think I speak for many when I say that we are looking forward to these upcoming conferences where we can meet our friends and colleagues face-to-face again.
I hope to see you at one of our upcoming events soon.
Lu Dai, Accellera Systems Initiative Chair
Lynn Garibaldi Receives the 2022 Accellera Leadership Award
Lynn Garibaldi was presented with the 2022 Accellera Leadership Award at the 59th Design Automation Conference during an Accellera-sponsored lunch panel. The award recognizes the vision, leadership and contribution to standards development, governance, and promotional activities on behalf of the organization.
“Lynn has been an integral part of the Accellera leadership team for 30 years,” stated Lu Dai, Accellera Chair. “She is a tremendous asset, helping to guide the organization through the many mergers that became Accellera since the founding of Open Verilog International (OVI). She has overseen the growth in our working groups, membership, and has helped to promote the advancement of standards among the global community of users. She continues to demonstrate a dedication to the organization and its members that is unmatched. It is befitting that we honor Lynn with the Accellera Leadership Award for her 30 years of superior service.”
For more information, read the full press release.
Proposed Working Group to Explore Clock Domain Crossing
A new Proposed Working Group (PWG) will focus on defining the requirements for a standard Clock Domain Crossing (CDC) collateral specification to ease SOC integration. Currently, SoC teams cannot reuse IP-level CDC collateral in the SoC environment if both teams use different CDC verification tools, causing a time-consuming CDC verification problem. Standardization on CDC collateral will bring significant benefit to not only product companies, but also IP design houses, EDA tool companies, and the entire ecosystem.
“Typically, the CDC verification tools that the IP and SoC teams use rely on different formats to capture CDC intent,” stated Martin Barnasconi, Accellera Technical Committee Chair. “Based on the level of interest and commitment from the community, the PWG will determine if a standard is needed to enable the interoperability of CDC collateral generated by different CDC verification tools to ease integration. If your company is interested in providing input, please join us for the initial kick-off meeting in September.”
The first Proposed Working Group meeting will be held Tuesday, September 13th from 9am – 4pm PT at Intel SC12, 3600 Juliette Lane, Santa Clara, SC12-538. For more information about the PWG, visit here.
The Chair of the CDC PWG invites you to join the kick-off meeting.
For more information, read the press release.
DVCon India will be in-person September 5-6 at the Radisson Blu, Marathalli, Bangalore. The conference opens with a vision talk by Manish Pandey, Vice President Engineering, Synopsys focused on “Unleashing AI/ML for Faster Verification Closure,” followed by a keynote, “Emerging Design/Verification Technologies and Standards—Which Comes First?” presented by Dave Rich, Verification Architect, Siemens EDA.
The two-day conference will have four parallel tracks with tutorials, short workshops and exhibits on Monday and paper and poster sessions on Tuesday. Both days will have keynotes and panels.
Accellera’s Portable Stimulus Working Group will have a tutorial, “Portable Stimulus Standard Update: PSS in the Real World,” on September 5 beginning at 11:45am.
“This conference will give you ample opportunities to share and highlight your technical contributions in the areas of Verification & Validation, Methodology & Automation, Functional Safety & Security, Low Power and Mixed Signal Design, Static and Formal Methods and Digital Twins and SystemC Modelling,” Stated Pradeep Salla, DVCon India General Chair 2022. “This year, we have added a special topic for New Design Areas and Disruptive Trends in Design Verification to showcase the latest work being done in AI/ML implementation, Big Data analysis and new algorithms in HW/SW co-design and co-verification.” For more from the General Chair, read the Welcome Message.
For more information on the program and to register, visit the conference website.
To view the proceedings from virtual DVCon India 2021, visit here.
SystemC Evolution Fika
The next SystemC Evolution Fika will be held September 15. The virtual workshops are referred to as Fikas to honor the Swedish tradition of sharing a coffee, slowing down a bit, and talking about things the participants care about. Free of charge, the Fikas are an extension of the annual SystemC Evolution Day co-located with DVCon Europe. They are offered as smaller online workshops throughout the year.
The September 15 Fika will be focused on “Safety-related Use Cases of SystemC-based Virtual Prototypes.” Increasingly, virtual prototypes are used in a safety-related context. In automotive and avionics, for instance, commonly known and discussed use cases include the development of embedded software as well as their use as an executable specification across the vendor chain.
The workshop will look at their value for the design & verification of safety-critical systems and address such questions as: How are they used? What are the benefits? How useful are the results?
To register for the upcoming Fika, visit here. For more information and to view presentations from past fikas, visit the SystemC events page.
If you have topics that you think should be included in an upcoming Fika, please email
The ninth annual DVCon Europe will be held in-person in Munich, Germany December 6-7. Advance registration for the conference and exhibition is available through October 31. Stay tuned for more information on the program coming soon.
To view videos from DVCon Europe 2021, visit here.
SystemC Evolution Day
The seventh SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. It is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.
The Call for Presentations is available and the deadline for submissions is September 15, 2022. For more information on SystemC Evolution Day and submission guidelines, visit the event webpage.
The 2022 workshop will be held December 8 from 9:00-17:00 CEST at the Holiday Inn Munich City Centre.
Presentations and videos from SystemC Evolution Day 2021 can be found here.
Stay Up to Date with Accellera Events
Visit the Accellera events page for the most recent updates on Accellera-sponsored events.
Post-Event Summary: DAC 2022
Accellera sponsored a luncheon and panel discussion at DAC focused on the current state of analog/mixed-signal (AMS) standards. Panelists Nagu Dhanwada, IBM; Martin Barnasconi, NXP and Accellera Technical Committee Chair; Peter Grove, Renesas; Lakshmanan Balasubramanian, Texas Instruments; and Xiang Li, Qualcomm presented their thoughts on the challenges and opportunities facing AMS standards development.
The interactive panel, moderated by Tom Fitzpatrick, Accellera UVM-AMS Working Group Chair, addressed questions from attendees and provided insight into what needs to happen with the current initiatives to further advance mixed-signal design and verification standards. Below is the slide used to open the panel discussion.
Videos and More
DVCon U.S. Videos
The videos from virtual DVCon U.S. 2022 are now available! While you’re waiting for DVCon U.S. 2023, enjoy videos from DVCon U.S. 2022 as well as other DVCon conferences. If you’re looking for information on an Accellera standard or a presentation from an event, Accellera has over 300 videos archived that are accessible to everyone for free.
If you’re looking for the most up-to-date information about SystemC, as well as what’s relevant to the SystemC Community, systemc.org is the place to start. It is a community portal with online references to just about everything related to SystemC.
Recent Media Coverage
Accellera Chair, Lu Dai provides insight into the new CDC Proposed Working Group and standards efforts with Functional Safety and AMS in a recent discussion with Bernard Murphy, SemiWiki.
Lynn Garibaldi, recipient of the 2022 Accellera Leadership Award, talks with SemiWiki’s Daniel Nenni about the history, reach, and impact of Accellera in a recent podcast.
IEEE Get Program Update
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 150,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
Accellera Global Sponsors
Contact us if you interested in becoming a Global Sponsor.
Copyright 2022 Accellera Systems Initiative