Community Newsletter: February 2019


  • Message from the Chair
    There is a lot in store for our members in 2019
  • Upcoming Accellera Events
    Mark your calendars!
    • DVCon U.S. is in two weeks – don’t miss the 31st annual conference and exhibition
    • The DVCon China full program is available and advance registration is open
    • DVCon India is returning this year – watch for the call for papers
    • DVCon Europe General Chair describes the goals for this year’s conference
    • SystemC Evolution Day is a full day workshop co-located with DVCon Europe
  • Call for Participation
    The IEEE P1666 Working Group is looking for member participation on a revision to the standard


Message from the Chair

Lu Dai, Accellera Systems Initiative ChairWelcome to the beginning of an exciting year at Accellera! 2019 is off and running, and we have a lot in store for our members this year. We have a new standard that already has a lot of traction, we have added new members, we’re evolving existing standards, and we have five major events throughout the year around the globe.

The Portable Stimulus Working Group has been focused on incorporating some errata for PSS 1.0 into the specification, making it much easier for users to see the clarifications within the standard itself. We’ll have PSS 1.0a available soon – stay tuned!

Our newest working group, IP Security Assurance, is meeting regularly to define an IP security assurance specification, and we’re seeing a lot of interest from the community on this topic. As a result, we’ve added new members because they want to get involved early and help shape the development of a new standard to address security assurance for hardware IP. The working group will be holding a face-to-face meeting at DVCon U.S., so if you’re interested and not currently an Accellera member, now is the time to join and have your voice heard.

We’ve got an informative and diverse program in store for attendees at DVCon U.S. During Accellera Day we’ll have a tutorial focused on UVM and a short workshop focused on high-level synthesis and functional coverage for SystemC. We’ll also have our luncheon with the presentation of our annual Technical Excellence Award, followed by a panel discussion on the future of SystemC. After lunch, we’ll gather to honor an old friend, Joe Daniels, who passed away unexpectedly in November. He was near and dear to us as he worked closely with many of our members helping to develop much of our technical documentation over the years.

Our other events throughout the year include DVCon China in April, the return of DVCon India in September, and DVCon Europe and SystemC Evolution Day in October.

We are looking forward to another busy and successful year.

Lu Dai, Accellera Systems Initiative Chair


Upcoming Accellera Events

DVCon U.S. 2019

DVCon U.S. 2019Accellera Day opens the conference on Monday, February 25th with a full morning UVM-focused tutorial titled, “Gain Valuable Insight into the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM and How to Make the Most of Them,” presented by Cliff Cummings.

The tutorial will be followed by an Accellera-sponsored luncheon that will include a presentation with an update on Accellera activities by Lu Dai, Accellera Chair; the presentation of the Accellera Technical Excellence Award; and a panel discussion focused on the future of the SystemC Language moderated by Laurie Balch, Research Director for Pedestal Research. In the afternoon there will be four Short Workshops including “SystemC: Focusing on High Level Synthesis and Functional Coverage for SystemC” sponsored by Accellera.

The Keynote, “Thriving in the Age of Digitalization,” will be presented by Fram Akiki, Vice President, Electronics & Semiconductor Industry for Siemens PLM Software, on Tuesday, February 26th. In addition to the keynote, over the course of the four-day program there will be 39 in-depth technical papers, four tutorials, 25 posters, eight short workshops, and two panels.

“I think attendees will be very impressed by the depth and breadth of our technical program this year,” stated Tom Fitzpatrick, DVCon U.S. 2019 Technical Program Chair. “In addition to the key technical topics our attendees have come to expect from DVCon, we had many submissions on new topics this year that will be very compelling and beneficial to our audience. We’ll have two paper sessions on Portable Stimulus, as well as sessions on applying “Big Data” to verification, formal verification, hybrid verification environments and many other valuable topics. With two great panels on Deep Learning and RISC-V, there are many intriguing topics for attendees to choose from as they review the detailed program.”

“As in years past, the tutorials and short workshops cover a wide variety of topics,” commented Vanessa Cooper, DVCon U.S. 2019 Tutorial Chair. “There are sessions on UVM, Formal Verification, Portable Stimulus, Safety, and Machine Learning just to name a few. Conference goers will easily find multiple sessions of interest to attend.”

For the complete DVCon U.S. 2019 schedule, visit the website. To register visit the registration page.


DVCon China 2019

DVCon China 2019The third annual DVCon China will be held April 17th at the Crowne Plaza Hotel Century Park, Shanghai. The full program is available online and advance registration is open through March 15. There will be morning keynotes followed by a poster session with 16 posters, 15 technical presentations and an exhibition.

“I look forward to seeing further developments and practical use cases for the Portable Stimulus Standard (PSS) in this conference, as well as companies demonstrating interesting applications that combine AI data learning with verification-related databases,” stated Bin Liu, DVCon China 2019 general chair. “The DVCon conference is positioned not only to enable attendees to understand the latest IC design verification technology applications, but also to enable IC design verification to become more professional at home. While improving the specialization of design verification, we also need to make efforts to alleviate the shortage of IC design verification talents.”


DVCon India 2019

DVCon India 2019Save the date! DVCon India is coming back on September 25-26, 2019 at the Radisson Blu Hotel in Bangalore. The Steering Committee is in place and the call for papers will be available soon. Stay tuned!


DVCon Europe 2019

DVCon Europe 2019Letter from DVCon Europe 2019 General Chair Joachim Geishauser

In the past five years, DVCon Europe has become a well-established conference: made by users for users, where experts meet, and where new business relationships and friendships start. In those five years, the European design and verification network has grown, and the DVCon Europe family has been built. We are proud that we have achieved this, together with you!

The challenges of today’s integrated embedded systems go far beyond development of hardware alone. Embedded software has become a key ingredient in many applications. However, finding the right tradeoff between hardware and software components remains the ultimate challenge. This means that software and hardware engineers need to work closely together, understanding both disciplines.

DVCon Europe, together with Accellera’s co-located SystemC Evolution Day, offers you a unique opportunity to escape from your daily work environment and learn from your peers in the industry. To address the multi-disciplinary challenges our industry is facing, DVCon Europe will broaden its scope in the call for papers and tutorials by including embedded software. As chair of DVCon Europe 2019, I encourage embedded software developers to come to the conference to share their challenges and get to see what the hardware side is working on. DVCon Europe and the Accellera SystemC Evolution Day will offer a discussion forum for the engineering community to further enrich the SystemC ecosystem.

Joachim GeishauserFor 2019, our ambition remains unchanged: to offer a compelling event where technical experts active in system-level design and verification can interact, share best practices, and learn the latest design and verification methodologies, languages and standards.

Mark your calendar: DVCon Europe 2019 takes place from October 29 to 30 in Munich Germany, followed by the SystemC Evolution Day on October 31, 2019. The call for papers, tutorials, and panels is now open.

The DVCon Europe steering committee and Accellera wish you a warm welcome and an enjoyable DVCon Europe 2019!


SystemC Evolution Day 2019

SystemC Evolution Day 2019The fourth SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for Accellera/IEEE standard’s inclusion. It will be co-located with DVCon Europe again this year and will be held October 31, 2019.

SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.

More details will be available soon. View the presentations from SystemC Evolution Day 2018.


Call for Participation: IEEE P1666 Working Group Focused on Revision to the SystemC Standard

SystemCThe IEEE P1666 (SystemC) Working Group is ramping up and focused on developing a revision of the SystemC and Transaction Level Modeling (TLM) standards. The goal is to implement new features as well as errata that have been identified since the last revision in 2011.

“Much of the content we’ve already identified is the result of hard work within the Accellera SystemC Language Working Group,” stated Jerome Cornet, IEEE SystemC Working Group Chair. “Of course, we’re open to contributions from other working groups, such as the SystemC Synthesis Working Group, as well as those donated directly at the IEEE level by P1666 contributors.”

Still in the preliminary stages, the Working Group is looking to address new core simulator features, datatypes, and enhancements to the TLM portion of the standard. “We expect improvements to the simulation capabilities as well as elements to help better address both model-to-model and model-to-tools interoperability,” continued Cornet. “We will also pay close attention on how to benefit from the powerful recent evolutions to our underlying standard: ISO C++ (with C++11, 14,17).”

The P1666 Working Group is targeting early 2021 for completion and approval of the revision. There are two main ways for you to get involved in this revision: 1) indirectly by working through the Accellera SystemC Working Groups and arranging for the contributions to be donated through Accellera, or 2) directly by being an active participant of the P1666 Working Group. The latter requires that you are affiliated with a company that is a corporate member of IEEE-SA. If you use SystemC as part of your business, consider joining P1666 to make the SystemC standard even better.

“This revision is an opportunity not only to add potential small missing features that would make a big difference in day-to-day interoperability or when integrating with other standards, but to materialize the future of the standard,” Cornet concluded.

If you have any questions about joining the IEEE P1666 Working Group, please contact Jerome Cornet ( ), IEEE SystemC WG Chair, or Jonathan Goldberg ( ), IEEE representative for SystemC.



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