Community Newsletter: February 2023
IN THIS ISSUE:
- Message from the Chair
- 2023 is off to a great start!
- Latest News from Accellera
- New CDC Working Group
- Accellera contributes SA-EDI Standard 1.0 to the IEEE
- Accellera at DVCon U.S. 2023
- Join us for standards-related events
- Upcoming Events
- DVCon U.S February 27-March 2
- DVCon Japan June 22
- Post-Event Summaries
- DVCon Europe 2022
- SystemC Evolution Day 2022
- Videos and more available on demand
- IEEE Get Program Update
- Almost 158,000 downloads!
I hope 2023 is off to a good start for each of you. Since our last newsletter, DVCon Europe concluded its first in-person event since the pandemic, celebrating excellent attendance. We are eager to connect with our colleagues later this month for DVCon U.S. and in June for our first in-person DVCon Japan. I look forward to seeing you at one of our events in 2023.
Although the new year has just begun, our Accellera work is in full swing. The Board of Directors recently approved the Clock Domain Crossing (CDC) Working Group, and members have already made significant advancements. The CDC Design Objective Document is in progress and the in-depth working group discussions are well underway. We also contributed our Security Annotation for Electronic Design (SA-EDI) Standard 1.0 to the IEEE for the development of the P3164 draft standard. This is a very exciting time for our IP Security Assurance Working Group, and we congratulate them on their efforts.
As always, I’d like to encourage you and your colleagues to share your thoughts and feedback with us. We’d like to hear from you on existing standards as well as new ideas for standards. Our standards come from community interest and are here for the benefit of everyone. As designs continue to grow in complexity, together we continue to innovate and refine standards for ever increasing quality, efficiency, and productivity. If you aren’t already an Accellera member and would like to join to have a direct impact on standards development, please get in touch with us.
I’d also like to take this opportunity to honor Andres Takach, our long time SystemC Synthesis Working Group Chair, beginning with the Open SystemC Initiative (OSCI). Sadly, Andres passed away recently, and we are grateful for his contributions and dedication to the SystemC ecosystem over many years. He was instrumental in bringing SystemC to great heights in the HLS arena, a tremendous benefit to the community.
From all of us at Accellera, we wish you the best in the coming year.
Accellera Systems Initiative Chair
Accellera Forms Clock Domain Crossing Working Group
The Board of Directors recently approved the new Clock Domain Crossing (CDC) Working Group. It will focus on defining a standard CDC collateral specification to ease SoC integration. Currently, SoC teams cannot reuse IP-level CDC collateral in the SoC environment if both teams use different CDC verification tools, causing a time-consuming CDC verification problem.
“Accellera’s mission is to collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products,” stated Lu Dai, Chair of Accellera. “Our newest working group will address the incompatibility of collateral generated by different CDC verification tools, which will help to greatly improve productivity. If you’re not currently a member of Accellera and would like to help shape the development of this standard, we encourage you to join and provide your input.”
“Our objective is to develop a standard format to capture CDC/RDC/Glitch intent,” stated Dammy Olopade, CDC Working Group Chair. “This will enable interoperability of CDC collateral generated by different CDC verification tools. We have been meeting as a proposed working group since September, and there has already been tremendous industry support. During the upcoming working group meetings, we will focus on the effort to produce a normative Language Reference Manual (LRM),” Olopade concluded.
Find out more about the CDC Working Group here.
Accellera’s Security Annotation for Electronic Design (SA-EDI) Standard 1.0 has been contributed to the IEEE for the development of the P3164 draft standard. “As a result of our longstanding partnership with the IEEE, our standards are able to achieve widespread global recognition and use,” stated Lu Dai, Chair of Accellera. “We anticipate that as the IEEE P3164 Working Group gets underway, this standard will be of tremendous benefit to IP providers and silicon integrators around the world as they work to reduce security risks in their IP.”
“SA-EDI 1.0 has been in the hands of the community for over a year and has already helped a number of providers in their quest to identify security issues,” stated Brent Sherman, IPSA Working Group Chair. “The standard is low overhead, non-disruptive, and scalable across multiple target implementations. We look forward to the continued work within the IEEE P3164 Working Group to continue to advance the standard.” Sherman is now Chair of the IEEE P3164 Working Group.
To learn more about the SA-EDI Standard and how it can help IP providers identify security concerns, there are resources on Accellera’s IP Security Assurance Working Group page, as well as the IEEE Security Annotation for Electronic Design Integration page.
Join us for events focused on standards development! The following DVCon events are open to registered DVCon attendees (these events are not part of the free registration option). Registration is open >
Portable Stimulus Working Group Tutorial
Monday, February 27
The Accellera Portable Stimulus Standard is moving beyond the “bleeding edge.” As the Portable Stimulus Working Group continues to develop additional features of the language, many companies are adopting the standard in their verification flows. This technical tutorial will begin with an overview of the new features to be included in the coming update to the standard and will feature users from AMD and Intel who will share their experiences using this exciting new technology.
IP-XACT IEEE 1685 Working Group Workshop
Monday, February 27
Accellera’s IP-XACT Working Group has been developing a proposal for a revision of IEEE Std. 1685-2014. The proposal was handed over to the IEEE P1685 Working Group in late 2021 and was approved by IEEE Standards Association Board in September of 2022. This workshop addresses the IP-XACT user community including IP and SoC companies, EDA vendors, and research institutes to inform them about upcoming changes in IEEE Std. 1685. It also addresses examples of commercial tool support for these changes.
UVM-AMS Working Group Workshop
Monday, February 27
The Accellera UVM-AMS Standard will define an architecture and methodology to extend UVM testbenches from digital-only applications to DMS/real-number and AMS designs as well. This technical workshop will walk the audience through a worked example that will illustrate the key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments.
Accellera Luncheon: Featuring Bob Smith Executive Director, SEMI ESD Alliance
Monday February 27
Join us for lunch and a captivating talk where Mr. Smith will present “The CHIPS Act and Its Impact on the Design & Verification Markets.”
IEEE 1666 Working Group Workshop
Monday, February 27
The next revision of IEEE 1666 SystemC is coming! It builds on enhancements and features contributed by the SystemC community during the last decade through the Accellera SystemC Language Working Group. This workshop will present some of the features of the upcoming revision that modernize the language and enable new use cases. The target audience of this short workshop are system engineers, designers, and architects who are familiar with SystemC simulation and modeling concepts and would like to know which new capabilities are being introduced to enable efficient Electronic System Level (ESL) design, systems modeling, or virtual prototyping in SystemC.
Accellera Luncheon: Featuring Mark Himelstein, CTO RISC-V
Wednesday, March 1
Join Accellera for a brief update on working group activities followed by an invited talk, “RISC-V Everywhere” presented by Mark Himelstein, CTO of RISC-V.
Accellera Luncheon: UVM 1800.2-2020-2.0 Library Discussion
Thursday, March 2
UVM Working Group members will discuss the release of the 1800.2-2020-2.0 library. Presenters will focus on the implementation of the IEEE 1800.2-2020 standard to the library, with greatly enhanced backward-compatibility using code written for UVM1.1d or UVM1.2, creating some substantial performance improvements. Questions from attendees are welcome!
“The DVCon U.S. 2023 Steering Committee looks forward to bringing back our friends and colleagues for an in-person technical program," stated Josh Rensch, DVCon U.S. 2023 Program Chair. “We have a program focused on design and verification with topics ranging from UVM, Formal, and IP-XACT, to an entire session on RISC-V. Academics will have opportunities to learn new technologies, and engineers will have topics to choose from to help in their day-to-day projects. In addition to the 41 paper presentations, we’ll have two panels, 17 poster sessions, four tutorials, and 16 workshops throughout the four-day program.”
The keynote speaker this year is Dirk Didascalou, Chief Technology Officer, Siemens Digital Industries. Mr. Didascalou will present, “What Do Farming, Steel, and Space Have in Common?” on Tuesday, February 28. With examples from Space Perspective, 80 Acres Farms and others, Mr. Didascalou will discuss how the new wave of digitalization is driving huge transformations and can be an inspiration for every industry.
Other conference highlights include:
- Poster Ninja Warrior session on Wednesday, March 1 includes four posters battling it out for top honors. Posters will be judged on a variety of factors, including audience reaction.
- Two panels will be offered on Wednesday, March 1:
- “Systems are Evolving. Is Verification Keeping Up?” will be moderated by Bernard Murphy, SemiWiki. Panelists will discuss areas where they would like to see breakthroughs and ideas and research that they would like to see explored further.
- “AI-ML Algorithms are Transforming Verification: Separating Hype from Reality,” will focus on the state of the art of design verification environments that power the new generation of advanced processors. Panelists will discuss systems which could potentially change the semiconductor landscape.
Registration is open. Registration for the keynote, panels, and exhibits is free.
For the latest updates regarding the conference and expo, please visit the website.
DVCon Japan 2023 will be held on June 22, 2023 at Kawasaki City Industrial Promotion Hall.
The first DVCon Japan was held in June 2022, with online and on-demand streaming. We would like to thank the many people who attended and participated in the conference. We were able to provide a wide variety of content with a variety of paper presentations and tutorial sessions. At the same time we could add a new page in the 30+ year history of DVCon worldwide. We would like to thank all the participants, presenters, sponsors, and all those involved.
DVCon Japan 2023 is planned to be held in-person. Focusing on the extremely important issue of functional verification, the conference will cover a wide range of topics including IEEE standards such as SystemVerilog, UVM, UPF, and the Portable Test and Stimulus Standard, formal verification methodologies, analog/mixed-signal, IP-XACT, and so on. We also would like to invite you to join us for discussions including functional safety and security. It is a good opportunity to network with other attendees, presenters, sponsors, and Accellera representatives.
Designers, Engineers, and Managers are encouraged to participate in paper presentations, tutorials, panel discussions, and exhibits. I hope to see you in DVCon Japan!
DVCon Japan 2023 General Chair
The Call for Papers is now available and the deadline for submissions is March 31.
For more information on DVCon Japan, visit the conference website.
DVCon Europe 2022
DVCon Europe was held in Munich in early December with strong growth in attendance. Registrations were higher than for the last in-person conference and exhibition in 2019. Attendees came from 115 different companies, up from 111 in 2019, and represented 36 countries (32 in 2019).
Highlights from the program included well-attended tutorials on standards development and best practices in functional safety, IP-XACT, and UVM. Attendees were happy to be back in-person this year, as General Chair Sumit Jha explained, “Meeting in-person after a gap of three years was exciting, and this was a lively show with enthusiastic networking.”
The award for Best Paper went to a team from Samsung, India, for their paper, “A Generic Configurable Error Injection Agent for On-Chip Memories.”
Save the date! DVCon Europe 2023 will be the 10th anniversary of the conference. It will be held in Munich November 14-15, followed by the SystemC Evolution Day on November16.
For more information on the upcoming conference, including some videos from DVCon Europe 2022, visit the conference website.
The seventh annual SystemC Evolution Day was held on December 8th in Munich. The main theme this year was Evolution and Ecosystem, to discuss the recent SystemC developments as well as explore the use of SystemC in other system modeling and simulation environments. The event started with an update on the standardization in the IEEE P1666 SystemC Working Group, which is finalizing the next revision of the SystemC standard, by giving a sneak preview into the proposed language definitions and updates of the SystemC standard. A reoccurring theme at the SystemC Evolution Day is the need to support distributed SystemC simulations, and the community discussed how to make this happen. A panel in the afternoon covered the topic of Federated Simulation, and the role of SystemC in this.
For more information on SystemC Evolution Day and SystemC Evolution Fikas, including past presentations, visit here.
Save the date! SystemC Evolution Day 2023 will be held following DVCon Europe on November 16.
Accellera has hundreds of videos available on-demand from past conferences and other events. Visit Accellera’s Vimeo site for the complete listing. You can also access papers, posters, presentations, and videos from a specific DVCon conference in the U.S., Europe, India, & China here.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in almost 158,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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