Community Newsletter: November 2016
IN THIS ISSUE:
- Message from the Chair
A fond farewell from Shishpal Rawat
- Design and Verification Conference and Exhibition around the Globe
Accellera expands DVCon to four countries
- Working Group Member Highlight
UVM WG officers commended for their service
- Portable Stimulus Tutorial Webinar
Three-part series begins January 19
As we move into 2017, I will have served as Accellera chairperson for the past six and a half years. As I have recently retired from Intel, I will no longer be serving on the Accellera board of directors beginning 2017. It has been a wonderful experience working with many talented technical teams and management executives from semiconductor and EDA companies. Accellera is a volunteer-led organization and has served the industry well since its inception. I am proud to have participated in its evolution.
During this period Accellera membership has grown almost 60% even though the semiconductor industry has gone through several phases of consolidation. Accellera members have achieved many milestones including:
- Consolidation with other standards bodies, namely the mergers with OSCI and The SPIRIT Consortium, and the acquisition of the OCP standard
- Maturing of UVM and continuing to drive it toward IEEE standardization
- Finalizing the Verilog AMS standard and moving it toward a unified umbrella under the SystemVerilog AMS standard
- Extending our relationship with the IEEE Standards Association's IEEE Get Program whereby the public has access to view and download current EDA standards at no charge courtesy of Accellera
- Establishing Apache 2.0 as the license of choice for all Accellera supplemental materials, which in turn required all SystemC contributions to be relicensed
- Initiating a big push for a Portable Stimulus standard which has made significant strides since work began a couple of years ago
There are numerous other standardization efforts — too many to mention here — that have benefited the electronics industry.
And last but not least, we have expanded DVCon to several international locales (Europe and India in 2014 and upcoming in China in 2017). These international efforts allow us to bring standards usage and methodologies to local practicing engineers who would find it difficult, if not impossible, to travel to and participate in DVCon U.S. It has been exciting to watch the conferences grow, proof that we are filling a need in these regions for the technical program that DVCon provides.
Best wishes for the upcoming holidays, 2017 and the years beyond. It has been my pleasure and an honor to serve as your chair.
Shishpal Rawat, Accellera Systems Initiative Chair
With the Design and Verification Conference and Exhibition (DVCon) now in four countries on three continents, practicing engineers around the world have access to the in depth technical program that DVCon is known for and attendees have come to rely on. Each conference is tailored to its specific region with involvement from local companies.
In their third year, DVCon India and DVCon Europe have established themselves as must-attend conferences in their countries.
DVCon India was held in Bangalore in September with almost 440 attendees over the two-day event. There were local start-ups participating and exhibiting for the first time, further demonstrating the local focus and interest in each conference. "DVCon India rightly promotes the four C's: connect, contribute, collaborate, and celebrate," stated Gaurav Jalan, DVCon India General Chair. The two-day event was inaugurated with a traditional lamp-lighting ceremony and welcome remarks by Jalan. Dr. Walden Rhines, Chairman and CEO of Mentor Graphics, and Professor Kamakoti Veezhinathan, Indian Institute of Technology Madras, delivered the keynotes.
DVCon Europe was held in October in Munich and enjoyed an increase in attendance of 20% over the previous year. Attendees of the two-day conference included representatives from 93 companies and organizations from 25 countries. Insightful keynotes were delivered by Hobson Bullman, General Manager of ARM's Technology Services Group, and Jugen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors. Bob Smith, Executive Director of the ESD Alliance, gave the keynote at the gala dinner. "It's fantastic to see this event continuing to do so well, meeting a clear need for a European forum that provides practical, detailed information on state-of-the-art development methodologies," noted Oliver Bell, DVCon Europe General Chair. "This year's conference was particularly exciting with three dynamic keynote speeches, overwhelming tutorial and paper submissions, and a vibrant exhibition. Now that DVCon Europe is established as the must-attend event in Europe for engineers to upgrade their skills, we are looking forward to an even larger event in 2017."
DVCon U.S. will be held February 27 - March 2, 2017 at the DoubleTree in San Jose, California. Early registration will open and the program will be available online on December 8th, so mark your calendars! "DVCon U.S. 2017 planning is well underway and the program is taking shape," commented Dennis Brophy, DVCon U.S. General Chair. "We look forward to a compelling and in-depth technical program full of engaging content that practicing design and verification engineers, managers and EDA tool suppliers have come to depend on from DVCon." The four-day program offers attendees an Expo, two exciting standards-focused panels and numerous informative papers, tutorials and posters to choose from. Accellera Day starts the conference on Monday and will devote the entire morning to a tutorial on Accellera's emerging Portable Stimulus standard titled "Creating Portable Stimulus Models with the Upcoming Accellera Standard," with two afternoon tutorials: "SystemC Design and Verification – Solidifying the Abstraction above RTL" and "Introducing IEEE P1800.2 – The Next Step for UVM."
In its first year, DVCon China 2017 will premier as a one-day event in Shanghai on April 17, 2017. The steering committee is in the process of analyzing a number of excellent paper abstract submissions for its inaugural program. The call for tutorials is still open, with a deadline of December 1, 2016. "Ideas, networking, technical discussions, learning opportunities and exciting exhibits of new products and services. This is what DVCon China will offer to attendees," stated Andy Liu Hongliang, DVCon China General Chair. "Many hot areas of ASIC design and verification such as UVM, Low Power, IP Reuse, Formal, Mixed-Signal, System Design and Debug Strategies will be distributed throughout the whole conference with lectures, discussions, presentations and demos."
We look forward to another exciting year of bringing DVCon to a region near you. We hope to see you in Bangalore, China, Munich or the U.S. in 2017!
The Universal Verification Methodology (UVM) Working Group has accomplished a great deal since it was first established in April 2008. Thanks to a dedicated team led by co-chairs Thomas Alsop, Intel, and Hillel Miller, Synopsys, UVM 1.2 was contributed to the IEEE in 2015, and balloting is currently underway to approve UVM as the new IEEE 1800.2 Standard for Universal Verification Methodology Language Reference Manual. The goal of the UVM standard is to improve design productivity by making it easier to verify design components with a standardized representation that can be used with various verification tools, helping to lower verification costs and improve design quality. UVM Standard version 1.0 was released in 2011, and version 1.2 was released in 2014.
In addition to Tom and Hillel, significant contributors to the UVM Working Group include Adam Sherer, Cadence, who was secretary of the UVM Working Group from 2008 to 2014, and Christeen Gray, AMD, who took over as secretary in 2014 and continues in that role today.
"Without the guidance and leadership of co-chairs Tom and Hillel and their dedicated working group members, UVM would not have moved forward as quickly as it has," stated Karen Pieper, Accellera Technical Committee Chair. "We have been fortunate to have them both at the helm, and I want to extend my sincere thanks to them for their years of dedication to the evolution of the UVM standard. It is with great gratitude that I wish them well as they move from co-chairs of the UVM Working Group to focus their efforts on the IEEE P1800.2 Working Group. I would also like to thank Adam and Christeen for their years as secretary of the working group and dedication to the advancement of UVM. They played a critical role in handling the day-to-day business of running such an important working group."
We are excited to announce a three-part webinar series on Portable Stimulus coming in January 2017. Save the dates of January 19, January 26 and February 2 at 8:00am PT. Each webinar will last approximately 45 minutes including Q&A.
Portability of reusable test cases has long been a goal for semiconductor verification and validation teams. No one wants to "reinvent the wheel" by having to rewrite similar tests again and again. The widely accepted Accellera Universal Verification Methodology (UVM) standard enables reuse of testbench components and constrained-random tests at the IP (block) level; however, limitations in terms of reuse at subsystem and full-chip level and lack of portability across execution platforms required a fresh look at addressing the portable stimulus and test challenge. The upcoming Accellera portable test and stimulus standard (PSS) specification will permit the creation of a reusable model for a variety of users across different levels of integration under different configurations. This model will enable the generation of different test implementations for multiple execution platforms, including IP simulation, full system-on-chip (SoC) simulation, emulation, FPGA prototyping and silicon. With such a standard in place, EDA vendors can produce tools that automatically generate stimulus, results checks and coverage metrics tuned for a particular target platform.
Our webinar series will be presented in 3 parts:
Part 1: January 19 at 8:00am PT. "Motivation for a Standard and PSS Enabling Automation."
In this presentation, attendees will learn why Portable Stimulus is needed to augment chip verification and validation and how the upcoming Accellera standard intends to fill this gap. Core Portable Stimulus concepts will be introduced.
Part 2: January 26 at 8:00am PT. "Capturing Complex Use Cases and Test Generation across Platforms."
In this presentation, attendees will learn how to assemble the Portable Stimulus building blocks into complex use-case scenarios that reflect real-world applications of the chip in end products and how these scenarios can be realized on different implementation platforms.
Part 3: February 2 at 8:00am PT. "Complementing PSS Models with Portable Hardware/Software Interface and Defining Coverage in PSS."
In this presentation, attendees will learn how to generate tests that cross the HW/SW interface and how to measure coverage and achieve coverage goals for all PSS tests.
Registration for these informative webinars will open two weeks prior to each event and will be posted on the Accellera website. If you would like to receive an email with registration information prior to each webinar, please register your email address.
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Copyright 2016 Accellera Systems Initiative