Community Newsletter: February 2024



Message from the Chair

Lu Dai, Accellera Systems Initiative ChairAlready in its second month, 2024 is off to a great start at Accellera.

We have a lot of exciting news coming from our working groups. The Clock Domain Crossing Working Group will be releasing the first draft of its standard for public review in the coming weeks, with multiple drafts to follow. This is a big step forward for a group that was formed just a year ago. Additionally, the Verilog-AMS 2023 standard has just been approved by the Board of Directors. An announcement with details is coming soon. The SystemC 3.0.0 Reference Implementation and UVM 3.0 Reference Implementation are on the cusp of release, and the SystemC Verification Working Group is also close to a new beta release.

On the horizon is Portable Test and Stimulus Standard 3.0 and UVM-MS 1.0. Stay tuned as we get closer to releasing these standards. And in case you missed it, we announced the new SystemVerilog Mixed-Signal Interface Types (MSI) Working Group last week. The new working group is a continuation of the MSI efforts of the IEEE 1800 Working Group. The Accellera working group has taken the baton with the goal to release a standard by the end of the year.

In other noteworthy news, I’d like to announce Frederic Doucet of Qualcomm as the new Chair of the SystemC Synthesis Working Group. We look forward to his leadership and expertise in advancing the SystemC Synthesis standard. Furthermore, we are currently accepting applications for our annual Stanley J. Krolikoski Scholarship for Electrical Engineering and Computer Science students. If you know of a deserving student who would benefit from this opportunity, please share the information with them.

We invite you to join us at DVCon U.S. 2024 next month in San Jose. We have presentations from six of our working groups as well as a luncheon focused on Federated Simulation with a special guest from Ford Motor Company. More information can be found in this newsletter.

I hope to see you and your colleagues at DVCon U.S.

Lu Dai, Accellera Systems Initiative Chair


Working Group Update

Accellera Forms New SystemVerilog Mixed-Signal Interface Types Working Group

The Board of Directors recently approved the new SystemVerilog Mixed-Signal Interface Types (SystemVerilog MSI) Working Group.

The focus of the new working group is to document a SystemVerilog-compatible language extension to permit interconnect, conversion, and resolution among dissimilar net types in SystemVerilog, including bidirectional connections.

The new working group will be chaired by Tom Fitzpatrick, who is also Chair of the UVM-MS and IEEE Std 1800 Working Groups; the working group will be co-chaired by Peter Grove, who is also the SystemVerilog-AMS Working Group Chair and UVM-MS Co-chair.

“Our goal is to release this new standard as an addendum to IEEE Std. 1800™-2023,” stated Fitzpatrick. “Vendors will be able to rely on this new standard to implement the functionality quickly to provide users a reliable platform with which to model and simulate complex mixed-signal design and verification environments.”

“We expect this new functionality to enable the SystemVerilog-AMS standard to bypass some limitations that were present in Verilog-AMS,” added Grove.

The first meeting of the new working group is planned for mid-March. For more information on the SystemVerilog MSI Working Group visit the working group page. If you are not already an Accellera member and are interested in joining to participate in the working group and the ongoing development of the standard, visit here.


The Stanley J. Krolikoski Scholarship for Electrical Engineering and Computer Science Students is Now Accepting Applications

The scholarship was established to honor our long-time friend and colleague, Stan Krolikoski, who was an Accellera Director and Board member for 22 years. He retired from Cadence Design Systems in 2021 as a Fellow. The $1,500 scholarship will be awarded each year to one undergraduate or graduate student. Students can reapply each year. Applications for the 2nd annual scholarship will be accepted through March 30, and the recipient will be notified by May 1.

For more information, including a list of requirements and an application, visit here.


Accellera Activity at DVCon U.S. 2024

DVCon U.S. 2024We hope to see you during DVCon U.S. March 4-7 in San Jose, California. Accellera working groups have a lot to share during the conference and exhibition. For more information on the conference program and to register, visit the DVCon U.S. website.

Accellera Luncheon Focused on Federated Simulation

Monday, March 4, 12:30-1:30pm

Join Accellera for an informative luncheon focused on the efforts and direction of the Federated Simulation Standard Proposed Working Group (FSS PWG). The luncheon will begin with an update on Accellera working group activity from Chair Lu Dai, followed by the presentation of a Distinguished Service Award to a long-time friend of Accellera.

Mark Burton, the FSS PWG Vice Chair will then discuss the intent of the PWG and what attendees can look forward to from the potential standard. He will be joined by Yury Bayda, Principal Software Engineer at Ford Motor Company, who will discuss how such a standard will be beneficial to Ford. The PWG was formed in September 2023 to identify industry interest in developing a standardized communication interface to enable interoperability of virtual modeling, simulation, and integration throughout the product lifecycle. The intent of this communication standard is to facilitate the creation of a distributed and orchestrated (“federated”) multi-domain simulation framework, compatible with and complementary to existing approaches used in different industries and sectors. We hope you’ll join us!

Portable Stimulus Tutorial: “Efficient Portable Programming Sequence Development with PSS”

DVCon U.S. 2024 Preview from Martin Barnasconi

Martin Barnasconi, Accellera Technical Committee Chair, gives a brief description of the Accellera activities attendees can look forward to.

Monday, March 4, 9am-12:30pm

Bringing a SoC-level system out of reset into an operational state involves configuring the component subsystems and IPs by properly programming hundreds or thousands of IP registers. Running behavior involves programming yet more registers and in-memory descriptors. Stake holders, including block-DV, subsystem, SoC verification, and silicon bring-up teams, rely on having early access to accurate programming sequences in order to shift-left their activities. Many of these stakeholders also depend on being able to efficiently modify/adjust the programming sequences to exercise different legal configurations and operations.

Current approaches to deriving bring-up sequences often require block-level teams to create some C code that captures key register-programming sequences to hand off to subsystem and SoC teams. Creating this content is an extra task that the block-level team would not normally perform and is often deferred until late in the verification cycle. This limits the ability of subsystem and SoC teams to shift-left their activities. The programming sequences are typically highly directed and cannot be easily modified to exercise different scenarios. Finally, because creating C-code programming sequences is disconnected from the primary work of a block-level design and verification team, they are at high risk of becoming outdated.

This tutorial will also provide an overview of the PSS features in development for PSS 3.0, as well as an introduction to the PSS methodology library currently under development by the working group.

IP-XACT Workshop: “An Introduction to IP-XACT”

Monday, March 4, 9:00-10:30am

This workshop will explain basic usage of IP-XACT IEEE 1685-2022 for IP reuse and integration flows as well as the data model underlying the standard. The SoC data model unifies logical and physical connectivity as well as memory map and registers; this unification enables the standard to be used as a single source of truth to automate large parts of SoC front-end design and verification flows.

During the workshop, presenters will address IP-XACT concepts that are relevant to understand the overall SoC data model, such as components, design and design configurations, bus and abstraction definition, component memory maps and registers, component address spaces and bus interface bridges, and type definitions.

CDC Workshop: “Hierarchical CDC and RDC Closure with Standard Abstract Models”

Monday, March 4, 11:00am-12:30pm

As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This workshop will cover the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. Presenters will then discuss the hierarchical CDC/RDC verification methodology, the tradeoffs faced when incorporating units from multiple sources, and the challenges when integrating multiple vendor-generated abstracted blocks into an encompassing design. To mitigate these issues, the workshop will highlight the CDC standard and summarize the status of the current efforts.

Functional Safety Workshop: “Whitepaper Review and What’s Next”

Monday March 4, 1:30-3:00pm

The implementation of Functional Safety standards such as ISO26262 poses challenges during the exchange and integration of functional safety data between different work products and activities, carried out by different teams and/or different layers of the supply chain. Automation with EDA tools is now common practice in this field, but interoperability is still challenged by the lack of a Functional Safety standard that supports the data exchange. The Accellera Functional Safety Working Group has recently completed a white paper that describes the approach taken to develop the data model and a corresponding language prototype that will enable Functional Safety data exchange. As a next step, the focus for the working group is to develop the Language Reference Manual (LRM) for the Functional Safety standard. This session will review the content of the white paper and discuss the plans to proceed with the LRM.

UVM Workshop: “An Update on New Features and Open Q&A”

Monday, March 4, 3:30-4:15pm

The Accellera UVM Working Group released the IEEE 1800.2-2020-2.0 reference library last year. Since that release, the group has been working on a public GitHub repository to give users enhanced access to the latest bug fixes and to provide bug fix suggestions. The working group has also developed new, additive features to poll an arbitrary DUT signal and to recover appropriately when a process (e.g., a sequence) is terminated abruptly, such as by a “disable fork.” During the workshop, presenters will provide details of the new features and explain the plan to interact with users via the public repository. There will be generous time for Q&A.

SA-EDI Workshop: “A Practical Guide to SA-EDI Methodology”

Monday, March 4, 4:15-5:00pm

This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) standard. This guidance is planned to be documented in the IEEE P3164 Asset Identification whitepaper.

The SA-EDI standard relies heavily on the accurate identification of assets within an IP. Any errors, either false positives or negatives, can render the SA-EDI collateral ineffective or non-applicable. Therefore, it's essential not only to identify assets but also to classify them correctly. However, this is not as straightforward as one may think. Contextual information of the IP’s integration, such as security requirements, use cases, surrounding IPs, etc., are often needed in order to properly identify assets. These are typically defined by the integrated circuit (IC) owner and well after the IP has been developed, which is when the SA-EDI collateral needs to be produced.

To address these challenges, the whitepaper introduces a methodical and practical approach that can be applied by IP owners with limited experience in security practices. The methodology is vetted using four example IPs, ranging from simple to complex, to highlight how an IP developer can use them to produce accurate SA-EDI collateral for the IC owner to properly consume and apply. Don't miss this opportunity to enhance your knowledge in security.

Want to Learn More from Past Conferences?

For inspiration ahead of DVCon U.S. 2024, visit the archives to view presentations from past DVCon conferences around the globe.


Additional Events

DVCon Europe 2024 Call for Contributions

DVCon Europe 2024The 11th annual DVCon Europe will be held October 15-16 at the Holiday Inn – Munich City Centre. We invite you to share your expertise by submitting proposals for Engineering Papers, Tutorials and Panels. The deadline for submission is April 22, 2024. More information and guidelines can be found here.

Due to the tremendous success of the Research Track introduced in 2023, the conference is seeking contributions for research papers again this year. The deadline to submit a full research paper is July 1, 2024. More details regarding solicited topics and submission guidelines can be found here.

For the latest information on DVCon Europe 2024, visit the website.

SystemC Evolution Fika

SystemC Evolution FikaThe next SystemC Evolution Fika will be held February 29 from 16:00-18:00 CEST. These virtual workshops are referred to as Fikas to honor the Swedish tradition of sharing a coffee, slowing down a bit, and talking about things the participants care about.

To register for the free SystemC Fika, visit here.

For the most up-to-date information and to view presentations from past fikas, visit the SystemC events page.


IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 175,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.


Accellera Global Sponsors

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