Accellera Taiwan Forum for
System Level Verification & Design

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Photos from the Accellera Taiwan Forum 2017The 2016 movie "Passengers" portrays a future of space travel. Sleeping in a dormant state for 120 years, the crew and passengers journey through the universe relying on a spacecraft entirely controlled by artificial intelligence. One can barely imagine the scale of effort in design and verification that would need to be conducted before such machines could ever be trusted by humans. Obviously today we see only the slim light of dawn of the massive applications of AI. We are already getting a glimpse into the near future with the Tesla autopilot vehicles and the AlphaGo’s winning streaks over human masters. As such, the Accellera Taiwan Forum for System Level Verification and Design looks into technologies flourishing in the past five years that have pushed the success of multiple-core SoC and are now pushing the progress of the IoT, fog computing and edge computing.

This Forum is a unique event in Taiwan. Major EDA vendors work together to introduce current status and trends in IC verification and design technologies. Attendees can learn from the combined know-how of the EDA industry. Dennis Brophy, Vice Chair of Accellera, will give an update to Accellera's ongoing standards work. Dr. Kazutoshi Wakabayashi, a well-known figure in the Japan industry and academy, illustrates how Japan professionals and researchers utilize High Level Synthesis to realize IoT and AI applications in FPGA. Three tutorials are featured to introduce the latest concepts and technologies in SoC verification, high level synthesis and the currently developing standard for portable stimulus. A special session by major EDA vendors will provide a look at unique methodologies in IC design and verification.

The event was held:
April 21, 2017
9:00am - 5:30pm
Ambassador Hotel Hsinchu, Room 10F
188 Section 2, Chung-Hwa Road, Hsinchu City

Organized by:
Alan P. Su, PhD
Adjunct Associate Professor
EE Dept., NCKU


 Taiwan Forum 2017 Program


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