Accellera Systems Initiative to Honor Shrenik Mehta with the 2016 Leadership Award
Synopsys's Mehta recognized for his significant role in Accellera's growth worldwide
Elk Grove, Calif., May 31, 2016 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that Shrenik Mehta is the recipient of the fifth annual Accellera Leadership Award. The award recognizes Shrenik's vision, leadership and contribution to standards development, governance and promotional activities on behalf of the organization. The award will be presented at the Design Automation Conference (DAC) during the Accellera breakfast and town hall meeting on Tuesday, June 7.
"Shrenik was a founding board member of Accellera, and his leadership had a tremendous impact on Accellera," stated Shishpal Rawat, Accellera Systems Initiative chair. "He was instrumental in the merger between VHDL International (VI) and Open Verilog International (OVI) to create what was to become Accellera, and over the following ten years helped grow membership, develop new Accellera and IEEE standards, and lead the merger of The SPIRIT Consortium. I am grateful for his contributions to Accellera and am proud to bestow him with this award."
"I am deeply honored to receive this prestigious award from Accellera," stated Shrenik Mehta, Strategic Programs Director at Synopsys. "Accellera standards have transformed system-on-chip (SoC) design and verification methods worldwide and have enabled engineer productivity benefits to semiconductor, systems, EDA and IP companies. I would like to thank all the individuals and companies who have contributed to these standards."
Shrenik has more than 30 years of semiconductor and system industry experience. In addition to being a founding board member of the Accellera Organization in 2000, he was also vice chair from 2002-2005 and chair from 2005-2010. He is a current member of the Accellera Promotions Committee and an active participant in the Portable Stimulus Working Group. Shrenik helped guide several initiatives within Accellera that evolved into widely-used standards such as SystemVerilog, Unified Power Format (UPF) and Universal Verification Methodology (UVM). He was also vice chair of the IEEE 1800-2005 Standard for SystemVerilog Committee. In addition, Shrenik is member of the US Technical Advisory Group - ISO26262 TC32/SC22/WG8 Functional Safety Working Group.
Shrenik received his master's degree in Computer Engineering from University of Michigan, Ann Arbor, and bachelor's degree from Indian Institute of Technology, BHU, Varanasi, India. He holds nine US patents and one patent in Taiwan.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera. Accellera Global Sponsors are: Cadence, Mentor Graphics and Synopsys.
Accellera and Accellera Systems Initiative are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.