--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  testchip_core_rtl
--* Filename & Ext  :  testchip_core_c.vhdl
--* Author          :  David W. Bishop
--* Created         :  8/21/97
--* Version         :  1.1
--* Revision Date   :  97/12/03
--* SCCSid          :  1.1 12/03/97 testchip_core_c.vhdl
--* WORK Library    :  testchip
--* Mod History     :  Configuration for Simulation only.
--* Description     :  Main level configuration for testchip
--* Known Bugs      :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
configuration testchip_core_rtl of testchip_core is
  for rtl
    for all : test_counter
      use entity work.test_counter ( rtl );
    end for;
    for all : test_add
      use entity work.test_add ( rtl );
    end for;
    for all : test_reg
      use entity work.test_reg ( rtl );
    end for;
    for all : test_shift
      use entity work.test_shift ( rtl );
    end for;
    for all : test_state
      use entity work.test_state ( rtl );
    end for;
    for all : test_multpipe
      use entity work.test_multpipe ( rtl );
    end for;
    for all : test_parity
      use entity work.test_parity ( rtl );
    end for;
  end for;
end testchip_core_rtl;