--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  TEST_TRISTATE
--* Filename & Ext  :  test_tristate.vhdl
--* Author          :  David W. Bishop
--* Created         :  June 5, 1996 
--* Version         :  1.2
--* Revision Date   :  96/06/17
--* SCCSid          :  1.2 6/17/96 test_tristate.vhdl
--* WORK Library    :  chiptest
--* Mod History     :  
--* Description     :  Example Tristate bus with pullup.
--* Known Bugs      :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity test_tristate is
  generic ( width : integer := 17 );
  port ( en1, en2, en3    : in  std_ulogic;
         inp1, inp2, inp3 : in  std_logic_vector ( width downto 0);
         tribus           : out std_logic_vector ( width downto 0) );
end test_tristate;

architecture rtl of test_tristate is
begin  --  rtl

  tribus <= inp1 when (en1 = '1') else
            (others => 'Z');
  tribus <= inp2 when (en2 = '1') else
            (others => 'Z');
  tribus <= inp3 when (en3 = '1') else
            (others => 'Z');
  tribus <= ( others => 'H' );          -- pullup

end rtl;