--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  Test_Shift
--* Filename & Ext  :  test_shift.vhdl
--* Author          :  David Bishop <dbishop@vhdl.com>
--* Created         :  1999/03/12
--* Version         :  1.2
--* Revision Date   :  00/12/08
--* SCCSid          :  1.2 12/08/00 test_shift.vhdl
--* WORK Library    :  testchip_lib
--* Description     :  Simple shift register, parameterizable
--* Known Bugs      :
--*                 :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_shift is
  generic ( width : integer := 17 );
  port ( clk   : in  std_ulogic;
         reset : in  std_ulogic;
         load  : in  std_ulogic;
         en    : in  std_ulogic;
         inp   : in  std_logic_vector ( width downto 0 );
         outp  : out std_ulogic );
end test_shift;

architecture rtl of test_shift is
  signal shift_reg : unsigned ( width downto 0 );
begin

  outp <= shift_reg (shift_reg'high);

  shifter : process ( clk, reset )
  begin
    if ( reset = '0' ) then
      shift_reg <= (others => '0');
    elsif rising_edge ( clk ) then
      if (load = '1' ) then
        shift_reg <= unsigned (inp);
      elsif ( en = '1' ) then
        shift_reg <= rotate_left ( shift_reg, 1 );
      end if;
    end if;
  end process shifter;

end rtl;