--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  TEST_REG
--* Filename & Ext  :  test_reg.vhdl
--* Author          :  David W. Bishop X-66788
--* Created         :  06/05/96 
--* Version         :  1.2
--* Revision Date   :  98/05/07
--* SCCSid          :  1.2 05/07/98 test_reg.vhdl
--* WORK Library    :  chiptest
--* Mod History     :  
--* Description     :  Simple test for Register and MUX inference.
--* Known Bugs      :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

library ieee;
use ieee.std_logic_1164.all;

entity test_reg is
  generic ( width : integer := 17 );
  port ( clk        : in  std_ulogic;
         reset      : in  std_ulogic;
         enable     : in  std_ulogic;
         sel        : in  std_ulogic;
         inp1, inp2 : in  std_logic_vector ( width downto 0);
         outpt      : out std_logic_vector ( width downto 0) );
end test_reg;

architecture rtl of test_reg is
  -- Temporoary variable needed for outptx because you can't read an
  -- output port.
  signal inpx, outptx : std_logic_vector ( width downto 0);
begin  --  rtl

  -- Assign the temporary output to the primary output
  outpt <= outptx;

  -- Lets put a mux in front of the register
  inpx <= inp1 when sel = '1' else
          inp2 when sel = '0' else      -- This "when" clause not necessary
          (others => 'X' );             -- "X" claus ignored in Synthesis.

  -- Register with a reset and an Enable, feeding back the output
  regis : process ( clk, reset )
  begin
    if reset = '0' then
      outptx <= ( others => '0');
    elsif rising_edge ( clk ) then
      if enable = '1' then
        outptx <= inpx;
      else
        outptx <= outptx;
      end if;
    end if;
  end process regis;

end rtl;