--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  Test_Gates
--* Filename & Ext  :  test_gates.vhdl
--* Author          :  David W. Bishop
--* Created         :  $Date$
--* WORK Library    :  ASICNAME
--* Description     :  Simple code to create a bunch of gates
--* Known Bugs      :
--*                 :  
--* RCS Summary     :  $Id$
--*                 :
--* Mod History     :  $Log$
--*                 :
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
library ieee;
use ieee.std_logic_1164.all;

entity Test_Gates is
  
  port (A, B, C, D, E, F : in  std_ulogic;   -- Simple inputs
        X, Y, Z          : out std_ulogic);  -- Simple outputs

end Test_Gates;

-- purpose: Behavioral discription of a bunch of gates
architecture RTL of Test_Gates is
  -- you can't re-use and output!  So you need to create local versions
  signal local_Y       : std_ulogic;    -- Local version of Y
  signal I, J, K, L, M : std_ulogic;    -- Internal signals
begin  -- RTL
  -- OR gate
  I <= A or B;
  -- and gate
  J <= B and C;
  -- Xor gate
  K <= C xor D;
  -- nand gate
  L <= not ( D and E );
  -- MUX (done as a signal assignment)
  Z <= I when ( F = '1') else
       J;
  -- MUX (done in a process statment)
  MUX2 : process (K, L, A)

  begin  -- process MUX2
    if A = '1' then
      M <= K;
    else
      M <= L;
    end if;
  end process MUX2;

  -- A Flip Flop
  -- purpose: Simple FF with no reset
  -- type:    memorizing
  -- inputs:  F
  -- outputs: local_Y
  FF1 : process (F)

  begin  -- process FF1
    -- activities triggered by rising edge of clock
    if rising_edge(F) then
      local_Y <= E;
    end if;
  end process FF1;
  Y <= local_Y;


  -- A latch done as a process statment
  -- purpose: A latch done as a process statment
  -- type:    memoryless
  -- inputs:  F
  -- outputs: X
  LATCH2 : process (F, M)

  begin  -- process LATCH2
    if ( F = '1' ) then
      X <= M;
    end if;
  end process LATCH2;
end RTL;