--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  TEST_CLKGEN
--* Filename & Ext  :  test_clkgen.vhdl
--* Author          :  David W. Bishop
--* Created         :  8/21/97
--* Version         :  1.2
--* Revision Date   :  97/12/04
--* SCCSid          :  1.2 12/04/97 test_clkgen.vhdl
--* WORK Library    :  testchip
--* Mod History     :  
--* Description     :  Sample clock generator, to test hierarchy and durived
--*                 :  clocks.
--* Known Bugs      :  
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Test_ClkGen is
  port ( clk   : in  std_ulogic;
         reset : in  std_ulogic;
         dclk  : out std_ulogic );
end Test_ClkGen;

architecture RTL of Test_ClkGen is

  component test_counter
    generic ( width : integer := 17 );
    port ( clk    : in  std_ulogic;
           reset  : in  std_ulogic;
           enable : in  std_ulogic;
           count  : out std_logic_vector ( width - 1 downto 0) );
  end component;

  signal count   : unsigned ( 2 downto 0 );
  signal count_i : std_logic_vector ( count'high downto 0 );
  signal dclk_i  : std_ulogic;
  signal VCC     : std_ulogic;
begin  -- RTL

  VCC   <= '1';
  dclk  <= dclk_i;
  count <= unsigned ( count_i );
  U1 : Test_Counter
    generic map ( width => 3 )
    port map (
      clk    => clk,
      reset  => reset,
      enable => VCC,
      count  => count_i );

  clkreg : process ( clk, reset )
  begin
    if reset = '0' then
      dclk_i <= '0';
    elsif rising_edge (clk) then
      if count = 16#07# then
        dclk_i <= not dclk_i;
      end if;
    end if;
  end process clkreg;
  
end RTL;