--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  Test_Bidir
--* Filename & Ext  :  test_bidir.vhdl
--* Author          :  David Bishop  <bishop@mithril>
--* Created         :  1998/05/07
--* Last modified   :  $Date$
--* WORK Library    :  ASICNAME
--* Description     :  Example of how to write a bidirectional buffer
--* Known Bugs      :
--*                 :  
--* RCS Summary     :  $Id$
--*                 :
--* Mod History     :  $Log$
--*                 :
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
library ieee;
use ieee.std_logic_1164.all;

entity Test_Bidir is
  generic (width : natural := 15);      -- Width of buffer
  port (Data_In  : in    std_logic_vector ( width downto 0 );  -- input data
        Data_Out : out   std_logic_vector ( width downto 0 );  -- Output data
        Data     : inout std_logic_vector ( width downto 0 );  -- Bidirectional pin
        OE       : in    std_ulogic);   -- Output Enable

end Test_Bidir;

-- purpose: RTL discription of a Bidirectional buffer
architecture RTL of Test_Bidir is

begin  -- RTL
  -- Drive the Bidirectional port
  Data <= Data_in when ( OE = '1' ) else
          ( others => 'Z' );
  -- Read the Bidirectional port
  Data_out <= Data;
end RTL;