--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  test_add
--* Filename & Ext  :  test_add.vhdl
--* Author          :  David Bishop  <dbishop@vhdl.org> X-XXXXX
--* Created         :  1999/03/12
--* Last modified   :  $Date: 1999-03-12 16:02:09-05 $
--* WORK Library    :  testchip_lib
--* Description     :  add to numbers and put them into a register
--* Known Bugs      :
--*                 :  
--* RCS Summary     :  $Id: test_add.vhdl,v 1.2 1999-03-12 16:02:09-05 bishop Exp $
--*                 :
--* Mod History     :  $Log: test_add.vhdl,v $
--* Mod History     :  Revision 1.2  1999-03-12 16:02:09-05  bishop
--* Mod History     :  Converted from std_logic_arith to numeric_std
--* Mod History     :
--* Mod History     :  Revision 1.1  1999-03-12 15:43:54-05  bishop
--* Mod History     :  Initial revision
--* Mod History     :
--*                 :
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_add is
  generic ( width : integer := 17 );
  port ( clk        : in  std_ulogic;
         reset      : in  std_ulogic;
         enable     : in  std_ulogic;
         inp1, inp2 : in  std_logic_vector ( width downto 0);
         sum        : out std_logic_vector ( (width + 1) downto 0) );
end test_add;

-------------------------------------------------------------------------------
--  RTL description.  Adds two inputs together (unsigned) into an integer
--  of "width + 1" in lenght.
-------------------------------------------------------------------------------

architecture rtl of test_add is
  constant terminal_count     : integer := 2**( sum'high + 1 ) - 1;
  subtype  adder_range is integer range 0 to terminal_count;
  signal   sumx, inp1x, inp2x : adder_range;
begin  --  rtl 

  sum   <= std_logic_vector( to_unsigned ( sumx, width + 2 ));
  inp1x <= to_integer ( unsigned ( inp1 ) );
  inp2x <= to_integer ( unsigned ( inp2 ) );

  adder : process ( clk, reset )
  begin
    if reset = '0' then
      sumx <= 0;
    elsif rising_edge (clk) then
      if enable = '1' then
        sumx <= inp1x + inp2x;
      end if;
    end if;
  end process adder;

end rtl;