--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * VHDL Source Code  * * * * * * * * * * * * * *
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
--* Title           :  GEN_SIGNAL
--* Filename & Ext  :  gen_signal.vhdl
--* Author          :  David W. Bishop
--* Created         :  Dec 1, 1995
--* Version         :  %I%
--* Revision Date   :  %E%
--* SCCSid          :  %I% %G% %M%
--* WORK Library    :  test_testchip_lib
--* Mod History     :  
--* Description     :  VHDL file to generate stimulous from a file and
--*                 :  feed it to a testbench.
--*                 :  This module will have to be modifed for your design.
--* Known Bugs      :
--* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

library IEEE;
use IEEE.std_logic_1164.all;
--
-- Generate stimulus signals and clock here
--

entity GEN_SIGNAL is
  generic ( INPUT_FILE : string );

  port(
    clk        : in  std_ulogic;
    slow_count : out std_logic_vector ( 4 downto 0 );
    enable     : out std_ulogic;
    load       : out std_ulogic;
    input_data : out std_logic_vector ( 7 downto 0 );
    shout      : out std_ulogic;
    control    : out std_logic_vector ( 1 downto 0 );
    count_oe   : out std_ulogic;
    count      : out std_logic_vector ( 7 downto 0 );
    sum        : out std_logic_vector ( 8 downto 0 );
    mulout     : out std_logic_vector ( 14 downto 0 );
    parity     : out std_ulogic);
end GEN_SIGNAL;

use std.textio;
library ieee;
use ieee.std_logic_TEXTIO.all;
use ieee.numeric_std.all;

architecture behavior of GEN_SIGNAL is
--    CONSTANT clk_half_period: TIME := DELAY_MULTIPLE * 25 ns; -- 20MHz

begin


  TESTER : process

    -----------------------------------------------
    --  Set the interval between data input HERE --
    -----------------------------------------------
    constant FILENAME         : string  := INPUT_FILE;  -- input file name
--  constant FILENAME       : string := "test_read.stm";  -- input file name
    file INFILE               : textio.text is in FILENAME;
    variable INLINE           : textio.line;
    variable DATA1            : std_ulogic;             -- data formats
    variable DATA2            : std_logic_vector(1 downto 0);
    variable DATA4            : std_logic_vector(3 downto 0);
    variable DATA6            : std_logic_vector(5 downto 0);
    variable DATA16           : std_logic_vector(15 downto 0);
    variable DATINT           : integer;
    variable EOF              : boolean := false;
    variable LOCAL_WORD_WIDTH : std_logic;
    variable WAIT_TIME        : integer := 0;


  begin

    INLINE := new string'("");
    -- Report an error when out of data
    if textio.endfile(INFILE) then
      EOF := true;
      --  assert not(EOF)
      --   report "OUT OF DATA"
      --   severity ERROR;
    end if;

    if not(EOF) then

      if ( WAIT_TIME = 0 ) then

        if not(EOF) then
          textio.readline (INFILE, INLINE);
        end if;

        -- If you see an empty line or a line with a "-" beginning it,
        -- then ignore it.
        while (INLINE'length = 0) or (INLINE(1) = '-') loop
          textio.readline (INFILE, INLINE);
        end loop;

        -- If you see a W as the first character on a line, read in
        -- a number from the next field and wait that many clock
        -- cycles
        if ( INLINE ( 1 ) = 'W' ) then
          read ( INLINE, DATA1 );
          textio.read ( INLINE, WAIT_TIME );
          -- X out all the outputs
          shout      <= '-';
          parity     <= '-';
          slow_count <= ( others => '-' );
          control    <= ( others => '-' );
          count      <= ( others => '-' );
          sum        <= ( others => '-' );
          mulout     <= ( others => '-' );
        else
          read (INLINE, DATA1);
          enable <= DATA1;

          read (INLINE, DATA1);
          load <= DATA1;

          textio.read (INLINE, DATINT);
          input_data <= conv_std_logic_vector ( DATINT, input_data'high + 1 );

          read (INLINE, DATA1);
          count_oe <= DATA1;

          read (INLINE, DATA1);
          shout <= DATA1;

          read (INLINE, DATA2);
          control <= DATA2;

          textio.read (INLINE, DATINT);
          count <= conv_std_logic_vector ( DATINT, count'high + 1 );

          textio.read (INLINE, DATINT);
          sum <= conv_std_logic_vector ( DATINT, sum'high + 1 );

          textio.read (INLINE, DATINT);
          mulout <= conv_std_logic_vector ( DATINT, mulout'high + 1 );

          read (INLINE, DATA1);
          parity <= DATA1;

          textio.read (INLINE, DATINT);
          slow_count <= conv_std_logic_vector ( DATINT, slow_count'high + 1 );
        end if;
      else
        WAIT_TIME := WAIT_TIME - 1;
      end if;
    end if;

    wait until ( CLK = '0' );
-- wait for (CLK_HALF_PERIOD*2.0);

  end process TESTER;

end behavior;