VHDL 200x-meeting July 7, 2004.

Attendance

John Ries 
Chuck Swart
Charlie Guy
Eric  Marschner
Jim Lewis
Carl Isnhoffer
Steve Bailey
Dave Bishop
Ryan Hilton
Deepak Pant
Ajay Varikat


An updated PSL draft proposal has been posted. Eric presented changes.  There
isn't much changed from last draft. The new draft resolve most of the
outstanding issues.  The conflict of the VHDL concurrent assertion with a PSL
assertion at time 0 has been resolved.  The resolution is in section 5a.  If the
assertion does not use temporal operators then it is a VHDL concurrent
assertion, otherwise a PSL assertion. Section 9a has a proposal to extend VHDL
identifier to deal with the trailing _ and ! character on some PSL keywords.
Eric believes that pathnames are addressed by Peter Ashenden's proposal.

PSL draft is now based on the 2002 LRM not 1993.
Section 7, allow endpoints as an expression element.
Section 9.8 resolve where equivalent processes for PSL occur.
Section  9.8.1 has comment about concurrent assertion and PSL assertion.

Section 13, lexical element changes to identifier syntax.

There are no further issues to resolve.
Reviewers need to check for the proposal for the level at which PSL is
incorporated in VHDL and for the completeness of the PSL inclusion.

There will be no further updates until a review occurs. 

Discussion of scheduling of PSL proposal review. This review
is tentative set for the first August meeting. It will include the PSL API.

Please review and generate comments before review happens.

Question from David Bishop, does PSL need the boolean equivalence proposal.
The answer is no.  PSL explicitly defines how to handle '1', '0', and meta values.
It doesn't call out for 'L' and 'H'.  The PSL LCS should map them to '0' and '1' respectively.



FT10 Condition assignment statement and ternary operator.

Jim presenting using e-mail post as outline.
 
There was a lot of discussion

One issue is fears of ambiguous grammar.  Some of this has been resolved but
have all the place been caught.  There appears to be a problem with the time
expression in waverforms. How do we catch these problems.
Proposed solution are
  1) Prototype
  2) Examine all possible places
  3) Use parenthesis around all ternary expressions.

There was an issue of consistency between concurrent condition signal assignments and
and assignments use ternary expressions.

Multiple nested ternary do not look like condition signal assignment.

Steve proposed we have a general n-ary operator or syntax.

Proposal to use ternary expression in sequential code. 
Lots of discussion on parenthesis and need or lack of needing them.


Some people, like Steve question the value for effort. Jim believes that the 
value is worth the effort.

A discussion of how the ternary operator would be used in FSM representations.

A motion for informal vote to move FT 10 from fast track to modeling and productivity
unless changes occur.

  vote called
  John Ries        yes
  Chuck Swart      yes
  Charlie Guy      yes
  Eric             yes
  Jim Lewis        no
  Carl Isnhoffer   yes
  Steve Bailey     yes
  Dave Bishop      yes
  Ryan Hilton      abstain
  Deepak           yes
  Ajay             yes

FT10 moved to modeling and productivity group.


FT18 Boolean equiv.
  
Discussion on how this interacts with PSL expressions.
Issue is if the operator is not visible in the VHDL code, does
PSL work. Does PSL use this operator itself?

Eric raised issue that this is based as overload, he proposed usage of a specification
on the type.  This does force everyone to use the boolean equivalence.  Since a number of
people want to be able disable it the forcing the equivalence may cause conflict.

Chuck wants to see normative text in the package say what it should be doing.
Proposal needs to take into account the PSL LRM. See PSL issue on type above.

Action for David Bishop update packages to reflect new overloaded operators need for this
proposal to function.  Need to have compassions operators between boolean and std_ulogic that
produce std_ulogic.  
Post meeting comment: We do have an issue here with the default equivalence operators.

Steve updated group on the vote for Jim's amendment of Peter's motion. The amended motion is
currently passing.

Future agenda items:

1) Fixed points issues
     There needs to be consensus is needed between David, Jim, and Ryan before the group
     reviews.

Next meeting?
  Monday July 11th, 2:00p.m. PST

Close of meeting