library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity varunitdelay is
  generic(wl : positive := 8; N_Delay : positive := 1;
          async_reset : boolean  := true);
  port( clk : in  std_logic;
        rst : in  std_logic := '0';
        ce  : in  std_logic := '1';
        i   : in  std_logic_vector((wl-1) downto 0);
        o   : out std_logic_vector((wl-1) downto 0)
       );
end entity varunitdelay;

architecture rtl of varunitdelay is

signal wo : std_logic_vector(o'range) := (others => '0');

begin

o <= wo;

G_T_ARST : if (async_reset = true)
  generate
    begin
      G1 : if (N_Delay = positive'low)
        generate
          signal qo : std_logic_vector(o'range) := (others => '0');      
          begin
            wo <= qo;
      
            P1 : process(clk,rst) is
              begin
                if (rst = '1') then
                    qo <= (others => '0');
                elsif rising_edge(clk) then
                  if (ce = '1') then
                      qo <= i;
                  end if;
                end if;
            end process P1;
      end generate G1;
      
      GN : if (N_Delay > positive'low)
        generate
          type slv_1d is array(natural range<>) of std_logic_vector(o'range);
          signal qo : slv_1d((N_Delay-1) downto 0) := (others => (others => '0'));
          begin
            wo <= qo(qo'high);
            
            P1 : process(clk,rst) is
              begin
                if (rst = '1') then
                    qo <= (others => (others => '0'));
                elsif rising_edge(clk) then
                  if (ce = '1') then
                      qo <= qo((qo'high-1) downto qo'low) & i;
                  end if;
                end if;
            end process P1;
      end generate GN;
end generate G_T_ARST;

G_F_ARST : if (async_reset = false)
  generate
    begin
      G1 : if (N_Delay = positive'low)
        generate
          signal qo : std_logic_vector(o'range) := (others => '0'); 
          begin
            wo <= qo;
      
            P1 : process(clk) is
              begin
                if rising_edge(clk) then
                   if (rst =  '1') then
                       qo <= (others => '0');
                   else
                     if (ce = '1') then
                         qo <= i;
                     end if;
                   end if;
                end if;
            end process P1;
      end generate G1;
      
      GN : if (N_Delay > positive'low)
        generate
          type slv_1d is array(natural range<>) of std_logic_vector(o'range);
          signal qo : slv_1d((N_Delay-1) downto 0) := (others => (others => '0'));
          begin
            wo <= qo(qo'high);
            
            P1 : process(clk) is
              begin
                if rising_edge(clk) then
                   if (rst = '1') then
                       qo <= (others => (others => '0'));
                   else
                     if (ce = '1') then
                         qo <= qo((qo'high-1) downto qo'low) & i;
                     end if;
                   end if;
                end if;
            end process P1;
      end generate GN;    
end generate G_F_ARST;

end architecture rtl;

configuration cfg_varunitdelay of varunitdelay is for rtl

  end for;
end configuration cfg_varunitdelay;