New RASSP developed CD-ROM being sold by the IEEE! The VHDL: Electronic Systems Design Methodologies and Interactive Tutorial, CD-ROM was created as part of the DARPA Rapid Prototyping of Application Specific Signal Processors (RASSP) program. The goal of the RASSP program was to dramatically improve the design process for complex digital systems, particularly embedded signal processors. A key objective was to reduce the total product development time by at least a factor of four while making similar improvements in product quality and life cycle cost. Also important was the ability to field state-of-the-art equipment at system build time and to rapidly upgrade the system throughout its life cycle. This multifaceted CD-ROM covers and links many different focus areas in Top-Down Design and includes tutorials, case studies, tools, and reference material. The CD-ROM organization allows you to start in any of these focus areas, thereby providing maximum utility in the CD-ROM. The focus areas are as follows: VHDL Tutorial -HTML sequence of course modules 10, 11, 12, 13 & 60 and labs for Unix and Windows systems. Top-Down Design Tutorial - HTML sequence of course modules 14, 29, 30, 32, 57 & 59 and labs for Unix and Windows systems. Case Studies - These real-world benchmark case studies provide an introduction to the top-down design process. Even though embedded Digital Signal Processors (DSP) are used as the delivery mechanism for the process, it can be applied to other areas. Application Notes - These application notes provide additional detail in selected technical areas that are covered in the Case Studies. They can also be used as stand-alone references. VHDL Based Acquisition - This material from the VITAMINS program covers the use of top-down design in developing requirements and performing system design, including a Sobel lab example. Course Modules-These are 18 PPT course modules which were designed to be taught in undergraduate/graduate courses. In addition, two labs covering the complete top-down process are provided. VHDL Standards- Key IEEE VHDL standards and a military handbook for VHDL design in a viewable format. IEEE Std 1029.1-1998, IEEE Standard for VHDL Waveform and Vector Exchange (WAVES) to Support Design and Test Verification IEEE Std 1076-1993, IEEE Standard VHDL Language Reference Manual IEEE Std 1076a-2000, Amendment to IEEE Std 1076-1993 IEEE Std 1076/INT-1991, IEEE Standards Interpretations: IEEE Std 1076-1987 IEEE Standard VHDL Language Reference Manual IEEE Std 1076.1-1999, IEEE Standard VHDL Analog and Mixed-Signal Extensions IEEE Std 1076.2-1996, IEEE Standard VHDL Mathematical Packages IEEE Std 1076.3-1997, IEEE Standard VHDL Synthesis Packages IEEE Std 1076.4-1995, IEEE Standard for VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification Approved draft of IEEE Std 1076.6-1999, IEEE Standard for VHDL Register Transfer Level Synthesis IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) MIL-HDBK 62, Documentation of Digital Electronic Systems with VHDL References - When possible, references listed in the material are included on the CD-ROM. This includes RASSP material as well as VIUF Conference Proceedings. VHDL Models - These are models that were developed as part of the RASSP program. The Model Section includes process and memory models. VHDL Tools - These include a VeriBest simulator, a VHDL GUI interface and a VHDL model generator. VHDL Taxonomy - This document provides a framework for classifying VHDL models to promote model reuse. Glossary - Provides definitions of terms within the context of the VHDL language, VHDL simulation, Digital Signal Processing and RASSP. Links to documents where the terms are used are included. See the IEEE Standards website for ordering information.