Subject: June VASG Meeting Minutes & Next Meeting
From: Stephen Bailey (sbailey@synopsys.com)
Date: Mon Aug 21 2000 - 13:08:30 PDT
Below are the minutes for the June (DAC) VASG meeting. Once again I thank
Paul for chairing in my absence. I've also attached the presentation that I
provided to Paul as it may be easier to read than the ASCII text below on
the VHDL 200x enhancements collection.
Next Meeting:
VHDL Workshop at FDL in Tubingen, Germany, Sep 4, 2000. Although the DASC
will be having a plenary session and other WGs will be meeting, the VASG is
relying on the Workshop as sufficient to cover all current status, issues,
etc and no separate meeting is planned. Please see the web site:
http://www.ecsi.org/ecsi/events/vhdl200x.html
Fall VIUF, Orlando, FL, Oct 16-18
I have not yet seen a schedule of meetings. I am currently planning on
holding a VASG meeting in conjunction with the Fall VIUF.
-Steve Bailey
> VASG Meeting
> LA, California
> 9 June 2000
> Paul Menchini acting for Steve Bailey
> Minutes: John Willis
>
> Agenda
> Welcome / approve agenda
> Status of VHDL 2000
> PLI Status
> VHDL 200x
> Next Meeting
>
> Status of VHDL 2000
> D3 of LRM is in review
> Possible D4 to update Annex D
> Paul addressed Bhasker's comments concerning Appendix D.
> Bhasker withdrew his objection after learning that 1076a
> was being published.
>
> Otherwise ready to ballot
> With a D4 probable submission of materials to IEEE is in July
>
> Note that there was a major problem with people not getting copies of
> balloted standard or ballots were not suitably counted. Please send
> any complaints to Paul Menchini (mench@mench.com) and Noelle Humenick
> (n.humenick@ieee.org). Noelle's address is IEEE, 445 Hoes Lane, PO
> Box 1331, Piscataway NJ 08855-1331 Phone 732.562.3818, FAX 732.562.1571.
>
> Francoise's Specification Status:
> Resolution of isses sent on reflector (ongoing)
> In progress: review and update of the draft
> handle lookup by name (reviewed, not updated)
> get object values (reviewed, updated)
> callbacks (review in progress)
> foreign models (not started)
> putting values to objects (not started)
> Next Milestones and Schedule
> Finish review
> Send first version of draft for review to VASG
> Time frame:
> Callbacks: end of June
> foreign models: end of July
> putting values: end of August
> other: end of September
> first version: end of October
> Issues
> Renew the PAR for VHDL containing VHPI
> Need publicly available standard working
> draft for early adopters
> What is the level of quality of the draft
> expected for a VASG review
>
> VHDL 200X
> ISAC status and 200x Process
> John Willis needs people to filter approximately 150 issues
> Volunteers
> Dave Barton, Paul Menchini, Steve Schultz, Greg Peterson,
> Kaba, Need EIAJ, Peter Ashenden,
> VHDL 200x User Survey Status
> Air Force 200x project funding eliminated
> Project group wanted to finish the VHDL user survey
> process that they had begun
> Initial Phase I survey complete
> Refresh numbers from earlier survey
> Bring up a few new issues
> Identify potential candidates for
> Phase II phone survey
> Phase I results presented at VIUF and HDLcon
> Draft Phase II survey ready
> Get more detailed inputs on directions
> Get specific suggestions for changes
> Look for potential volunteers to help in VHDL
> standardization process
> Bob handed out a DRAFT copy of the questionaire
> Questions can be viewed online at:
>
> http://saturn.vcu.edu/~rhklenke/vhdl200x/survey_phaseII.html
> We will take comments or suggestions on the survey
> until 19 June
> After this date, they survey process will begin
> They are looking for suggestions of users to interview
> Volunteers:
> Jim Aylor, Patrick Bryant, Bob Klenke,
> Paul Menchini,
> Alex Zamfirescu, Jean Mermet, Steve
> Bailey, Peter Ashenden,
> Wolfgang Ecker, Satoshi Kojima, Ron Waxman
> Interview process to be completed this summer
> Results to be presented at VIUF workshop and HDLCon 2001
> Survey and workshop results will also be summarized
> in a final
> report and given to VASG
> Future- how do we translate survey results into
> initial requirements
>
> Proposed Language Enhancements for VHDL 200x
> This presentation is a collation of the
> contributions returned
> in response to the Chair's call for Brainstorming
> It also contains the chair's collection of suggested
> enchancements that he has encountered over the years
> No claim is maede to the completeness of this collation
> Further recommendations are welcome
>
> Standardize synthesis on/off pragmas in the languages
> J Bhasker
> A standard processor (such as CPP). Even with the wealth of
> language features available, a text-replacement preprocessor
> provides additional value
> E. Lavelle
> Read references to signals across scope/visbility boundaries
> (Verilog $monitor) J Bhasker
> Write access in addition to Bhasker's read access and
> including variables
> L. Thompson
> Applicability of VHPI to meet this need?
> L Thompson
> Or a VHDL standard package interface to VHPI
> S Bailey
> Eliminate restriction that processes in an entity be passive.
> This eliminates the need for a separate architecture, but
> permits the continued use of architectures by those who want
> them
> Clive Charlwood
> Short-hand for including all signals read in a
> process sensitivity
> list-- inference made by synthesis tools for
> combinatorial processes.
> Example:
> p1: process (all)
> L. Thompson
> Verilog 2000: @(*)
>
> Globally static expressions in sensitivity list:
> process(rst, clk'event and clk = '1')
> S Bailey
> Allow separation of the specifications of
> "exceptional" from "normal"
> process execution Example:
> process (clk)
> begin
> if clk'event and clk = '1' then
> end if;
> except (rst = '0')
> end process
> S. Bailey
> Comment: NEED SEMANTICS
> If the top design unit has generics, there is no
> mechanism in the
> language to associate values to them. Example (Ada
> generic packages)
> entity foo_bound is new work.foo generic map (g1
> => 1, g2 => "i1");
> or
> configuration foo_bound of foo is generic map (g1 => 1,
> g2 => "i1");
> L. Thompson, W. Ecker
> A way to make types more lie subtypes.
> Specifically a way for std_ulogic_vector to be used
> interchangably
> with std_logic_vector as std_ulogic and std_logic
> can be. (Chair's
> note: Issue appears to be how resolution is
> specified in for related
> vector/composite types.)
> L. Thompson
> Comment: Probably infeasible as proposed, need underlying
> requirement
> Add 64-bit integer type and/or 128-bit type (ammendment)
> W. Ecker
> Add unlimited range integers (constrained by subtype
specification)
> S. Bailey
> Define 2's complement representation of integers and little/big
> endian for bit-level manipulation of integer values
> W Ecker and S. Bailey
> ISAC has the action item to automate bug tracking
> Add fixed point types & related operations for DSP
> applications
> S. Bailey
> Add generic types (ala Ada)
> W. Ecker
> Standard way to specify representation of
> enuemrated literals for
> bit-level manipulations
> S. Bailey
> Require a minimum 64-bit range for type time (friendly comment,
> should be extended to all physical types).
> W. Ecker
> Should the number of delta cycles be characterized?
> J Willis
> Permit unconstrained elements in composite types
> (also driven by
> the issue of related, but resolved composite subtypes).
Suggestion
> was that OO could handle this.
> S. Bailey
> What can be doen to accelerate RTL sign-off (Evan
> Lavelle posited
> by Chair)
> What do people still need to do gate-level simulation.
> Un-attributed
> Unary reduction operators on vectors
> (AND, OR, NAND, NOR, XOR, XNOR)
> W. Ecker and Lance Thompson
> Need bit-wise operators on objects of integer and enumerated
types
> E. Lavelle, W. Ecker, M. Ronan (and S. Bailey as related
> to type catagory)
> Need increment and decrement operators for integer
> (E. Lavelle)
> Define a case-equality operator which is used to
> evaluate case
> alternative matching (Like Verilog == versus ===). This will
> allow use of '-' (don't care) in case statements have an
> appropriate meaning without requiring 1164 to be
> pulled directly
> into the language.
> S Bailey
> May require full-case and exclusive-case variants
> of case statement
> An operator to get the address of an object for
> futher use as an
> object for further use as an access type object. John Willis
> commented that this would potentially cut heavily
> into performance.
> E. Lavelle
> Tertiary operator like C's ?: operator. Selected
> signal assignments
> are approximations of this, but are a specific form
> of signal assignment
> when a general expression form is required.
> S. Bailey
> With 2's complement representation of integers and
> enumerated types of
> assignment between integer/enumerated types objects
> and bit vector
> (bit_vector, std_logic_vector, etc) can be defined.
> S Bailey (logical extension of previous requests)
> No overflow/underflow detection with arithmetic
> operations to match
> hardware behavior and improve performance. (Or
> have some standard
> way to disable the overflow/underflow detection).
> W. Ecker
> Allow an expression of a one-dimensional array type
> in a multi-
> dimensional array aggregate where the language
> currently permits
> a string or bit string literal as a sub-aggregate.
> S. Bailey (at least one sim vendor allows this
> now but it is currently
> illegal in the LRM).
> Permit a simple object reference where a boolean
> expression is required
> when that object is of a bit type (signal A:
> std_logic; if A then...)
> From VI survey
> Generic packages (parameterizability on type,
> subprogram, use of other
> packages)
> W. Ecker & M. Ronan
> Better capabilities for abstract data types including
> information hiding,
> instantiability of objects, variant records and etc)
> M. Ronan
> Enhancements to support reconfigruable hardware
> W. Ecker
> Other enhancements for FPGA design (no other
> specifics provided).
> W. Ecker
> Relax semantics to allow hex string literals that are assigned
to
> objects with fewer or more than 4n bits. Define
> how the hex string
> is truncated or padded out.
> E. Lavelle
> Add optional elsif or else branch to if generates.
> Helps ensure
> mutually exclusive genrate conditions and reduces
> typing burden.
> E. Lavelle
> Generalize port map aspect to allows association of
> a non-static
> expression with an actual of mode IN (Eliminates
> need to explicitly
> declare combinatorial signals to do this).
> E. Lavelle
> Conditional ports for use with things such as
> pre-inserted scan ports
> that aren't always simulated or synthesized.
> M Ronan
> Ability to use a generic within a generic clause
> immediately after its
> declaration (aS default value or constraint of
> subsequent generics).
> W. Ecker
> Ability to bundle ports (regardless of modes)
> D. Soderberg
> Textio is inadequate. Insufficient set of I/O functionality.
> (for example no standard I/O for std_logic_1164).
> Every new type
> needs to have its own write functionality implemented, etc.
> Look at the capabilities for C and C++ for I/O.
> E Lavelle, S Bailey
> Need a file flush operation.
> W. Ecker
> Overload write procedures as functions that return
> their string values
> S. Bailey
> Eliminate the need to type qualify certain operands
> to write procedures
> S. Bailey
> Allow variable length parameter lists with
> subprograms as with C>
> (Necessary for adopting C-like I/O capabilities).
> Useful in other
> contexts as well. Default values for input
> parameters only partially
> meet the needs here.
> E. Lavelle
> Subprogram call overhead in VHDL is tremendous. We
> need to find ways
> to reduce the overhead.
> S. Bailey
> For same performance reason, we should allow
> subprogrqams to be
> identified as macros by the user for inlining.
> S. Bailey
> Find a way to eliminate compilaiton dependencies or automate the
> recompilation of dependent units.
> E. Lavelle
> Find a way to eliminate the need to always type
> library IEEE; use IEEE.std_logic_1164.all;
> with practically every design unit.
> S Bailey
> Generalized declarative regions within sequential
> code. Allows
> explicit indication of lifetime of objects. Eases
> modification of
> existing processs code.
> S. Bailey
> Modify 'value so it does not abort simulation when
> provided an
> incorrect value.
> W. Ecker
> Permit user-defined overloading of predefined attributes
> W. Ecker
> 'image need definition for composite types
> W. Ecker
> Type conversion functions in port maps need the flexibility of
> additional paramters to specify sizing or other attributes or
> control characteristics (sounds like globally
> static values are
> acceptable).
> W. Ecker
> Better time abstraction capabilities (Specification of time
> ranges).
> S. Bailey
> Global set/reset capabilities similiar to Verilog "disable
> named processes" capability.
> M Ronan
> Ability to specify a condition under which a process
> re-initializes
> J. Vellenga
> Portable way to filter by severity assertions in standard
> packages. Suggestion was to forward to the TCL team.
> S. Bailey
> Ability to model jumpers and straps
> S. Bailey
> User-defined events (data-less signals)
> S. Bailey
> Quicker, easier clock specifications
> (CLOCK: clk: std_logic := '0', 10 NS);
> S. Bailey
> More efficient FSM specification
> S. Bailey
> Standard memory modeling support package (higher
> level than the
> VITAL 2000 memory modeling specification).
> Especially for large
> and/or sparse memorues and including loading and
> dumping operations.
> Would not require signal resolution for multi-port RAMS.
> S. Bailey
>
> What Else is needed for VHDL 200x?
> Should we look at incorporating verification language (Vera,
> e) capabilities.
> Higher abstraction level capabilities?
> SID-like, OO-like (continue deference to other WGs)
> Anything contrinbuting to re-usability
> Need volunteers to lead analysis and investigation
> Who has the interest to push an area of interest
> forward (working with data WG collects).
>
> Next meeting
> FDL, Tubingen, Germany (4-8 September)
> Fall VIUF?
> W/T/F October, Orlando, Florida
> ASP-DAC 2001?
> HDLCon 2001
>
>
>
>
>
>
>
>
>
>
> John Hillawi DA Solutions
> hillawi@eda.org
> Noelle Humenick IEEE Standards
> n.humenick@ieee.org
> Peter Ashenden University of Adelaide
> petera@cs.adelaide.edu.au
> Jim Heaton JNA Limited
> jim_heaton@ieee.org
> Greg Peterson FTL Systems
> gdp@ieee.org
> Masamichi Kawarabayashi NEC
> kaba@el.nec.com
> Bob Klenke VCU
> rhklenke@vcu.edu
> John Willis FTL Systems
> jwillis@ftlsys.com
> Paul Menchini
> mench@mench.com
> Dennis Brophy Model Technology
> dennisb@model.com
> Gabe Moretti ISD Magazine
> gabe@dimensional.com
> David Barton Averstar
> dlb@wash.averstar.com
> Steve Schultz Texas Instruments
> ses@ti.com
>
>
>
>
>
>
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