Subject: Re: Some suggestions
From: Stephen Bailey (sbailey@synopsys.com)
Date: Thu Apr 27 2000 - 08:25:22 PDT
Evan, a couple of responses to your suggestions. (BTW, thanks for providing
the suggestions.)
-Steve Bailey
Chair, VASG
----- Original Message -----
From: Evan Lavelle <eml@riverside-machines.com>
To: stds-vasg <stds-vasg@ieee.org>
Sent: Thursday, April 27, 2000 4:23 AM
Subject: Some suggestions
> 3) Buffer mode ports need fixing.
VHDL 2000 has changes related to BUFFER mode ports. Whether they "fix"
them, I'll let you decide. If the changes don't "fix" BUFFER ports, please
let us know what else you'd like.
VHDL 2000 eliminates the restriction on a single source for BUFFER mode
ports or any actual associated with a BUFFER port. VHDL 2000 will allow OUT
and INOUT mode ports to be associated with BUFFER mode ports. There is no
change to the effective value of a BUFFER mode port (when read inside the
architecture, it returns the driving/sourcing value of the BUFFER port).
> 4) A significant amount of my code involves creating temporary
> signals, doing some simple combinatorial assignment to them, and
> then using them as actuals in a port map. The problem here is that
> although you can use an expression as an actual for a formal
> signal, the expression has to be globally static, and so you can't
> do something simple like:
>
> U1 : COMP port map (
> A => SIGA and SIGB, -- illegal
> B => "00" & SIGC); -- illegal
>
> Why does the expression have to be static? Removing this
> restriction would make it more difficult to identify drivers, but
> surely there's very little extra complexity here.
VHDL '93 permitted the association of expressions as actuals to IN mode
ports. The purpose is to allow the specification of the default value of
the port when it is not connected to another signal (such as tied high or
tied low). For this purpose, a globally static expression is all that is
required. Your suggestion generalizes this capability in a way that was not
intended in VHDL '93. (Please note, this is only historical information on
the existing capability and not a judgment on your suggestion. Your
suggestion will be considered.)
> 5) Anonymous arrays. For example, this declaration is illegal:
>
> signal SIG: array (7 downto 0) of X;
>
> Why? This is apparently legal in Ada.
Anonymous array subtypes are legal in VHDL. Unfortunately, I'm travelling
at the moment and cannot quickly review the correctness of your sample
declaration. Please re-check your code and your implementation.
> 11) A standard PLI - how is this getting on?
The VHPI committee work continues. Unfortunately, this work always takes
longer than anyone expects or would like to see. The committee is
progressing. I personally know of at least two simulation vendors who are
actively working on implementing and supporting the VHPI (Cadence and
Synopsys). Other vendors may also be actively working on this. (Any
vendors on this list who wish to identify their pro positions on VHPI,
please do so. The intent is to promote the VHPI and not specific vendors to
the exclusion of others.) You should question and pressure your vendor(s)
to support it as well.
Hopefully, the committee will be able to get to balloting this year.
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