Subject: questions std 1164
From: Ammar.Aljer (aljer@lifl.fr)
Date: Mon Apr 24 2000 - 01:41:50 PDT
Goodmorning,
I am preparing for the phd in informatic in LIFL of france .a part of my
work is to translate the VHDL_STAND_1164 .
may i ssk you to help me to answer at these questions :
what are the benifices of:
1-is the BIT a type of VHDL how has the value 0 or 1
2-i undrestood that we need a vector to solve the probleme of the
singal of many sources . so what is the importance of the operations
between 2 vectors ?
3-what are the benifices of the attributes :
attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";
attribute REFLEXIVE of resolved: function is TRUE;
attribute RESULT_INITIAL_VALUE of resolved: function is
std_ulogic'POS('Z');
thank you
senceerly
aljera mmar
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