Subject: Re: AW: Brainstorming VHDL 200x
From: lancet@us.ibm.com
Date: Wed Apr 19 2000 - 13:10:56 PDT
The object oriented technique you show would work just fine. My original
line of thought was to use an extension of configuration declaration.
Something like:
configuration c of e
generic map( g1 => a1 )
end configuration c;
c would be the thing that gets synthesized and instantiated, documenting
and maintaining the fact that generic g1 has the value a1.
Wolfgang.Ecker@infineon.com on 04/19/2000 01:08:43 PM
Please respond to stds-vasg@ieee.org
To: stds-vasg@ieee.org
cc:
Subject: AW: Brainstorming VHDL 200x
Might it be that you look for something as available in ADA
for generic packages? Something like
entity Entity4x4y2z is new
Entity_x_y_z generic map ( x => 4, y=> 4, z=> 2);
From my perspective, I would also like to have generic
packages, with a similar specialization mechanism. They would
e.g. useful to provide a package with an integer type, which
has a configurable
3. No, I don't mean entity instantiation. This request has to do with
synthesis and managing design information more than anything else. If I
have a reusable design, it will typically have generics. If that design is
large enough, I might want to synthesize it on its own. Synthesis tools
allow a method of passing generics through a command interface. The
question is, how are those generics documented as part of the design.
True, in the instantiation of this design, I'll have to associate the
generics, but what assures that the generics I associate in the
instantiation match the generics I pass by command? Now, I can do this
today by adding a "wrapper" layer but that is more work than a
configuration that sets the generics...
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