Subject: Re: Brainstorming VHDL 200x
From: Stephen Bailey (sbailey@synopsys.com)
Date: Wed Apr 19 2000 - 05:46:36 PDT
Evan,
> > 2. A short-hand notation to denote a process sensitivity list that
> > contains all the names read in that process. Process( all ) comes to my
> > mind. This would ensure that simulation and synthesis results "match"
in
> > level sensitive storage element inference.
>
> Good idea. I suppose the only downside is that simulation of clocked
> processes will be slower if this is used indiscriminately. I suspect
> that there will also be combinatorial cases in which pre- and post-synth
> sims will differ (can't think of one right now) but this will be a case
> of buyer bewares.
You are missing the point. What Lance has proposed here is for
*combinatorial* processes and not *sequential* processes (in usage).
Synthesis style guidelines would still apply. Therefore synthesis tools
would expect to only see the "clk" and "asynchronous control" (if any)
signals in the sensitivity list for a sequential process. Synthesis
guidelines expect all signals read in a combinatorial process to be in the
static sensitivity list. If the sensitivity list is incomplete, synthesis
completes it. This can result in differences between simulation behavior
and synthesis results. Lance's short-hand for this is a concise and
accurate way to capture design intent (all signals read are to be in the
static sensitivity list).
(BTW, Verilog 2000 has added this type of feature.)
-Steve Bailey
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