Subject: Re: Brainstorming VHDL 200x
From: Evan Lavelle (eml@riverside-machines.com)
Date: Wed Apr 19 2000 - 02:19:53 PDT
Stephen Bailey wrote:
> 1. As stated in the context setting message. Gate level verification
> remains an "achilles heel" of VHDL. (Don't take that quite literally as in
> we fail unless we fix it. Just take it as a major competitive disadvantage.
> One that results in the competitor (Verilog) getting into our installed
> base.) I think we need to explore ways to neutralize this disadvantage and
> eliminate it from the competitive evaluation process. If we do not, it has
> been and will likely remain a deciding factor in many language evaluations.
This may be heresy, but I don't think that this issue is quite this
important. Why?
1) The industry seems to be moving towards RTL sign-off, possibly with
equivalency checking.
2) How many people actually do significant gate-level sims? I suspect
that a lot of people just do very limited testing, to confirm that the
device exits from reset, that the modules are still connected together
properly, that some simple regression tests pass, and that no timing
violations are reported in the process. In any event, there are always
going to be a lot more people in any organisation doing RTL coding than
gate-level signoff.
> 2. Neutralizing our current competitive disadvantage with Verilog in
> designer productivity at the RT/synthesizable level of design is closely
> related to the 3rd category. However, I think it is worthwhile and
> justified to separate it out. The primary reason is that this is the level
> that 90% or more of HDL users are working at today. Most likely greater
> than 50% of HDL users will remain at this level for the next 5-10 years. We
> need to reward our current users and entice a broader user base.
>
> 3. I believe that designer productivity is the only factor of importance.
> Designer productivity has many perspectives (tool performance, number of
> keystrokes and correct-by-construction are 3 major ones).
This may again be heresy, but I don't think that raw designer
productivity is an issue. It looks bad when a competition demonstrates
that designer X can code up a module in Verilog faster than designer Y
can do it in VHDL, but it wouldn't surprise me if someone also ran these
contests with Basic and C 20 years ago - with the unsurprising answer
that you can code up something simple in Basic faster than you can do it
in C.
Second: just how much of the design process is taken up with RTL coding
anyway? In my case, less than 10%. The rest of the process is far more
time-consuming: defining specifications and architectures, correcting
and iterating them, making sure procedures are adhered to, going to
numerous meetings, developing an abstract version of the design, doing
the back-end work, and so on. At the end of the day, it simply doesn't
matter that it may take me an extra week to code up my RTL bits in VHDL
compared to Verilog. I could even do it in schematics, and it's unlikely
that anyone would notice the effect on the timescales.
I've got a pie chart in front of me, originally published in Electronic
Systems, Jan. '99, breaking down the 'Typical ASIC design process'. The
figures given are, highest first:
Authoring 20%
P&R 17%
Synthesis 16%
Simulation 14%
Gate Simulation 7%
The rest is back-end grunt work. However, this pie chart appears to
assume that the process started with a correct specification. In any
real-world design, the above figures are going to be shrunk
correspondingly.
The reason I use VHDL isn't related to productivity. It's because I can
write at a higher level (*not* a more abstract level), because it's
easier to parameterise and re-use, it's hopefully easier for other
designers to take over my code, my testbenches almost look like real
programs, and so on. My opinion is that the way forward for VHDL has to
be to capitalise on, and extend, these high-level features, rather than
addressing perceived disadvantages against Verilog. Where Verilog has
market share over VHDL, it's for very simple historical reasons. Gateway
talked to ASIC vendors early on, and they got Synopsys on board. Period.
This didn't happen for VHDL because no-one was paid to go out and sell
it. It's got nothing to do with technical reasons.
Evan
This archive was generated by hypermail 2b28 : Wed Apr 19 2000 - 02:34:29 PDT