Here are some observations from clause 1.
p. 6 - entity AndGate is - the port list has the syntax run together (
Inputs:inBit_Vector )
p. 8 - should the paragraph on page 11 that starts "The various kinds of
declarations..." also appear after the syntax in 1.1.2 Entity declarative
part?
p. 9 - might want to align the port names in entity ROM.
p. 10 - an extra '(' in (see (10.2 and 10.3).
p. 12 - component name runs into port map. UUT:Full_Adderport map
(A,B,C,D,E);
Cheers,
Lance