At the last VASG I got an action to
provide a plan for the review of the
new VHDL draft. The deadline was
Nov 15.
Here is what I propose
- A one day VASG meeting on December 8 1999 at
Mentor Graphics in San Jose CA with interested
people for general review (room arrangement
in principle agreed)
- A follow-up ISAC meeting next day (half day) to nail
down hard cases.
Please send your availability
to me at mno1@ricochet.net
and cc sbailey@synopsys.com.
Please avoid as much as possible
to reply to the whole reflectors.
Due to the overlapping of the lists
you might have recieved
more than one message.
Please forgive that.
A second condition is to be able
to look at "something" concrete
at least one week before December 8.
Is that possible?
PAUL and STEVE, if the answer
is yes I plan to get the input from
the IEC WG2 people who might not
be able to attend directly, but have
a great interest in the success of
the new draft.
A third ingredient, is discipline
in order to be able to optimize
our time at te meeting. I am sure
that we will find the best way to
interact.
Please,
1. SEND MR. BAILEY and ME AN ANSWER ABOUT
YOUR ATTENDING THE REVIEW MEETING ON DECEMBER
8 1999 IN SAN JOSE CA. SEND YOUR ANSWER ASAP (BY THE
END OF THIS WEEK) TO MAKE SURE WE CAN CONFIRM THE
MEETING 14 DAYS IN ADVANCE
2. IF YOU ARE AN ISAC MEMBER PLEASE CONFIRM
YOUR AVAILABILITY ON DEC 9 TH (HALF DAY).
3. STEVE AND PAUL PLEASE CONFIRM FEASIBILITY OF THIS
PLAN
If you have any comments relevant to all
please reply to this message.
If this review is not your concern please
accept my appologise.
Best regards,
Alex Zamfirescu