Re: VHDL '98 ('99) LCS Review and Approval

Yosi Veller (veller@sd.co.il)
Thu, 14 Jan 1999 11:41:09 +0200

LCS Approve Disapprove Comment
-----------------------------------------------
1 Approve
2 Approve
3 Disapprove see below
4 Approve
5 Disapprove see below
6 Approve
7 Approve
8 Approve
9 Approve
10 -
11 Approve However the LRM can allow unconstrained result
conversion functions for constrained formals
12 Approve
13 Approve
14 Approve
15 Approve
16 Approve
17 -
18 -
19 Approve
20 Disapprove I concur Peter Ashenden
21 Disapprove I concur Peter Ashenden
22 Disapprove I concur Peter Ashenden
23 Disapprove I concur Peter Ashenden
24 Approve See below
25 Approve
26 Approve

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LCS 3

I agree that the LRM should add a declarative region that encompasses
BOTH the entity and the architecture. In order to allow then an
architecture with the same name as the entity the LRM should make them
non-homographs.

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LCS 5

In the current state of affairs, the analyzer may check at compile
time the compatibility between a componnet declaration and the
associated entity, issue errors about type and width mismatch at the
earliest possible stage. Moreover the analyzer can then generate code
that saves a lot of work and information reading during elaboration.

Secondly I don't agree with the wording:

"Secondly, requiring the entity to be directly visible at analysis
implies that the entity interface must exist during the analysis of
the component instantiation statement that will eventually be bound to
the entity interface. This requirement has the effect of precluding
top-down design, where the entity interface need not exist when its
corresponding component is instantiated."

The interface has to exist in the component declaration, and even if
the entity does not exist one can still compile the instantiating unit
and even simulate it. The only overhead is that instantiating unit has
to be compiled after the entity is compiled.

It does not seem consistant to allow in some cases compile time
checking of the instantiation and in other cases only elaboration.

My proposal for the solution is to specify that the entity with the
component declaration's name within the component declaration's
library is made visible for the binding indication. In my opinion this
can be achieved by adding another visibilty rule (c) to the rules in
5.2.2.

----------------

LCS 24

VHDL users are using buffer ports as a mean to get compilation errors
for multiple drivers even for resolved signals. Hence the restriction
of a single driver to a buffer port should not be relaxed.