Re: VHDL '98 ('99) LCS Review and Approval
lancet@us.ibm.com
Mon, 11 Jan 1999 09:47:05 -0600
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| LCS |Approve |Disappro|Comment |
| | | ve | |
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| 1| X | | |
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| 2| X | | |
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| 10| X | |Part of LCS 3 |
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| 11| X | |I'd like to revisit this in 200x. The goal |
| | | |being to make std_logic_vector a subtype of |
| | | |std_ulogic_vector. The fact that std_logic is a|
| | | |subtype of std_ulogic but std_logic_vector and |
| | | |std_ulogic_vector are distinct types is |
| | | |troublesome to most users. |
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| 12| X | |First, let us correct an apparent typographical |
| | | |error and consider the relational expression |
| | | |1.001 ps = 1001 fs. |
| | | | |
| | | |This expression is always true in the absence of|
| | | |3.1.3.1, page 39, line 231 which describes |
| | | |modifying the execution time resolution limit of|
| | | |type time. It is always true (and thus exact) |
| | | |because a physical type is constructed of an |
| | | |integer range constraint, and integral multiples|
| | | |of the primary and secondary unit declarations. |
| | | |Therefore, while writing a "time literal with a |
| | | |real part," one is expressing an integer time. |
| | | |Furthermore, 3.1.3.1 states that it is an error |
| | | |if a unit is used in the model that is smaller |
| | | |than the resolution limit requested. So, if we |
| | | |selected ps as our resolution limit, our |
| | | |expression would cause an error. |
| | | | |
| | | |With that said, if VHDL-AMS has a different |
| | | |concept of time, this issue should be forwarded |
| | | |to VHDL-AMS. |
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| 26| | |Abstain |
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"Bailey, Stephen A (Steve)" <sbailey@veribest.com> on 12/22/98 03:07:57 PM
Please respond to stds-vasg@majordomo.ieee.org
To: stds-vasg@ieee.org
cc: (bcc: Lance Thompson/Rochester/IBM)
Subject: VHDL '98 ('99) LCS Review and Approval
NOTE: Suspense date: 15 January 99.
Finally, what everyone has been waiting for: The VHDL '98 ('99) LCSs.
Unfortunately, I cannot email the LCS file as the IEEE majordomo server
rejects it because it is too large. I have put it on
http://www.vhdl.org/pub/vasg under the Archives link. However due to
vhdl.org/eda.org policy, you need a password to access it. Therefore, I've
had it placed on the VeriBest website for easy access
(http://www.veribest.com/vhdl98revd.pdf). I'll continue to look into
making
it more accessible via vhdl.org/eda.org. Until then, please get it from
the
VeriBest website.
Please review the LCSs and either approve or disapprove each individually.
(Disapprovals require justification.) Because each LCS essentially maps
into an ISAC IR and an IR may be resolved by recommending no language
change, some LCSs, in fact, result in no language changes.
Enjoy the holiday season!
The following matrix is provided to facilitate the review process.
LCS Approve Disapprove Comment
-----------------------------------------------
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Steve Bailey
HDL & Simulation Product Manager
Free Evaluation of VB VHDL: http://www.veribest.com/vhdl.html
VeriBest Inc.
The EDA Systems Company
6101 Lookout Rd.
Boulder, CO 80301
303-581-2467 (voice) 303-581-9143 (fax)
303-588-2001 (mobile)
mailto:sbailey@veribest.com http://www.veribest.com