Next VASG Meetings:
EDA Techno-Fair: There are no DASC meetings scheduled for Japan this
year. However, it is likely that I will be in Tokyo for the EDA
Techno-Fair. EIAJ representatives should contact me if they would like to
schedule a meeting.
DATE: Munich, Germany, week of 8 March 1998. I believe DASC meetings
are planned in conjunction with DATE. I am also planning a VASG meeting at
this time. Specific time and place are TBA.
International HDL Conference, Santa Clara, CA, week of 5 April 1998.
Planning on DASC and VASG meetings. Specific time and place are TBA.
PLI Status:
* New member (Rob Newshutz, FTL Systems)
* Progress isince DAC, approved definitions:
* VHPI Foreign models and applications
* Simulation callbacks registration and execution
* Information model
* Subprogram call data access
* Property access functions definition
* Error checking
Issues postponed to later version of VHPI
* VHPI support of multi-threaded applications
* J. Willis expressed concern about the deferral
* G. Moretti: don't delay VHPI further on this issue
* F. Martinolle: Only a few areas of PLI identified as impacted by
issue, but no band-width available to ensure PLI is multi-thread safe.
* Standard set of error codes
* Special access to VITAL data (most likely)
Current working item:
* Connectivity access (sources, drives, loads)
Pending reviews:
* Printing of VHDL strings
* Runtime scheduling of transactions (when Vish returns from India)
* Access to VHDL object values
Remaining tasks
* Specifications needed for:
* Interface file delivery
* Utilities such as file I/O
* Prototyping and validation
* Good if a test suite could be developed
Forecast
* On schedule (based on August re-schedule)
* 1st complete draft at end of March
* Technical editing of the standard itself (Paul Menchini doing the
tech editing)
* Targeting June for VASG review and approval
There was a discussion of how to create more interest in VASG's efforts.
Consensus was that the related standards are where the excitement is not the
VASG. The best thing we can do is get VHDL '98 behind us and start working
on future enhancements that might interest newcomers.
Wolfgang Ecker offered to head up a group to extend 1164 and look at
integration issues.
Gabe asked that a group be formed to examine the interaction and synergy
between related standards (such as 1164 and VITAL).
Agreement was made on changes to the ballot response for 1076a. Means were
not found to maintain backward compatibility without substantive changes to
1076a. The 1076a ballot response is in final review (to ensure consistency
with the draft LRM changes). The ballot response will be circulated
shortly, but there will be no substantive changes and, therefore, no
re-circulation will be required.
Each LCS for VHDL '98 was reviewed and several were discussed in detail. A
new proposal for the LCS covering default bindings was made. Also, a
proposal for "fixing" buffer ports (allowing OUT mode ports to be associated
with a buffer mode port) was offered. The LCSs are in the process of being
updated and will be distributed for VASG review and approval shortly.
Steve Bailey
HDL & Simulation Product Marketing Manager
Free Evaluation of VB VHDL: http://www.veribest.com/vhdl.html
VeriBest Inc.
The EDA Systems Company
6101 Lookout Rd.
Boulder, CO 80301
303-581-2467 (voice) 303-581-9143 (fax)
303-588-2001 (mobile)
mailto:sbailey@veribest.com http://www.veribest.com