VASG Meeting 18 Jun 1998
Attendees:
Steve Bailey, VASG chair
Greg Peterson - gdp@vhdl.org
John Willis, ISAC chair - jwillis@ftlsys.com
John Hillawi - hillawi@dasl.compulink.co.uk
Victor Berman - berman@vhdl.org
Rob Newshutz - newshutz@ftlsys.com
Dennis Brophy - dennis_brophy@mentorg.com
Francoise Martinelle - fm@cadence.com
Dave Barton - dlb@wash.inmet.com
Jim Heaton - jheaton@wg.icl.co.uk
Kamal Hashmi - kamal@computer.org
Ron Waxman - r.waxman@computer.org
Paul Grojean - pmg@sr.hp.com
Henry Lin - hylin@veribest.com
D Townsend - townsend@synopsys.com
Murray Pearson - mpearson@cs.waikato.ac.nz
Agenda approved:
Review/Approve Agenda
PLI Status
SVWG Ballot summary
VHDL '98
IEEE Awards nominations
Next meeting
Discussion of getting funding from VI for projects - Victor is POC as VI
Technical Activities Chair
DASC membership - need to get folks to sign up
VHPI (VHDL PLI) Status Update (Francoise Martinelle)
Paul Menchini will be technical editor
New members
5 companies will implement - Cadence, Ikos, Synopsys, Veribest, FTL
Time frame (should be in the next year or so, not like VHDL
'93,
the development is based on VHDL '93 and should move to '98
without
much difficulty)
Since IVC, interface handle allocation management and naming
conventions approved
Issues resolution - working on information model for VHPI
Pending reviews:
Runtime scheduling of transactions
Connectivity traversal
Information model details
Specifications of iterations and access
Specs needed for
Error handling
Call back creation
Value access
IP delivery
Behind schedule ~5 weeks, but trying to catch up
Hope to have a draft for review by November
VASG meeting suspended for VHDL+/System & Interface Level Modeling meeting
(Jim Heaton)
Formed as study group fall 1997 VIUF
Met at ASP-DAC '98
Overview of VHDL+ (Kamal Hashmi)
Raison d'etre:
Unambiguous protocol specifications
Mix models from different levels
Higher level functional capture & simulation
Aims:
Timing, data abstraction & dynamic resources
Interfaces
Specify protocols (& design)
Multiple levels of protocols
Mapping between levels
Declarative semantics
Entity /Architectures
More general process - callable "activity"
Mixed parallel and serial hierarchy
Flexible interprocess communication
Version 4.0 released 12 June 1998
LRM available on web page soon & documents
www.icl.com/da
eda.org/sid
email on reflector
added protocol construct
multiple direction messages
full nesting of statements, serial & parallel blocks
signal mapping - packet level
"action" statement - non-deterministic selection
choice/choose - weights on branches
questions - this seems like a nice
representation for a specification, where one then proves the implementation
meets the spec. there is some work occurring in this area
consider the equivalent structure within VHDL for
these constructs
A roadmap will be developed by July (Jim Heaton)
Plan to move to working group/PAR
need to have a vote over the reflector for the PAR
discussion of the relationship to the OO-VHDL group - still
needs to be done
Will discuss these things more with OO-VHDL and then meet at FDL
with steering committee
Next meetings at Fall VIUF and FDL
And back to the VASG meeting...
Discussion of the complexity of the language and what needs to be done to
handle it
Pedagogical issues vs. language maintenance issues
Suggestion to have groups collect lists of language needs to
synchronize across groups or have a language coordination meeting to discuss
it
SVWG ballot summary
Ballot passed
34 affirmative
3 negative
7 abstention
44/55 ballots (80%)
15% abstention
91% affirmative
10 ballots/coordinations with comments
producer category had highest number of abstentions or
non-response
Lessons learned:
Form the ballot constituency as late as possible!
Get as many types of contact as possible - especially email!
Discussion of balloting requirements for standards and people
Comments of note
Not backward compatible with VHDL '93 shared variables (3)
Extra complexity is not warranted
Remove shared variables
Mode of SV parameters too limited (INOUT only)
Allow constraints in protected (sub)types
Allow initial values
Allow overloading of equality and inequality (2)
Various suggestions for clarifying & rewording text
Possibility for having a university create tool for
translating old models to new version of shared variables
Get copy of comments to Paul Menchini
Send email to Victor, Paul, John, Greg, Steve for date for response
to comments
IEEE Awards Nominations
Richard E. Merwin Award
Outstanding Service to the profession at large
Computer Society
Predecessor organization
Bronze medal
$2000 honorarium
Nominations due 18 Sep 98
Any VASG or DASC participants that we want to nominate?
Ideas for nominations?
Will discuss at steering committee meeting.
Break for lunch
Back to the salt mines...
VHDL '98 status
LCS's should be approved within ISAC in the next couple weeks
About 16 language change proposals
No deletions
No major additions
Attempted to keep language stable
Had quick overview of issues not yet resolved
Jeff Carter will put each LCS on the vhdl.org machine
ISAC voting closed out by end of June
VASG approval should only need 2 weeks for review
VASG reflector at stds-vasg@ieee.org
Paul will need 6-8 weeks for LRM writing
Will need time to review
Probably will not ballot until September
Discussion of the need to reconstitute VASG balloting constituency
Action item to set some rules and let folks know what they
are - want to avoid controversy about their participation.
Need to give the EIAJ some notice about the meeting.
Need to talk to Paul to see about the dates for
balloting/editing
Next meetings
FDL - 11-12 Sept 1998; Lausanne Switzerland
Fall VIUF - 29-30 Oct 1998; Orlando FL
Steve Bailey
HDL & Simulation Product Marketing Manager
VeriBest Inc.
6101 Lookout Rd.
Boulder, CO 80301
303-581-2467 (voice) 303-581-9143 (fax)
mailto:sbailey@veribest.com http://www.veribest.com