> The next VASG meeting will be held on Thursday,
> June 18th. The location is Mentor Graphics in
> San Jose (http://192.94.39.7/cet/CTR_SJC.html).
> We have the meeting room from 9-5 but will try to
> finish as soon as possible to allow people to join
> the VHDL+ or PLI meetings. Here's the agenda for
> the meeting:
>
> 1. SVWG Ballot Summary S. Bailey 30 mins.
> 2. VHDL '98 J. Willis, S. Bailey
> Details of proposed changes 1+ hour
> Balloting process, timing, etc. 30 mins.
> 3. VHDL PLI status
>
> NOTE: I do not plan on discussing any VHDL 200x
> issues at this meeting. We need to get '98 done and
> I have been deferring VHDL 200x work for the past few
> months and will continue to do so for at least a couple
> more to ensure it doesn't interfere with '98.
>
> If there is anything that should be added to the agenda,
> please let me know.
>
> Steve Bailey
> HDL & Simulation Product Marketing Manager
> VeriBest Inc. http://www.veribest.com
> 6101 Lookout Rd.
> Boulder, CO 80301
> sbailey@veribest.com
> 303-581-2467 (voice) 303-581-9173 (fax)
Dear Steve,
thank you for the information. I am sorry, but I can not come
to the meeting. See you in Lausanne and/or Florida,
Wolfgnag