Conference: In conjunction with ASP-DAC
Location: Pacific Convention Center (Pacifico),
Yokohama, Japan
Date: 10 Feb 98
Time: 9am to 5pm
Agenda:
Welcome &
General Status: S. Bailey (15 mins)
EIAJ Activities: Kaba/EIAJ Representative (30 mins)
VHDL '98: John Willis (30 mins)
VHDL PLI: S. Bailey for Francoise Martinolle (15 mins)
Break
VHDL Standard Output Format: Paul Menchini or S. Bailey (15 mins)
VHDL 200X:
Modeling Enhancements: S. Bailey (30 mins)
System Level Requirements: Greg Peterson (30 mins)
Lunch
Afternoon:
Set aside for in-depth technical discussions.
Currently, John Willis has requested an hour for
detailed discussions of VHDL '98 issues of particular
import to EIAJ.
The remaining time can be used for any other
issues which may come up in the morning or that
EIAJ would like to discuss in more detail than what
time would permit in the morning.
I will be staying at the Pan-Pacific Hotel in Yokohama
(arriving 8 Feb).
Stephen Bailey
VeriBest Inc.
6101 Lookout Rd., Suite A
Boulder, CO 80301
mailto:sbailey@veribest.com http://www.veribest.com
voice: 303-581-2467 fax: 303-581-9972