Your explanation is quite reasonable. Good plan.
Ron
At 12:27 PM 12/9/97 -0600, Bailey, Stephen A (Steve) wrote:
>Ron,
>
>> I have a question on scope of modeling enhancements with respect to
>> system
>> design language requirements. There is in interplay between the
>> modeling
>> capabilities for requirements and specification modeling, and the
>> language
>> requirements to accommodate such modeling activities at the system
>> design
>> level. Such modeling capabilities are needed at the system level. My
>> question is how shall the VASG ensure that the correct degree of
>> interplay
>> takes place between Wolfgang's and Greg's groups. Undoubtedly, many
>> people
>> will contribute to both groups. But people overlap is probably
>> insufficient.
>>
>You are correct that there is potential for overlap. However, I believe
>the
>potential is limited and that the process will ensure that such overlaps
>are addressed prior to any language design effort. Here's why:
>
>1. The scope of modeling enhancements is the current VHDL language
>scope. So, it is only to the extent that some advanced users are
>currently
>using VHDL to do system level modeling that we may receive enhancement
>requests in the system design "edge" of the current language scope.
>
>2. The modeling enhancement and systems requirements committees are
>currently restricted to identifying user requirements at this point in
>time.
>Both committees will report back their findings to the VASG and then
>language design activities can begin. (In fact, in any areas of
>overlap,
>some effort at integrating those two areas must be done either
>immediately
>preceding language design or during language design.) So, let us let
>these
>two committees gather the data and then we shall see what overlaps, if
>any, exist.
>
>-Stephen Bailey
>
>
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