Your announcements are indeed good news. The people leading the activities
have my full support.
I have a question on scope of modeling enhancements with respect to system
design language requirements. There is in interplay between the modeling
capabilities for requirements and specification modeling, and the language
requirements to accommodate such modeling activities at the system design
level. Such modeling capabilities are needed at the system level. My
question is how shall the VASG ensure that the correct degree of interplay
takes place between Wolfgang's and Greg's groups. Undoubtedly, many people
will contribute to both groups. But people overlap is probably insufficient.
My suggestion is that the two groups jointly lay out a roadmap of sorts, to
establish the points of interaction, both technical and in point of time, to
try to eliminate the fixups that might otherwise be needed down the road.
I submit this idea as a constructive proposal to the progress and success of
the VASG. Comments on this proposal are welcome.
Regards,
Ron Waxman
At 09:48 AM 12/9/97 -0600, Bailey, Stephen A (Steve) wrote:
>I have 3 announcements:
>
>1. Wolfgang Ecker has agreed to co-chair the modeling enhancement
>activity. Wolfgang has already provided several enhancement requests
>and actively participated in the recent Birds of a Feather meeting at
>the
>Fall VIUF. As a member of Siemens' corporate R&D center in Munich,
>Wolfgang has broad & direct exposure to the "user's perspective." He
>has also
>been an active contributor in past VIUFs. I'm very pleased that
>Wolfgang
>has accepted my invitation to co-chair. You can contact Wolfgang at
>mailto:wolfgang.ecker@mchp.siemens.de.
>
>2. Greg Peterson has agreed to lead the 200x related effort of
>identifying
>language requirements for supporting systems and systems-on-chip
>design. He will be following up the initial thoughts and ideas
>identified
>at the 1st Future of VHDL Workshop from the Fall '96 VIUF. Greg can
>be reached at: mailto:gdp@vhdl.org.
>
>I believe we now have all of the important areas for "VHDL 200x"
>covered:
>
> - VHDL PLI: Francoise Martinolle (fm@cadence.com)
> - VHDL Simulation Output Format: Paul Menchini (mench@mench.com)
> - Modeling Enhancements: Wolfgang Ecker
>(wolfgang.ecker@mchp.siemens.de)
> - System-Level Requirements: Greg Peterson (gdp@vhdl.org)
>
>Note 1: VHDL 200x is a catch-all term. The above activities may
>justify
> more than one round of balloting depending upon timing,
>etc.
> We need to let each committee pursue their technical areas
>further
> before identifying ballot timing and logistics.
>Note 2: If there are other areas of import which you believe should be
>addressed
> for VHDL 200x and you don't think they are covered by the
>above activities,
> please let me know.
>
>3. Shared Variables: The ballot package has been submitted to the
>IEEE.
>Hopefully, it is complete and the ballot packages will be distributed to
>the
>balloting group shortly. I requested a 60 day ballot period and
>coordination
>with IEC WG2. If IEC WG2 members need further help directly from me to
>facilitate the IEC review, please let me know.
>
>Stephen Bailey
>VeriBest Inc.
>6101 Lookout Rd., Suite A
>Boulder, CO 80301
>mailto:sbailey@veribest.com http://www.veribest.com
>voice: 303-581-2467 fax: 303-581-9972
>
>
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Ronald Waxman rwaxman@ibm.net
EDA Standards Consulting fax: (+1) (703) 620-6716
Visiting Principal Scientist at UVa
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