CATEGORY,IQNUM,LEVEL,DESCRIPTION
OPTIONAL,2.9,{OPTIONAL},[Disclaimer] and [Copyright]
OPTIONAL,3.2.4,{OPTIONAL},[Pin] RLC complete
REQUIREMENT,2.2,{LEVEL 0},Latest [IBIS ver] used
REQUIREMENT,2.3,{LEVEL 0},Do not use [Comment Char]
REQUIREMENT,2.7,{LEVEL 0},[Source] is complete
REQUIREMENT,2.8,{LEVEL 0},[Notes] is complete
REQUIREMENT,3.3.2,{LEVEL 0},[Diff Pin] Vdiff and Tskew complete and reasonable
REQUIREMENT,3.4.2,{LEVEL 1},[Model Selector] first [Model] is default
REQUIREMENT,4.1.13,{LEVEL 1},[Model] timing test load subparameters complete
REQUIREMENT,4.1.5,{LEVEL 2a},[Model] C_comp SPICE correlation
REQUIREMENT,4.1.6,{LEVEL 2b},[Model] C_comp laboratory correlation
REQUIREMENT,4.2.1,{LEVEL 0},[Model] Vinl and Vinh complete
REQUIREMENT,4.2.13,{LEVEL 1},[Model Spec] S_Overshoot subparameters complete
REQUIREMENT,4.2.16,{LEVEL 1},[Model Spec] D_Overshoot subparameters complete
REQUIREMENT,4.2.5,{LEVEL 1},[Model Spec] Vinl and Vinh complete
REQUIREMENT,4.2.6,{LEVEL 0},[Model Spec] Vinl+/- and Vinh+/- complete,,,
REQUIREMENT,4.2.9,{LEVEL 1},[Model Spec] Pulse subparameters complete,,,
REQUIREMENT,4.5.2,{LEVEL 1},[Ramp] R_load present if value other than 50 ohms,,,
TEST,2.1,{LEVEL 0},Header passes IBISCHK,,,
TEST,2.4,{LEVEL 0},[File Name] is correct,,,
TEST,2.5,{LEVEL 0},[File Rev] is correct,,,
TEST,2.6,{LEVEL 0},[Date] is correct,,,
TEST,5.1,{LEVEL 0},Typ/min/max order of parameters correct,,,
TEST,5.1,{LEVEL 1},Open_sink/Open_source model not push-pull,,,
TEST,5.11,{LEVEL 1},All pins consistent with data sheet,,,
TEST,5.2,{LEVEL 1},C_comp checked in both input and output mode,,,
TEST,5.3,{LEVEL 1},First/last point of waveforms equal to V_fixture values,,,
TEST,5.4,{LEVEL 1},Sufficient points in waveform table,,,
TEST,5.5,{LEVEL 1},Minimize waveform lead-in time,,,
TEST,5.6,{LEVEL 1},Open_sink/Open_source model with correct Vref, Cref, Rref, Vmeas
TEST,5.7,{LEVEL 1},Differential models contain appropriate waveform tables,,,
TEST,5.8,{LEVEL 1},Models correspond to data sheet
TEST,5.9,{LEVEL 0},Model_type correct for model data
TEST,3.1.1,{LEVEL 0},[Package] must have typical values
TEST,3.1.2,{LEVEL 0},[Package] Parasitics must be reasonable
TEST,3.1.3,{LEVEL 0},[Define Package Model] present if [Package Model] is present
TEST,3.1.4,{LEVEL 1},[Package] parasitics are validated against data sheet
TEST,3.2.1,{LEVEL 0},[Pin] section complete
TEST,3.2.2,{LEVEL 0},[Pin] model names not too long
TEST,3.2.3,{LEVEL 0},[Pin] models present in file
TEST,3.2.5,{LEVEL 1},[Pin] RLC parasitics are validated against data sheet
TEST,3.3.1,{LEVEL 0},[Diff Pin] referenced pins exist
TEST,3.3.3,{LEVEL 1},[Diff Pin] Vdiff and Tskew correct
TEST,3.3.4,{LEVEL 1},[Diff Pin] referenced pin models matched
TEST,3.4.1,{LEVEL 0},[Model Selector] referenced [Model]s exist
TEST,4.1.1,{LEVEL 0},[Model] parameters have correct typ/min/max order
TEST,4.1.10,{LEVEL 1},[Pulldown Reference] is reasonable
TEST,4.1.11,{LEVEL 1},[POWER Clamp Reference] is reasonable
TEST,4.1.12,{LEVEL 1},[GND Clamp Reference] is reasonable
TEST,4.1.2,{LEVEL 0},[Model] Model_type
TEST,4.1.3,{LEVEL 0},[Model] C_comp is reasonable
TEST,4.1.4,{LEVEL 1},[Model] C_comp is correct
TEST,4.1.7,{LEVEL 1},[Temperature Range] is reasonable
TEST,4.1.8,{LEVEL 1},[Voltage Range] or [* Reference] is complete
TEST,4.1.9,{LEVEL 1},[Pullup Reference] is reasonable
TEST,4.2.10,{LEVEL 1},[Model Spec] Pulse_high greater than Vinh
TEST,4.2.11,{LEVEL 1},[Model Spec] Pulse_low less than Vinl
TEST,4.2.12,{LEVEL 1},[Model Spec] Pulse_time reasonable
TEST,4.2.14,{LEVEL 1},[Model Spec] S_Overshoot subparameters match data sheet
TEST,4.2.15,{LEVEL 1},[Model Spec] S_Overshoot subparameters track typ/min/max
TEST,4.2.17,{LEVEL 1},[Model Spec] D_Overshoot subparams exceed S_Overshoot
TEST,4.2.2,{LEVEL 1},[Model] Vinl and Vinh correct
TEST,4.2.3,{LEVEL 1},[Model] Vinl and Vinh enclose Vmeas
TEST,4.2.4,{LEVEL 1},[Model] Vmeas matches data sheet
TEST,4.2.7,{LEVEL 0},[Model Spec] Vinl+/Vinh+ greater than Vinl-/Vinh-
TEST,4.2.8,{LEVEL 1},[Model Spec] Vinl+/- and Vinh+/- enclose Vmeas
TEST,4.3.1,{LEVEL 0},I-V tables complete
TEST,4.3.10,{LEVEL 1},[Pulldown] I-V tables pass through zero/zero
TEST,4.3.11,{LEVEL 1},[Pullup] I-V tables pass through zero/zero
TEST,4.3.12,{LEVEL 1},No leakage current in clamp I-V tables
TEST,4.3.13,{LEVEL 1},Clamp I-V behavior not double-counted
TEST,4.3.14,{LEVEL 1},On-die termination modeling documented
TEST,4.3.15,{LEVEL 1},ECL models I-V tables swept from -Vdd  to +2 Vdd.
TEST,4.3.16,{LEVEL 1},Point distributions in IV curves should be sufficient
TEST,4.3.17,{LEVEL 2},Correlate IV curves to combined curves.
TEST,4.3.2,{LEVEL 1},I-V tables have correct typ/min/max order
TEST,4.3.3,{LEVEL 1},I-V tables have reasonable numerical range
TEST,4.3.4,{LEVEL 1},[Pullup] voltage sweep range is correct
TEST,4.3.5,{LEVEL 1},[Pulldown] voltage sweep range is correct
TEST,4.3.6,{LEVEL 1},[Power Clamp] voltage sweep range is correct
TEST,4.3.7,{LEVEL 1},[GND Clamp] voltage sweep range is correct
TEST,4.3.8,{LEVEL 1},I-V tables do not exhibit stair-stepping
TEST,4.3.9,{LEVEL 1},Combined I-V tables are monotonic
TEST,4.4.2,{LEVEL 0},V-T table endpoints consistent with I-V tables
TEST,4.4.3,{LEVEL 1},V-T tables look reasonable
TEST,4.4.4,{LEVEL 1},Model simulation successful
TEST,4.4.5,{LEVEL 1},Document known model limitations
TEST,4.4.6,{LEVEL 1},Output and IO buffers have should have 2 sets of V-T tables
TEST,4.5.1,{LEVEL 0},Output and IO buffers have a [Ramp] section
TEST,4.5.3,{LEVEL 1},[Ramp] test fixture has no reactives
TEST,4.5.4,{LEVEL 1},[Ramp] typ/min/max order is correct
TEST,4.5.5,{LEVEL 1},[Ramp] data dv and dt values positive
TEST,4.5.6,{LEVEL 1},[Ramp] dV consistent with supply voltages
TEST,4.5.7,{LEVEL 1},[Ramp] dV consistent with V-T table endpoints
TEST,4.5.8,{LEVEL 1},[Ramp] dt is consistent with 20%-80% crossing time
TEST,4.5.9,{LEVEL 1},[Ramp] dt is consistent with data sheet