From owner-ibis  Wed Sep  1 15:36:57 1999
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Date: Wed, 1 Sep 1999 15:30:38 -0700 (PDT)
From: Raymond Chen <sigrity@yahoo.com>
Reply-To: chen@sigrity.com
Subject: RE: Paper on IBIS simulation algorithm
To: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
Cc: ibis-users@eda.org, si-list@silab.eng.sun.com
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Andy and Larry,
  We did some studies on IBIS simulation techniques
and algorithms back to 1996, and we did publish a
pretty detailed paper on that topic at 1996 ECTC
conference. You can download that file from our web
page at http://www.sigrity.com/support.htm, which is
the 11th paper titled as "Extraction of Transient
Behavioral Model of Digital I/O Buffers from IBIS".
That paper pointed out how to implement a simulation
algorithm to extract the transient behavior of ibis
model from the static I-V curve and V-T curve so you
can later simulate different load situations without
knowing the transistor level details. Hope that will
help.

Raymond Chen


--- "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
wrote:
> Larry Forsythe wrote:
> 
> >I'm confused about how IBIS is used in actual
> simulations. I haven't seen
> >any articles about this (please indicate if there
> are some).
> 
> And you might not find any that go into much detail.
>  The actual algorithm
> used by each simulator, especially as to how it
> handles the V-T data, might
> be a guarded secret.
> 
> > What I'm
> >confused about is how can a few static I-V curves
> and some V-T curves done
> >at specific loads be used to simulate other loads.
> The I-V curves involve
> >fully on transistors. The V-T curves involve
> partially turned-on
> transistors
> >driving a specific load.
> 
> Typically, an output buffer interacts with its load
> over a period of several
> nanoseconds while the signal rattles around and
> eventually settles.  Yet the
> time it spends actually changing -- the time for the
> drive to its output
> transistors to switch -- is much less, perhaps a few
> hundred picoseconds.
> It is a fair approximation to treat the output
> buffer as if it were static
> (defined by one I-V curve or the other) almost all
> of the time.  In between
> the two, it makes some sort of transition from one
> I-V curve to another, in
> a relatively short interval, the effects of which
> might be swamped by the
> interaction with the load.
> 
> > Is it valid to scale the I-V curves using the V-T
> >curves in order to derive the response to driving
> other loads?
> 
> Here's where you get into the proprietary details of
> each simulator's
> vendor.
> 
> If you're lucky, the load for the V-T curves is
> close to the trace
> characteristic impedance.
> 
> > Can the I-V
> >curves and V-T curves be used to determine the
> characteristics of a
> >partially turned on transistor driving a different
> load-I guess that is the
> >source of my confusion.
> 
> To varying degrees, apparently yes.
> 
> Regards,
> Andy Ingraham
> 
> 
> 


===
-------- Currently on leave for Intel projects --------
Office Phone: 253.371.4261  Mobile Phone: 408.718.3080
-------------------------------------------------------
Sigrity, Inc.                     Tel: 408.377.2180
2105 Hamilton Ave. Suite 310      Fax: 408.377.2565
Santa Clara, CA 95125             Web: www.sigrity.com
__________________________________________________
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From owner-ibis  Thu Sep  2 07:32:44 1999
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From: "Richard A. Schumacher" <schumach@valencia.rsn.hp.com>
Message-Id: <199909021425.JAA15560@valencia.rsn.hp.com>
Subject: RE: Paper on IBIS simulation algorithm
To: chen@sigrity.com
Date: Thu, 02 Sep 1999 9:25:49 CDT
Cc: Andrew.Ingraham@compaq.com, ibis-users@eda.org, si-list@silab.eng.sun.com
In-Reply-To: <19990901223038.14975.rocketmail@web1404.mail.yahoo.com>; from "Raymond Chen" at Sep 1, 99 3:30 pm
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>   We did some studies on IBIS simulation techniques
> and algorithms back to 1996, and we did publish a
> pretty detailed paper on that topic at 1996 ECTC
> conference. You can download that file from our web
> page at http://www.sigrity.com/support.htm, which is
> the 11th paper titled as "Extraction of Transient
> Behavioral Model of Digital I/O Buffers from IBIS".
> That paper pointed out how to implement a simulation
> algorithm to extract the transient behavior of ibis
> model from the static I-V curve and V-T curve so you
> can later simulate different load situations without
> knowing the transistor level details. Hope that will
> help.
> 
> Raymond Chen

Which vendors have implemented this algorithm?
Who has tested such implementations with measurements
of real devices in real circuits?

regards,
Richard Schumacher
Hewlett Packard Company

From owner-ibis  Thu Sep  2 11:23:36 1999
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From: Raymond Chen <sigrity@yahoo.com>
Reply-To: chen@sigrity.com
Subject: RE: Paper on IBIS simulation algorithm
To: "Richard A. Schumacher" <schumach@valencia.rsn.hp.com>
Cc: ibis-users@eda.org, si-list@silab.eng.sun.com
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Richard,
  The paper "Extraction of Transient Behavioral Model
of Digital I/O Buffers from IBIS" was the result of
university research. I am not aware if any vendors
have implemented the scheme. No measurements were done
that time. The verification was done through the
comparison with SPICE transistor level simulation,
which gave good correlation.

Raymond Y. Chen
Sigrity, Inc.

--- "Richard A. Schumacher"
<schumach@valencia.rsn.hp.com> wrote:
> >   We did some studies on IBIS simulation
> techniques
> > and algorithms back to 1996, and we did publish a
> > pretty detailed paper on that topic at 1996 ECTC
> > conference. You can download that file from our
> web
> > page at http://www.sigrity.com/support.htm, which
> is
> > the 11th paper titled as "Extraction of Transient
> > Behavioral Model of Digital I/O Buffers from
> IBIS".
> > That paper pointed out how to implement a
> simulation
> > algorithm to extract the transient behavior of
> ibis
> > model from the static I-V curve and V-T curve so
> you
> > can later simulate different load situations
> without
> > knowing the transistor level details. Hope that
> will
> > help.
> > 
> > Raymond Chen
> 
> Which vendors have implemented this algorithm?
> Who has tested such implementations with
> measurements
> of real devices in real circuits?
> 
> regards,
> Richard Schumacher
> Hewlett Packard Company
> 
> 

===
-------- Currently on leave for Intel projects --------
Office Phone: 253.371.4261  Mobile Phone: 408.718.3080
-------------------------------------------------------
Sigrity, Inc.                     Tel: 408.377.2180
2105 Hamilton Ave. Suite 310      Fax: 408.377.2565
Santa Clara, CA 95125             Web: www.sigrity.com
__________________________________________________
Do You Yahoo!?
Bid and sell for free at http://auctions.yahoo.com
From owner-ibis  Thu Sep  2 13:54:40 1999
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Other than hacking them into the resultant IBIS model is there a  way to
insert Vinh and Vinl into the control files for s2ibs model generator
from NCSU. I've tried putting them into the control files but s2ibis
doesn't like it.


Thanks,
-- 
Bruce Frederick

Transmeta Corp.
(408) 919-6323
From owner-ibis  Thu Sep  2 14:45:24 1999
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Date: Thu, 2 Sep 1999 14:38:19 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: vinl/vinh parameter insertion
To: ibis-users@eda.org, brucef@transmeta.com
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Bruce,

If your Model_type is 'Output', it maynot insert those parameters in. Are
you using s2ibis2 or s2ibis ?

Regards,
Syed
Cisco Systems, Inc

> X-SMAP-Received-From: outside
> Date: Thu, 02 Sep 1999 13:47:38 -0700
> From: Bruce Frederick <brucef@transmeta.com>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: ibis-users@eda.org
> Subject: vinl/vinh parameter insertion
> Content-Transfer-Encoding: 7bit
> 
> Other than hacking them into the resultant IBIS model is there a  way to
> insert Vinh and Vinl into the control files for s2ibs model generator
> from NCSU. I've tried putting them into the control files but s2ibis
> doesn't like it.
> 
> 
> Thanks,
> -- 
> Bruce Frederick
> 
> Transmeta Corp.
> (408) 919-6323

From owner-ibis  Thu Sep  2 18:54:17 1999
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Hello,

I'm Sung-Ki Lim of computer division in Samsung Electronics.
I'd like to participate in IBIS group.
Please add my email address to the reflector's distribution list.

lsk1101@samsung.co.kr

Thank you for your attention and have a nice day.
Bye.

From owner-ibis  Tue Sep  7 12:23:28 1999
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From: Roy Gao <Roy.Gao@idt.com>
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To: ibis-users@eda.org
Subject: Spectre to create IBIS
Cc: arthur@Eng.idt.com, anwar@Eng.idt.com

Dear IBIS users,

When I try to use spectre to create IBIS models, I met a problem:

If there are current curves like Power-clamp or Pull-down, when I check model file, it always said like:
pull-down has Decreasing Current or so.

I observed the testbench created for that curve and found that in Spectre testbench, it will record all terminal currents of a component, so in output file there will be two set of currents values of voltage source, one is positive and one is negetive or vice versa. Unfortunately, IBIS creation will use the wrong set of current values and so the curve will be wrong. Since IBIS command file will create the test bench automatically, I can't control it.

I wonder if you have ever used spectre for IBIS model or have some good idea. 

Thank you for your time.

Roy
From owner-ibis  Tue Sep  7 20:35:20 1999
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To: Roy Gao <Roy.Gao@idt.com>
CC: ibis-users@eda.org, arthur@Eng.idt.com, anwar@Eng.idt.com
Subject: Re: Spectre to create IBIS
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Roy,

It sounds like you are using s2ibis. I use s2ibis with Spectre and have not
seen this problem. However, I see that half of the simulations run by s2ibis 
save current values with a a statement like:

VOUTS2I pad 0 vsource type=dc dc=0
...
save VOUTS2I:currents

and this generates plot data like:

Plotname: DC Analysis `DCsweep': VOUTS2I:dc = (5.5 V -> 10.5 V)
Flags: real
No. Variables:        3
No. Points:       51
Variables:      0       dc      V
                1       VOUTS2I:n       A plot=0 grid=0
                2       VOUTS2I:p       A plot=0 grid=0
...

So conceivably the positive terminal of VOUTS2I might be reported first,
causing s2ibis to get reversed data. Is this happening in your case? And
I wonder why it might happen only sometimes?

Mike

Roy Gao wrote:
> 
> Dear IBIS users,
> 
> When I try to use spectre to create IBIS models, I met a problem:
> 
> If there are current curves like Power-clamp or Pull-down, when I check model file, it always said like:
> pull-down has Decreasing Current or so.
> 
> I observed the testbench created for that curve and found that in Spectre testbench, it will record all terminal currents of a component, so in output file there will be two set of currents values of voltage source, one is positive and one is negetive or vice versa. Unfortunately, IBIS creation will use the wrong set of current values and so the curve will be wrong. Since IBIS command file will create the test bench automatically, I can't control it.
> 
> I wonder if you have ever used spectre for IBIS model or have some good idea.
> 
> Thank you for your time.
> 
> Roy
From owner-ibis  Tue Sep 14 15:07:40 1999
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Date: Tue, 14 Sep 1999 15:59:25 -0400
To: ibis-users@eda.org
From: Kathy Breda <breda@nesa.com>
Subject: REMINDER - IBIS User's Group Meeting WEDS. 9/15/99 @ 3:00 pm @
  NESA
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REMINDER MESSAGE - IBIS Users Group to be held tomorrow:

The summer is winding up and it is time to move IBIS activities
forward again.  We also need to discuss the upcoming IBIS Summit
being held at the Marlboro Holiday Inn on October 14th.


Date:     WEDNESDAY - September 15, 1999
Time:     3:00 pm - 5:00 pm
Location: North East Systems Associates, Inc.(NESA), Stow, MA

If you have not already, please let me know if you'll be joining us 
and if you would like to connect by telephone conference.

Regards,

   Kathy Breda

FYI - Directions to NESA can be found on our website:
http://www.nesa.com/map.html

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |
|      -------------------------------------      |
|     "High Performance Engineering & Design"     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Kathy Breda             e-mail: breda@nesa.com  |
| NESA, Inc.              http://www.nesa.com/    |
| 636 Great Road          Tel +1.978.897-8787     |
| Stow, MA 01775 USA      Fax +1.978.897-5359     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
From owner-ibis  Thu Sep 16 09:39:24 1999
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Date: Thu, 16 Sep 1999 09:38:13 -0700
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Hello IBIS group,

I read the IBIS Accuracy Specification v.1.2 which mentioned (in the
Reference section) that an IBIS Accuracy Test Board Application Note was
forthcoming.  I was just wondering if I could perhaps get some
preliminary information regarding this, since I will be building a
Signal Integrity Test Board in the near future.

Thank you for your assistance,
- Yash Mody
App.Eng. @ PMC-Sierra
From owner-ibis  Fri Sep 17 17:52:27 1999
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From: "Chen, Run (chenru)" <chenru@sequent.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: Questions regarding IBIS2SPICE Converter
Date: Fri, 17 Sep 1999 17:51:45 -0700
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Dear ibis-users:

 I have some questions for IBIS2SPICE Converter.
 I don't understand some of the codes in template.mdl under IBIS2SPICE
 Converter. Hspice doesn't recognize these codes. These codes are the
 followings:
 
 ********************************************************************
 * Input Control
 B1 820 0 V=V(100) & V(500)
 B2 830 0 V= V(500) & ~V(100)
 
 * Up and Down Ramps
 B3 300 850 I= V(830) > 1.2   ? 0 : V(300,850) / {RTR}
 
 S1 220 850 0 820 SMOD
 S2 840 220 0 830 SMOD
 .MODEL SMOD SW RON=.1M ROFF=1E15 VT=-1.2 VH=.1
 **********************************************************************
 
 If you could explain me what the above codes mean and how I can modify
 them into hspice codes, I would appreciate it. 
 
 Regards,
 
 Run Chen
 Sequent Computer Systems Inc.
 

From owner-ibis  Tue Sep 21 11:47:10 1999
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From: "eh" <elisimi@netvision.net.il>
To: <ibis-users@eda.org>
Subject: Veribest Signal Integrity  - crosstalk simulation, no IBIS models
Date: Tue, 21 Sep 1999 19:43:20 +0200
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Dear Sir/Mrs.,
I've heard that it is possible to simulate a layout and look for =
crosstalk problems,
even without IBIS models. The simulation will not be that accurate , and =
it's OK with me.
What I need to supply is that all the devices will have pin i/o =
direction specified
on the VBDC , and I've done it.
I don't know how to supply the technology of the devices.
I'm using Veribest tools, 1998.
Have you heard about it ?
Regards
Simi Eshkol

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN">
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<HEAD>

<META content=3D"text/html; charset=3Dwindows-1255" =
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Dear =
Sir/Mrs.,</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>I've heard that it is =
possible to=20
simulate a layout and look for crosstalk problems,</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>even without IBIS =
models.=20
</FONT><FONT color=3D#000000 face=3DArial size=3D2>The simulation will =
not be that=20
accurate , and it's OK with me.</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>What I need to supply =
is that all the=20
devices will have pin i/o direction specified</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2></FONT><FONT =
face=3DArial size=3D2>on the=20
VBDC , and I've done it.</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>I don't know how to =
supply the=20
technology of the devices.</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>I'm using Veribest =
tools,=20
1998.</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Have you heard about it =

?</FONT></DIV>
<DIV><FONT color=3D#000000 face=3DArial size=3D2>Regards</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Simi Eshkol</FONT></DIV></BODY></HTML>

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From owner-ibis  Tue Sep 21 13:22:23 1999
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From: Roy Gao <Roy.Gao@idt.com>
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Message-Id: <199909212022.NAA03225@mig.Eng.idt.com>
To: ibis-users@eda.org
Subject: when vdd=2.5V
Cc: sangho@Eng.idt.com

Dear IBIS users,

After I create IBIS models (vdd=3.3v) for my i/o buffer, I change vdd to 2.5v and try again. Everthing seems fine expect that at the end of pull-up/pull-down section in IBIS model file, after -2.5v ~ 5.0v sweep, it will add a few lines which I attach here, I try a few buffers and got the same results. I wonder if s2ibis2 can't handle vdd=2.5v?

Thank you for your help!

-------------------------
  -2.50      -0.108A            -66.400mA            -0.124A
  -2.30      -0.108A            -65.600mA            -0.125A
    .           .                   .                   .
    .           .                   .                   .
    .           .                   .                   .
    .           .                   .                   .
   4.80       0.169A              0.173A              0.171A
   5.00       0.192A              0.194A              0.195A
   0.00     1.082e-312A         3.395e-313A         1.401e-312A
   0.00       0.000A              0.000A              0.000A
   0.00       0.000A              0.000A              0.000A
   5.00       0.192A              0.194A              0.195A
-----------------------------

Roy
IDT Inc.
From owner-ibis  Wed Sep 22 08:59:20 1999
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From: "Hobbs, Will" <will.hobbs@intel.com>
To: "'Bob Ross'" <bob_ross@mentorg.com>, ibis@eda.org, ibis-users@eda.org
Subject: RE: IBIS Version 3.2 - ANSI/EIA-656-A
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Congratulations everyone, and thanks for all your hard work!!

Will Hobbs
Intel Corp.
(and Former Chair-- that's an official position isn't it?)

-----Original Message-----
From: Bob Ross [mailto:bob_ross@mentorg.com]
Sent: Wednesday, September 22, 1999 8:37 AM
To: ibis@eda.org; ibis-users@eda.org
Cc: bob_ross@mentorg.com
Subject: IBIS Version 3.2 - ANSI/EIA-656-A


To All:

Cecilia Fleming of EIA has just informed me that ANSI has
approved IBIS Version 3.2.  The document now is designated:

  ANSI/EIA-656-A

Congratulations to all who have worked hard over the years to
initiate and consider the issues and to produce the document.

Bob Ross
Chair., EIA IBIS Open Forum
Mentor Graphics
From owner-ibis  Wed Sep 22 08:37:17 1999
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To All:

Cecilia Fleming of EIA has just informed me that ANSI has
approved IBIS Version 3.2.  The document now is designated:

  ANSI/EIA-656-A

Congratulations to all who have worked hard over the years to
initiate and consider the issues and to produce the document.

Bob Ross
Chair., EIA IBIS Open Forum
Mentor Graphics
From owner-ibis  Thu Sep 23 14:34:07 1999
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From: apanella@molex.com
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Date: Thu, 23 Sep 1999 16:27:19 -0500
Message-ID: <0004E6E0.C21030@molex.com>
Subject: RE: package and connector model questions
To: Aubrey_Sparkman@dell.com, kellee@hyperlynx.com, ibis-users@eda.org,
        mbflora@hyperlynx.com, bob_ross@mentorg.com, ibis@eda.org
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Aubrey,

There are rough drafts of this wording... created...  They are now under review.
 These descriptions are really to describe the format of the values in the
matrices (as related to the final simulation)

I would suggest a review of the samples may assist in understanding the
specification.  Most (all?) of the points you bring up are covered in the
specification...  however... to implement this... a rather complex format was
needed to be created.  I think the examples may be helpful in clearing up the
issues.

As an off note....  the IBISCnn specification is not a part of the general  IBIS
v3.2 spec....  maaybe the next one???


I'll try to address your specific questions now...


Re "unmated connector"
Need these to represent connectors that are not mated but are still on the bus. 
For instance, an empty PCI slot in a PC. 

Re: "Part of Package Modeling Spec..."
The package modeling spec does not have stubs, cascaded models, swath, other?? 
As such,  instead, maybe packages could be represented by the connector spec.

Re: "Trace to Trace Coupling Effects
The off diagonals of the matrices take care of the coupling.  The distributed
effects are handled by the "cascaded sections".  These cascaded sections also
allow the series connection of SLMs and MLMs in series or as stubs in the same
model.

The "Sections" area of the specification allows the installation of as many
matrices in a model as required....  These sections can then be hooked up in the
"Begin_Connector" area.  There are examples that contain multiple cascaded
sections.

Re: "Min / Max LC values"
These values are typically very tightly controlled in the final assembled
connector...  More variability in LC is always in the process where the
connector gets mounted to a board.  (Solder hole fill, board warp, connector
floating during a reflow, other..)

Best Regards,

Gus

apanella@molex.com


-----Original Message-----
From: Aubrey_Sparkman@Dell.com 
Sent: Thursday, September 23, 1999 3:59 PM
To: kellee@hyperlynx.com; ibis-users@eda.org; mbflora@hyperlynx.com;
bob_ross@mentorg.com; ibis@eda.org
Subject: package and connector model questions


Hello ibis-users.  I am new to the discussion group -- joined the end of
July.  I have read through the Version 3.2 spec and the ibisConSpec
documents and I have 2 questions.

The first question has to do with Kellee's outstanding item below.  I.E.,
why not use the RLC matrix description in section 7 on package modeling?  I
am not sure why Connector modeling isn't (or couldn't be) a subset of the
package modeling spec.  After all, a package is a connector that connects
the silicon to a PCB....or socket, which is again another connector.  And
before someone comments "un-mated connector" I also wonder why I need the
model for an unmated connector or a package out of the socket, etc.

But there are some excellent modeling enhancements in the connector spec
such as Begin/End_Cn_Swath.  Great way to simplify what could be an
unnecessarily large matrix.  Can we put this in the package model section?
At least where possible, let's keep (or copy) everything that is or could be
the same.  And I also like the ability to name and therefore have more than
one RLC matrix.

Which brings me to my second (and more important to me) question.  As I read
section 7 of Ver 3.2, I can have only one RLC matrix set.  I can't put two
RLC sets in series.  Or, if I want to do distributed effects, I can do
sections (a wire bond section, a trace section, a via section, another trace
section, etc) but I can NOT have "trace to trace" coupling effects.  And I
can not connect several uncoupled sections to the single RLC matrix which
would at least give me some coupling.  Is this a correct statement of my
options?

I was hoping for the ability to connect more than one matrix in series.
And since the point of having a matrix is the coupling, I was also looking
for the typ, min, and max coupled matrix for L and C.

Is this too much for one message?

Thanks for your consideration and patience,
Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


-----Original Message-----
From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
Sent: Monday, August 23, 1999 12:56 PM
To: ibis-users@eda.org; Matthew Flora
Subject: Re: USB connector model 


Hi Ibisians, Matt,

  Matt thanks for giving the correct web address for the preliminary
connector specification.

FYI.. The only outstanding item in the connector specification is to agree
on the
wording of the RLC matrix description.  I have asked several industry
experts to
write it and have not received one from anyone yet.  If someone else out
their
would like to contribute a technically correct RLC matrix description that
would
allow someone "skilled in the art" to understand which type of RLC matrix
is being
used I am interested.  If I end up with more than one I would be extremely
happy.
It must have a simple included example of both a physical cross section and
the
resulting matrices.  Ideally it would explain things like what the diagonal
is and
why there are sometimes negative signs.
When we receive this and the connector sub-group reviews it and accepts it
I believe we are ready to give it to the IBIS group as a bird.

At 10:28 AM 8/23/99 -0700, you wrote:
>> Wilco Hamhuis writes:
>> > I have two short questions: Is IBIS capable of describing a (coupled)
>> > connector? Are there IBIS USB connector models available? I am
currently
>> > analysing a high speed board (app. 500 MHz) and I want to take the
effect
>of
>> > connectors into account.
>>
>>   There is an IBIS working group that has proposed an IBIS extension for
>> connectors that supports coupling, but it has not yet become
>> a part of the official standard.  If you are interested, a copy of the
>> proposal is on the Hyperlynx website at www.hyperlynx.com.  As for your
>> specific need, I am not aware of any IBIS USB connector models, but
others
>> may know of some.
>
>Actually, the proposed IBIS extension for connectors can best be found at:
>ftp://ftp.eda.org/pub/ibis/connector/
>
>Regards,
>Matthew Flora
>IBIS Open Forum Postmaster
>(425) 869-2320 PH
>(425) 881-1008 FAX
>mbflora@hyperlynx.com
>HyperLynx, 14715 NE 95th Street, Redmond, WA 98052 USA
> 


From owner-ibis  Thu Sep 23 14:02:18 1999
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To: kellee@hyperlynx.com, ibis-users@eda.org, mbflora@hyperlynx.com,
        bob_ross@mentorg.com, ibis@eda.org
Subject: package and connector model questions
Date: Thu, 23 Sep 1999 15:59:04 -0500
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Hello ibis-users.  I am new to the discussion group -- joined the end of
July.  I have read through the Version 3.2 spec and the ibisConSpec
documents and I have 2 questions.

The first question has to do with Kellee's outstanding item below.  I.E.,
why not use the RLC matrix description in section 7 on package modeling?  I
am not sure why Connector modeling isn't (or couldn't be) a subset of the
package modeling spec.  After all, a package is a connector that connects
the silicon to a PCB....or socket, which is again another connector.  And
before someone comments "un-mated connector" I also wonder why I need the
model for an unmated connector or a package out of the socket, etc.

But there are some excellent modeling enhancements in the connector spec
such as Begin/End_Cn_Swath.  Great way to simplify what could be an
unnecessarily large matrix.  Can we put this in the package model section?
At least where possible, let's keep (or copy) everything that is or could be
the same.  And I also like the ability to name and therefore have more than
one RLC matrix.

Which brings me to my second (and more important to me) question.  As I read
section 7 of Ver 3.2, I can have only one RLC matrix set.  I can't put two
RLC sets in series.  Or, if I want to do distributed effects, I can do
sections (a wire bond section, a trace section, a via section, another trace
section, etc) but I can NOT have "trace to trace" coupling effects.  And I
can not connect several uncoupled sections to the single RLC matrix which
would at least give me some coupling.  Is this a correct statement of my
options?

I was hoping for the ability to connect more than one matrix in series.
And since the point of having a matrix is the coupling, I was also looking
for the typ, min, and max coupled matrix for L and C.

Is this too much for one message?

Thanks for your consideration and patience,
Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


-----Original Message-----
From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
Sent: Monday, August 23, 1999 12:56 PM
To: ibis-users@eda.org; Matthew Flora
Subject: Re: USB connector model 


Hi Ibisians, Matt,

  Matt thanks for giving the correct web address for the preliminary
connector specification.

FYI.. The only outstanding item in the connector specification is to agree
on the
wording of the RLC matrix description.  I have asked several industry
experts to
write it and have not received one from anyone yet.  If someone else out
their
would like to contribute a technically correct RLC matrix description that
would
allow someone "skilled in the art" to understand which type of RLC matrix
is being
used I am interested.  If I end up with more than one I would be extremely
happy.
It must have a simple included example of both a physical cross section and
the
resulting matrices.  Ideally it would explain things like what the diagonal
is and
why there are sometimes negative signs.
When we receive this and the connector sub-group reviews it and accepts it
I believe we are ready to give it to the IBIS group as a bird.

At 10:28 AM 8/23/99 -0700, you wrote:
>> Wilco Hamhuis writes:
>> > I have two short questions: Is IBIS capable of describing a (coupled)
>> > connector? Are there IBIS USB connector models available? I am
currently
>> > analysing a high speed board (app. 500 MHz) and I want to take the
effect
>of
>> > connectors into account.
>>
>>   There is an IBIS working group that has proposed an IBIS extension for
>> connectors that supports coupling, but it has not yet become
>> a part of the official standard.  If you are interested, a copy of the
>> proposal is on the Hyperlynx website at www.hyperlynx.com.  As for your
>> specific need, I am not aware of any IBIS USB connector models, but
others
>> may know of some.
>
>Actually, the proposed IBIS extension for connectors can best be found at:
>ftp://ftp.eda.org/pub/ibis/connector/
>
>Regards,
>Matthew Flora
>IBIS Open Forum Postmaster
>(425) 869-2320 PH
>(425) 881-1008 FAX
>mbflora@hyperlynx.com
>HyperLynx, 14715 NE 95th Street, Redmond, WA 98052 USA
> 


------_=_NextPart_000_01BF0606.7CA354B4
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N:Sparkman;Aubrey
FN:Sparkman, Aubrey
EMAIL;PREF;INTERNET:Aubrey_Sparkman@Dell.com
REV:19990728T212924Z
END:VCARD

------_=_NextPart_000_01BF0606.7CA354B4--
From owner-ibis  Fri Sep 24 00:15:07 1999
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Date: Thu, 23 Sep 1999 20:45:00 -0700
To: Aubrey_Sparkman@dell.com, kellee@hyperlynx.com, ibis-users@eda.org,
        mbflora@hyperlynx.com, bob_ross@mentorg.com, ibis@eda.org
From: Kellee Crisafulli <kellee@nwlink.com>
Subject: Re: package and connector model questions
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Hi Aubrey all,

At 03:59 PM 9/23/99 -0500, Aubrey_Sparkman@Dell.com wrote:
>The first question has to do with Kellee's outstanding item below.  I.E.,
>why not use the RLC matrix description in section 7 on package modeling?  I
>am not sure why Connector modeling isn't (or couldn't be) a subset of the
>package modeling spec.  After all, a package is a connector that connects
>the silicon to a PCB....or socket, which is again another connector.  And
>before someone comments "un-mated connector" I also wonder why I need the
>model for an unmated connector or a package out of the socket, etc.

Wow good comments... here is some of our thinking but many more
heads and ideas made these decisions than just mine.

The connector group made several decisions up front:
1) The specification should be stand-alone to remove the overhead
     associated with the IBIS IC specification which is getting
     very complex.   Several of the connector companies that were interested
     in using the connector specification expressed concern over the
     need to understand the full IBIS specification in order to make a
connector
     model.
2) The matrix descriptions must be compatible with the IBIS .pkg 
    specification.
3) The general syntax must be the same as the IBIS specification.
4)  Some of the concepts needed for connectors were missing from
    the .pkg specification and were much easier to accomplish as a stand
    alone specification.  You mentioned a few.  The biggest concern I
personally had
    is that since the specification was constrained to just connectors
there was less
    disagreement over what and how to do it.  We attempted this once before
    integrated in the main specification and the project failed.  One of
the reasons
    was difficulty getting agreement on how to proceed with various aspects.
    Another was different groups had different needs i.e. cables v.s.
connectors.
    v.s. IC packages and that added another set of problems that caused
disagreements.

I do believe the connector specification concepts and keywords could
be used to augment the .pkg model since the connector specification
is mostly a super set and contains many improvements.
The people in the connector group fully expected many of the features to
migrate directly to the .pkg specification over time.
We also have many other new features like support for .jpg images of the
connector
and web site and email paths that can be added directly into the file so a
user
can easily get the latest version model or contact the department that created
the model.  These features should probably migrated back into the IBIS IC
specification.  Can you image being able to access the correct web site by
just clicking on your connector model picture.  Or being able to email the
correct
department of the company that created the model by clicking on an email icon.
way... cool.  if the simulator folks pick up on it.

I found it is often a mistake to try and make one size shoe fit everyone.

If we can use the same shoe leather, laces and polish and manufacturing
equipment we are doing very good.  (i.e. the syntax is compatible and we
could re-use the concepts and keywords directly).  If the syntax is left
compatible the simulators should have an easy time supporting either
with the same code and parsers.

>But there are some excellent modeling enhancements in the connector spec
>such as Begin/End_Cn_Swath.  Great way to simplify what could be an
>unnecessarily large matrix.  Can we put this in the package model section?
>At least where possible, let's keep (or copy) everything that is or could be
>the same.  And I also like the ability to name and therefore have more than
>one RLC matrix.
Speaking for the connector sub group we appreciate the kind words .

>Which brings me to my second (and more important to me) question.  As I read
>section 7 of Ver 3.2, I can have only one RLC matrix set.  I can't put two
>RLC sets in series.  Or, if I want to do distributed effects, I can do
>sections (a wire bond section, a trace section, a via section, another trace
>section, etc) but I can NOT have "trace to trace" coupling effects.  And I
>can not connect several uncoupled sections to the single RLC matrix which
>would at least give me some coupling.  Is this a correct statement of my
>options?
>I was hoping for the ability to connect more than one matrix in series.
>And since the point of having a matrix is the coupling, I was also looking
>for the typ, min, and max coupled matrix for L and C.

The connector specification allows for as many series matrices as
you desire and the matrices may all be of different types.  So the
first matrix might be simple inductors to represent bond wires and
then a series of diagonal matrices to represent transmission lines
and then a series of full matrices to represent a coupled region.
This method could be added to the .pkg file very easily if the IBIS 
group desired.

I should be able to complete the final integration of feedback and release
the connector specification to the full IBIS group very soon.
  We have received comments from the full group already at 
DesignCon 99 and we are hoping for rapid acceptance.
I am only working 3 days a week so my schedule is limited and it
is taking longer than I would like to complete.  Hopefully within the next
one to two weeks.

best wishes...
Kellee

From owner-ibis  Fri Sep 24 10:21:51 1999
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Date: Fri, 24 Sep 1999 11:00:12 -0400
To: ibis-users@eda.org, ibis@eda.org
From: Kathy Breda <breda@nesa.com>
Subject: IBIS Summit - Thursday, 14-Oct-99 - AGENDA included
Mime-Version: 1.0
Content-Type: text/enriched; charset="us-ascii"

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

-------------------------------------------------------

<bold>IBIS SUMMIT 

	CALL FOR 

		PARTICIPATION, 

			PRESENTATIONS 

				& SPONSORSHIP!!!!

</bold>-------------------------------------------------------

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


             <bold>I B I S   S U M M I T   M E E T I N G

</bold>

Time/Date:      8:30 AM - 5:00 PM, Thursday, October 14, 1999


Location:       Marlboro Holiday Inn <bold>(NOT AT THE BOXBORO HOLIDAY
INN THIS YEAR)

</bold>                265 Lakeside Ave. 

                Marlboro, MA

                Tel:  (508) 481-3000

               

Content:        Presentations and Discussions


Purpose:        Solicit and Exchange IBIS Model Related Information and
Ideas.


Sponsors:       North East Systems Associates, Inc. (NESA), Hyperlynx,
Praegitzer Design

                 <bold>we are looking for other sponsors!

</bold>

PCB Conference: October 11-15, 1999

East            Royal Plaza Trade Center

                Marlborough, Massachusetts

                See http://www.pcbeast.com/ for more information.


<bold>BACKGROUND

</bold>

The IBIS Users Group (IBIS East) has been formed under the leadership of
Dr. 

Edward Sayre from North East Systems Associates (NESA) and has been
meeting

for a year to consider and forward IBIS model user concerns.  As a result
of

regular East coast meetings, the group has developed an IBIS Accuracy

Specification document and has helped move forward work on formatting
Connector Models.

These topics plus others of current interest to the EIA IBIS Open Forum

will be discussed at this meeting.


This meeting will be conducted as a formal IBIS Summit meeting. 
Presentations

are expected to be available and archived in an electronic format, and
minutes

of the meeting will be issued.  Any pending formal decisions (votes) will
be

announced at least two weeks prior to the meeting.


If you are interested in attending, please send e-mail to

Kathy Breda (breda@nesa.com)

  


<bold>AGENDA 

</bold>

Morning Sessions Focused on Round-Table, Open Discussions:


   Intro and Business         Bob Ross / Ed Sayre

  

   Accuracy Specification     Lead by Bob Haller

 

   <bold>Break

</bold> 

   Connector Specification    Discussion leader TBD  

  

   SPICE to IBIS Discussion   Discussion leader TBD  


   <bold>Lunch

</bold>

Afternoon Sessions Focused on Presentation Topics:

 

    Round Table Discussion: Input Modeling Discussion,  Discussion leader
TBD


    "Model Design: Tables and Equations" - Lynne Green, Hyperlynx   

<bold>

   Break (Sponsored by Praegitzer Design)

</bold>

    "Model Extraction Based on Differential TDR" - Dima Smolyansky or
Steven Cory, TDA Systems




  <bold>We have time for one more presentation!  Contact 

  Kathy Breda (breda@nesa.com) if you are interested

</bold> 

    

Format of Presentation:  Overhead Projections

Time:                    15-30 Minutes

Electronic Archival:     We request electronic versions so that the

                         presentations can be archived and also made

                         available to non-attendees.  Formats used in

                         the past have been text, Power Point, Word, 

                         Postscript, and Acrobat.  Electronic
presentations

                         should be made available by October 8, 1999.

                         Otherwise the presenters will be expected to
provide

                         50 copies for distribution.



****************************************************************************

<bold>DIRECTIONS TO MEETING

</bold>

The Marlboro Holiday Inn

is located at the junction of Route 20 and I-495

(exit 24A off I-495 North or South)

Located 4 miles from the Massachusetts Turnpike and

One Mile from I-290.  Thirty miles from Boston and

Logan International Airport


****************************************************************************


<bold>LIST OF NEARBY HOTELS

</bold>

Marlboro Holiday Inn

265 Lakeside Ave. 

Marlboro, MA

Tel:  (508)481-3000


Boxboro Holiday Inn.  

One Adams Place

Boxboro, MA

Tel:  (978) 263-8701

Fax:  (978) 263-0518


Royal Plaza Hotel 

181 Boston Post road West

Marlborough, MA 01752

Tel:  (508) 460-0700


Radisson Inn

75 Felton St.

Marlboro, MA

Tel:  (508) 480-0015


Embassy Suites Hotels

123 Boston Post Rd.

West Marlboro, MA

(508) 485-5900


Amerscot House

61 West Acton Road

Stow, MA  01775

email: doreen@amerscot.com, web site http://www.amerscot.com

Tel: (508)897-0666, FAX (508)897-6914


Westford Regency Inn

219 Littleton Rd. (exit 32 off I-495)

Westford, MA

Tel:  (978) 692-8200



+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |

|      -------------------------------------      |

|     "High Performance Engineering & Design"     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

| Kathy Breda             e-mail: breda@nesa.com  |

| NESA, Inc.              http://www.nesa.com/    |

| 636 Great Road          Tel +1.978.897-8787     |

| Stow, MA 01775 USA      Fax +1.978.897-5359     |

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
From owner-ibis  Fri Sep 24 13:22:03 1999
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X-Mailer: exmh version 2.0delta 6/3/97
To: Aubrey_Sparkman@dell.com, ibis-users@eda.org, ibis@eda.org
Subject: Re: package and connector model questions 
In-reply-to: Your message of "Thu, 23 Sep 1999 20:45:00 PDT."
             <199909240714.CAA07001@rgate.ricochet.net> 
Mime-Version: 1.0
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Date: Fri, 24 Sep 1999 13:21:52 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>



Hello Kellie, Aurbey, all:

> At 03:59 PM 9/23/99 -0500, Aubrey_Sparkman@Dell.com wrote:
> >The first question has to do with Kellee's outstanding item below.  I.E.,
> >why not use the RLC matrix description in section 7 on package modeling?  I
> >am not sure why Connector modeling isn't (or couldn't be) a subset of the
> >package modeling spec.  After all, a package is a connector that connects
> >the silicon to a PCB....or socket, which is again another connector.  And
> >before someone comments "un-mated connector" I also wonder why I need the
> >model for an unmated connector or a package out of the socket, etc.
> 

  As one of the authors of the .pkg extensions, I'd like to add a comment. It is tempting to think of an IC package as 'just another type of connector', but in reality an IC package is much closer to a circuit board than a connector.  In fact, for many of the high performance products I've seen, the package IS a circuit board, complete with edge fingers or pins to connect it to a mother board.  The problem is that when trying to create an electrical description of this type of package you're not dealing with a group of parallel pins of equal length.  You've got *traces* that have different lengths, diverge, switch layers, who knows what else. To model the coupling requires having many small matrixes that are named or somehow interrelated.  After we played with it for a while we realized that 1) Even if we could agree on a description no one is going to create such a data base by hand and 2) it's a problem the CAE companies have already solved by integrating PCB extraction with!
!
 their SI tools.  Thus, we settled on what we could achieve -- a simpler uncoupled description.

  As Kellie mentioned, I do expect that some of the extensions the connector group has come up with will find there way into the .pkg section.  But I suspect other approach will be needed before IBIS will support full coupled
package models.

   Regards,
   Stephen Peters
   Intel Corp.


From owner-ibis  Fri Sep 24 15:51:36 1999
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Date: Fri, 24 Sep 1999 15:50:57 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: parser chk for sweep range
To: ibis-users@eda.org
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Hi,

I recently got a model and it passed the ibischk3.2.2 parser even though the
model did not use the IBIS specified voltage sweep ranges.

Is this correct ?

Regards,
Syed
Cisco Systems, Inc

From owner-ibis  Fri Sep 24 17:46:57 1999
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syed:

The parser does not check for the specified voltage ranges.

Bob Ross
Mentor Graphics



Syed Huq wrote:
> 
> Hi,
> 
> I recently got a model and it passed the ibischk3.2.2 parser even though the
> model did not use the IBIS specified voltage sweep ranges.
> 
> Is this correct ?
> 
> Regards,
> Syed
> Cisco Systems, Inc
From owner-ibis  Sun Sep 26 12:52:26 1999
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From: "wamiq ahmed" <wamiq_m_ahmed@hotmail.com>
To: ibis-users@eda.org
Subject: simulation of mc13176, mc2833 and mc3356
Date: Sun, 26 Sep 1999 12:51:48 PDT
Mime-Version: 1.0
Content-Type: text/plain; format=flowed

I am an ee senior student working on my ee senior project. I need some 
software tool for the simulations of the mc 13176, mc2833 and mc3356 ic's. I 
would be pleased and highly obliged if some one could help me regarding 
that.

______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com
From owner-ibis  Wed Sep 29 07:48:32 1999
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Organization: ST Microelectronics
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Subject: Mos Drain-Bulk Junction current 
Content-Type: text/plain; charset=us-ascii
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Hello,

I would like to ask you in which way it is possible to obtain the  V/I  IBIS
curve trough Hspice simulation.


My supply voltage is 3.3V and my output buffer is a standard C-MOS.
Considering the pull-down element, I force on the buffer output  -6.6 V in order
to obtain the first point of my IV curve.
Thus I turn on  the N-Mos Drain-Bulk juncition and the current value is like
1e20 A.
I have to use a resistor in order to limit this current .

I would like to know  what is the resistor to use  (Rref, R_pck ,  ..) and if I
have to add other elements like Cref  Rref  Vref, Rload, Cload .....


Thank you in advance for your answer ,      Your Sincerelly


Riccardo Giordani

                                                                         e-mail:
riccardo.giordani@st.com

From owner-ibis  Wed Sep 29 07:47:01 1999
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Organization: ST Microelectronics
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CC: riccardo.giordani@st.com
Subject: Mos Drain-Bulk Junction current 
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello,

I would like to ask you in which way it is possible to obtain the  V/I  IBIS
curve trough Hspice simulation.


My supply voltage is 3.3V and my output buffer is a standard C-MOS.
Considering the pull-down element, I force on the buffer output  -6.6 V in order
to obtain the first point of my IV curve.
Thus I turn on  the N-Mos Drain-Bulk juncition and the current value is like
1e20 A.
I have to use a resistor in order to limit this current .

I would like to know  what is the resistor to use  (Rref, R_pck ,  ..) and if I
have to add other elements like Cref  Rref  Vref, Rload, Cload .....


Thank you in advance for your answer ,      Your Sincerelly


Riccardo Giordani

                                                                         e-mail:
riccardo.giordani@st.com

