From owner-ibis  Tue Mar 31 17:50:59 1998
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Hello,

  Do you have the IBIS models of  Rambus-based chips below:
   1)2D/3D graphics accelerator chip,for example,CL-GD5465.
   2)RDRAM

  Model of any chips in this library is okay, for I just use it for an
experiment.

  Thank you !

Lisa

From owner-ibis  Tue Mar 31 21:54:08 1998
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From owner-ibis  Wed Apr  1 01:19:48 1998
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Date: Wed, 1 Apr 1998 18:15:59 +0900 (JST)
Message-Id: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
From: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
To: crokusek@qdt.com
Cc: ibis-users@vhdl.org
Subject: [Re: About WARNING of ibischk2]


Chris,
  thank you very much for your quick response and answer.

  I would like to confirm my issue.

  # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
   + [Gndclamp] ?
 

      (I)
          |                             *  [Pulldown] + [GNDclamp]
    0.6A  x                    ****
          |  x            **
          |     x     *
          |        * 
          |     *  ^  x
          |   *    |     x           slope = 50 Ohm
          | *      |        x
          *--------|-----------x---------
        0.0V       |        3.0 V     (V)
                (0.95V)
                 #####

 - Regards,
    A.Takegma 
>     ************************************
>     *   Name   : Akihiro Takegama      *
>     *   E-mail : tkgm@tdc.tijp.ti.com  *
>     *   Corp.  : Texas Instruments     *
>     ************************************

-----------------------------------------------------------------------
------- Start of forwarded message -------
Sender: crokusek@qdt.com
Date: Tue, 31 Mar 1998 10:01:46 -0800
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: About WARNING of ibischk2
References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
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Akihiro,

The ibishk2 program is checking the first and last point of your Rising
and Falling AC Waveforms against the DC VI curves and given test load
(50 Ohms).

For your case the message indicates that the first point given in the
Rising Waveform table is .74V.  

If you were to plot the intersection of a 50 Ohm to 3V load line (slope
= 50 V/I) and the given DC VI curve you would see that they interesect
at .95V (this is fist value in [3] below).

So since 

     abs(.95 - .74) > 2% * (3 - .74)
               .21  > .045

The checker will print a warning.

The reason for the check is that the first and last points of the AC
waveforms are supposed to be the stable DC value when driving the given
load.

Chris Rokusek
Viewlogic


Akihiro Takegama wrote:
> 
> To: IBIS-users,
> 
>   Hello, I'm making the IBIS model. But I am confused at ibischk.
>  Could you support me ?
> 
>   I have one question.
> 
>   1 ) I made the IBIS model within "Rising Waveform" and "Falling
>      Waveform" and I ran the ibischk2. But many warning appeares
>      it's IBIS model, which like as below.
>       Could you please tell me how to calculate the value [3]. ?
> 
> - ----------------------------------------------------------------------------
> WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
>                                                    -------------
>                                                         [1]
> 
>           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
>           -----------    ----------------
>              [2]               [3]
> - -----------------------------------------------------------------------------
> 
>  - Regards,
>     A.Takegama
> 
>     ************************************
>     *   Name   : Akihiro Takegama      *
>     *   E-mail : tkgm@tdc.tijp.ti.com  *
>     *   Corp.  : Texas Instruments     *
>     ************************************
> ------- End of forwarded message -------
------- End of forwarded message -------
From owner-ibis  Wed Apr  1 03:12:23 1998
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From: Justin Yu <JustinYu@via.com.tw>
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=====================================
Have a great day...             
Justin Yu at VIA Tech. 
Justinyu@via.com.tw     http://www.via.com.tw
=====================================


From owner-ibis  Wed Apr  1 05:34:49 1998
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Regards - Marc Faucher
STSM, x86 Business Unit                  TIE: 446-6704 TEL:802-769-6704, FAX:
x6800
Internet: faucher@us.ibm.com      Notes: Marc Faucher/Burlington/IBM@IBMUS
From owner-ibis  Wed Apr  1 05:46:16 1998
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--
unsubscribe

From owner-ibis  Wed Apr  1 09:35:43 1998
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Date: Wed, 01 Apr 1998 09:21:51 -0800
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: [Re: About WARNING of ibischk2]
References: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
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Akihiro,

The "LOW" curve used in the DC vs. AC test is the sum of BOTH shunt
curves (POWER_Clamp/GND_Clamp) + the Pulldown Curve.

Similarly the "HIGH" curve used in the test is the sum of BOTH shunt
curves + Pullup Curve.

Chris



Akihiro Takegama wrote:
> 
> Chris,
>   thank you very much for your quick response and answer.
> 
>   I would like to confirm my issue.
> 
>   # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
>    + [Gndclamp] ?
> 
> 
>       (I)
>           |                             *  [Pulldown] + [GNDclamp]
>     0.6A  x                    ****
>           |  x            **
>           |     x     *
>           |        *
>           |     *  ^  x
>           |   *    |     x           slope = 50 Ohm
>           | *      |        x
>           *--------|-----------x---------
>         0.0V       |        3.0 V     (V)
>                 (0.95V)
>                  #####
> 
>  - Regards,
>     A.Takegma
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> 
> -----------------------------------------------------------------------
> ------- Start of forwarded message -------
> Sender: crokusek@qdt.com
> Date: Tue, 31 Mar 1998 10:01:46 -0800
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: About WARNING of ibischk2
> References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Akihiro,
> 
> The ibishk2 program is checking the first and last point of your Rising
> and Falling AC Waveforms against the DC VI curves and given test load
> (50 Ohms).
> 
> For your case the message indicates that the first point given in the
> Rising Waveform table is .74V.
> 
> If you were to plot the intersection of a 50 Ohm to 3V load line (slope
> = 50 V/I) and the given DC VI curve you would see that they interesect
> at .95V (this is fist value in [3] below).
> 
> So since
> 
>      abs(.95 - .74) > 2% * (3 - .74)
>                .21  > .045
> 
> The checker will print a warning.
> 
> The reason for the check is that the first and last points of the AC
> waveforms are supposed to be the stable DC value when driving the given
> load.
> 
> Chris Rokusek
> Viewlogic
> 
> Akihiro Takegama wrote:
> >
> > To: IBIS-users,
> >
> >   Hello, I'm making the IBIS model. But I am confused at ibischk.
> >  Could you support me ?
> >
> >   I have one question.
> >
> >   1 ) I made the IBIS model within "Rising Waveform" and "Falling
> >      Waveform" and I ran the ibischk2. But many warning appeares
> >      it's IBIS model, which like as below.
> >       Could you please tell me how to calculate the value [3]. ?
> >
> > - ----------------------------------------------------------------------------
> > WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
> >                                                    -------------
> >                                                         [1]
> >
> >           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
> >           -----------    ----------------
> >              [2]               [3]
> > - -----------------------------------------------------------------------------
> >
> >  - Regards,
> >     A.Takegama
> >
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> > ------- End of forwarded message -------
> ------- End of forwarded message -------
From owner-ibis  Wed Apr  1 17:41:25 1998
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Message-Id: <199804020137.KAA17286@mario.tdc.tijp.ti.com>
From: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
To: crokusek@qdt.com
Cc: ibis-users@vhdl.org
Subject: Thanks [Re: Re: [Re: About WARNING of ibischk2]]


 Chris,
  thank you very much for you kindness.
  I understand very well.

 - Regards,
    A.Takegama

    ************************************
    *   Name   : Akihiro Takegama      *
    *   E-mail : tkgm@tdc.tijp.ti.com  *
    *   Corp.  : Texas Instruments     *
    ************************************
-----------------------------------------------------------------------

------- Start of forwarded message -------
Sender: crokusek@qdt.com
Date: Wed, 01 Apr 1998 09:21:51 -0800
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
Mime-Version: 1.0
To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: [Re: About WARNING of ibischk2]
References: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Akihiro,

The "LOW" curve used in the DC vs. AC test is the sum of BOTH shunt
curves (POWER_Clamp/GND_Clamp) + the Pulldown Curve.

Similarly the "HIGH" curve used in the test is the sum of BOTH shunt
curves + Pullup Curve.

Chris



Akihiro Takegama wrote:
> 
> Chris,
>   thank you very much for your quick response and answer.
> 
>   I would like to confirm my issue.
> 
>   # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
>    + [Gndclamp] ?
> 
> 
>       (I)
>           |                             *  [Pulldown] + [GNDclamp]
>     0.6A  x                    ****
>           |  x            **
>           |     x     *
>           |        *
>           |     *  ^  x
>           |   *    |     x           slope = 50 Ohm
>           | *      |        x
>           *--------|-----------x---------
>         0.0V       |        3.0 V     (V)
>                 (0.95V)
>                  #####
> 
>  - Regards,
>     A.Takegma
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> 
> -----------------------------------------------------------------------
> ------- Start of forwarded message -------
> Sender: crokusek@qdt.com
> Date: Tue, 31 Mar 1998 10:01:46 -0800
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: About WARNING of ibischk2
> References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Akihiro,
> 
> The ibishk2 program is checking the first and last point of your Rising
> and Falling AC Waveforms against the DC VI curves and given test load
> (50 Ohms).
> 
> For your case the message indicates that the first point given in the
> Rising Waveform table is .74V.
> 
> If you were to plot the intersection of a 50 Ohm to 3V load line (slope
> = 50 V/I) and the given DC VI curve you would see that they interesect
> at .95V (this is fist value in [3] below).
> 
> So since
> 
>      abs(.95 - .74) > 2% * (3 - .74)
>                .21  > .045
> 
> The checker will print a warning.
> 
> The reason for the check is that the first and last points of the AC
> waveforms are supposed to be the stable DC value when driving the given
> load.
> 
> Chris Rokusek
> Viewlogic
> 
> Akihiro Takegama wrote:
> >
> > To: IBIS-users,
> >
> >   Hello, I'm making the IBIS model. But I am confused at ibischk.
> >  Could you support me ?
> >
> >   I have one question.
> >
> >   1 ) I made the IBIS model within "Rising Waveform" and "Falling
> >      Waveform" and I ran the ibischk2. But many warning appeares
> >      it's IBIS model, which like as below.
> >       Could you please tell me how to calculate the value [3]. ?
> >
> > - ----------------------------------------------------------------------------
> > WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
> >                                                    -------------
> >                                                         [1]
> >
> >           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
> >           -----------    ----------------
> >              [2]               [3]
> > - -----------------------------------------------------------------------------
> >
> >  - Regards,
> >     A.Takegama
> >
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> > ------- End of forwarded message -------
> ------- End of forwarded message -------
------- End of forwarded message -------
From owner-ibis  Thu Apr  2 02:39:33 1998
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From: "Jeno Varga (MEPCD)" <jenov@apricot.mee.com>
To: "'ibis-users@vhdl.org'" <ibis-users@vhdl.org>
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Date: Thu, 2 Apr 1998 10:04:30 +0100
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Dear Sirs,

My company (MEPCD - Mitsubishi Electric PC Division) recently bought the
Veribest CAD system. 
I am a design engineer of the R&D site at Birmingham, UK. I am just
started to learn this new signal analyzer tool from Veribest and the
IBIS modeling.
I have already find a few IBIS model of integrated circuit (like Intel
443BX chipset) for our new mother design. But I need some help to find
model files for some special non vendor specific components like the
empty PCI bus connector, any PCI bus card, AGP video card and connector,
empty DIMM socket. The new 100MHz local bus design is a very time and
tracing critical one and it's very difficult to measure signals on the
PCB so the simulation is vital for a reliable product. Could you help me
to find this model files please, if you can. Or give me some advice what
is the best way to create some accurate model for an empty connector
like the PCI one.

Regards,
Jeno Varga
Senior Design Engineer
Mitsubishi Electronic PC Division

Apricot R&D
2500 The Crescent Birmingham Business Park, 
Birmingham, B37 7YE UK
Tel.: [+44] 121 717-2521
Fax: [+44] 121 717-2600
e-mail: jenov@apricot.mee.com
http://www.mitsubishi-computers.com



From owner-ibis  Thu Apr  2 08:30:09 1998
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From: Ming Yin <bg21359@binghamton.edu>
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To: IBIS <ibis-users@vhdl.org>
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hi, IBIS fans

I have a question about the SPICE-IBIS utility s2ibis. 
In the IBIS COOKBOOK the author says that during extracting data for
[Ramp] keyword by simulations the C_comp is included in the circuit.
But in the *.spi files produced by s2ibis I can't see the C_comp.

Could you tell me why in s2ibis the C_comp is not used?

Thanks lot.

MingYin

From owner-ibis  Thu Apr  2 22:06:59 1998
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From owner-ibis  Fri Apr  3 06:03:45 1998
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Date: Fri, 3 Apr 1998 22:52:36 +0900 (JST)
From: Kai Koichiro <kai@askcs69.asic.lsi.nec.co.jp>
Message-Id: <199804031352.WAA04057@askcs69.asic.lsi.nec.co.jp>
To: ibis-users@vhdl.org
Subject: Question about new Warning from ibischk2+

Chris,

I'm sorry I have posted my question to wrong address,
and I thank you for your reply.

I understand the concept of the warning from ibischk2.
But now I have some questions.

1) the value in the expression

>      abs(.95 - .74) > 2% * (3 - .74)

   I think .95 means an ideal voltage of endpoint of the waveform.
   If it is true, is the right expression  2%*(3-.95) ?
                                                 ^^^
2) Where is "2 percent" from ?

3) Is the value of "2" rightful ?

Could you help me ?

K.Kai in NEC
  kai@lsi.nec.co.jp
From owner-ibis  Fri Apr  3 06:45:44 1998
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****************************************************************
John Horner				Phone: (919)481-6813	
Core Compentancy Group		Fax:   (919)469-9921
Cadence Design Systems		VoiceMail: (919)481-6813
113 Edinburgh South, Ste. 100	Email: horner@cadence.com
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****************************************************************
From owner-ibis  Fri Apr  3 08:55:23 1998
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Date: Fri, 03 Apr 1998 08:44:39 -0800
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To: Kai Koichiro <kai@askcs69.asic.lsi.nec.co.jp>
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Subject: Re: Question about new Warning from ibischk2+
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Kai,

Here are answers to your questions...

> I understand the concept of the warning from ibischk2.
> But now I have some questions.
> 
> 1) the value in the expression
> 
> >      abs(.95 - .74) > 2% * (3 - .74)
> 
>    I think .95 means an ideal voltage of endpoint of the waveform.
>    If it is true, is the right expression  2%*(3-.95) ?
>  

>> If you were to plot the intersection of a 50 Ohm to 3V load line (slope
>> = 50 V/I) and the given DC VI curve you would see that they interesect
>> at .95V (this is fist value in [3] below).
 
The .95 in the example is mathematically determined from the DC VI
curves in the model and the given load.  When this value differs from
the waveforms endpoints there is a discrepency in the data.  

Currently the checker takes the 2% times the Vac_high - Vac_low.  I
agree it might be better to trust the DC vi curves to get the range as
your suggested formula says and will suggest this change for next
release.  However, practically speaking, just thinking about the values
it really doesn't appear to matter which range (AC vs. DC) is used.

> 2) Where is "2 percent" from ?

The IBIS committee agreed that 2% of the range is a reasonable tolerance
for IBIS model builders to comply with.

The spec says something to the effect "The first and last AC waveform
point should be equal to the stable DC values"

2% just allows some tolerance to "equal"

 
> 3) Is the value of "2" rightful ?

I ran tests on all .ibs models and found that about 98% of model's
passed the test within 1% and they other 2% were off by more than 5%. 

You may need to lengthen the run time of the AC analysis so that the
output becomes stable.  If you have too many points, you may need to
carefully (in an interlaced fashion) remove some of the points toward
the end of simulation (not the last one).  

It would be a nice feature of the new visual ibis building tools to
allow visual editing of the waveforms as well as an automated
"redundant" point removal based on some linearization tolerance. 

See http://www.eia.org/EIG/IBIS/ibis.htm and hit tools for more info.

Chris Rokusek
Viewlogic Systems
From owner-ibis  Fri Apr  3 10:08:10 1998
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Mustafa Celik
Pacific Numerix 

From owner-ibis  Mon Apr  6 06:38:21 1998
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Date: Mon, 6 Apr 1998 22:34:39 +0900 (JST)
Message-Id: <199804061334.WAA20640@mario.tdc.tijp.ti.com>
From: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
To: crokusek@qdt.com
Cc: ibis-users@vhdl.org
Subject: About WARNING of ibischk2


  Chris,
    I'm sorry. I would like to cofirm my opinion, and I have one question.


   [1] Is slope of V(R) of <Fig 1> based on V(R) of <Fig 2>, isn't it ?

      <Fig 1>                                       <Fig 2>
                       [Pulldown] + [GNDclamp]               --- Vcc         --- 
       (I)                     or [POWERclamp]                ^               ^      
           |                             *  	              |   |           |      
     0.6A  x                    ****                          |   |           |        
           |  x            **                               |-+   | I         | V (Pch) 
           |     x     *                               +--o||     |           |        
           |        *                                  |    |-+   +------+    |        
           |     *  ^  x                             L |      |          |    V        
           |   *    |     x      slope = -50 Ohm     --+      +------+   |   ----     
           | *      |        x                         |      |      |   V    ^       
           *--------|-----------x---------             |    |-+      <        |      
         0.0V       |         3.3       (V)            +---||        < 50     | V (R) 
	                    (V_fixture)                     |-+      <  Ohm   |      
           |<------>|<--------->|		              |      |        V         
             V(Pch)     V (R) 	                             ---    ---      ---        
                                                             ///    ///      ///        


   [2] Could you tell me the reason why it is 2% ?
      Is this must value ?   
       ( You decided the value on Oct. in 1996. )
       If we decided the diode value, the value is lower the IV curve (leak).

      We have the IBIS check problem yet. The last warning disappeared by your
     cooperation.
      The max voltage value can't be up 2.81V. ( Below is in 3% margin )
  ----------------------------------------------------------------------------
  WARNING - Model 'inout': MAX AC Falling Endpoints (-0.00V,  2.73V) not within 
          0.055V (2%) of ( 0.00V,  2.81V) on VI curves for 50 Ohms to 0V
  ----------------------------------------------------------------------------

 - Regards,
    A.Takegama ( tkgm@tdc.tijp.ti.com )

    ************************************
    *   Name   : Akihiro Takegama      *
    *   E-mail : tkgm@tdc.tijp.ti.com  *
    *   Corp.  : Texas Instruments     *
    ************************************
- -----------------------------------------------------------------------

- ------- Start of forwarded message -------
Sender: crokusek@qdt.com
Date: Wed, 01 Apr 1998 09:21:51 -0800
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: [Re: About WARNING of ibischk2]
References: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
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Akihiro,

The "LOW" curve used in the DC vs. AC test is the sum of BOTH shunt
curves (POWER_Clamp/GND_Clamp) + the Pulldown Curve.

Similarly the "HIGH" curve used in the test is the sum of BOTH shunt
curves + Pullup Curve.

Chris



Akihiro Takegama wrote:
> 
> Chris,
>   thank you very much for your quick response and answer.
> 
>   I would like to confirm my issue.
> 
>   # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
>    + [Gndclamp] ?
> 
> 
>       (I)
>           |                             *  [Pulldown] + [GNDclamp]
>     0.6A  x                    ****
>           |  x            **
>           |     x     *
>           |        *
>           |     *  ^  x
>           |   *    |     x           slope = 50 Ohm
>           | *      |        x
>           *--------|-----------x---------
>         0.0V       |        3.0 V     (V)
>                 (0.95V)
>                  #####                                               
> 
>  - Regards,
>     A.Takegma
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> 
> -----------------------------------------------------------------------
> ------- Start of forwarded message -------
> Sender: crokusek@qdt.com
> Date: Tue, 31 Mar 1998 10:01:46 -0800
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: About WARNING of ibischk2
> References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Akihiro,
> 
> The ibishk2 program is checking the first and last point of your Rising
> and Falling AC Waveforms against the DC VI curves and given test load
> (50 Ohms).
> 
> For your case the message indicates that the first point given in the
> Rising Waveform table is .74V.
> 
> If you were to plot the intersection of a 50 Ohm to 3V load line (slope
> = 50 V/I) and the given DC VI curve you would see that they interesect
> at .95V (this is fist value in [3] below).
> 
> So since
> 
>      abs(.95 - .74) > 2% * (3 - .74)
>                .21  > .045
> 
> The checker will print a warning.
> 
> The reason for the check is that the first and last points of the AC
> waveforms are supposed to be the stable DC value when driving the given
> load.
> 
> Chris Rokusek
> Viewlogic
> 
> Akihiro Takegama wrote:
> >
> > To: IBIS-users,
> >
> >   Hello, I'm making the IBIS model. But I am confused at ibischk.
> >  Could you support me ?
> >
> >   I have one question.
> >
> >   1 ) I made the IBIS model within "Rising Waveform" and "Falling
> >      Waveform" and I ran the ibischk2. But many warning appeares
> >      it's IBIS model, which like as below.
> >       Could you please tell me how to calculate the value [3]. ?
> >
> > - ----------------------------------------------------------------------------
> > WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
> >                                                    -------------
> >                                                         [1]
> >
> >           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
> >           -----------    ----------------
> >              [2]               [3]
> > - -----------------------------------------------------------------------------
> >
> >  - Regards,
> >     A.Takegama
> >
> >     ************************************
> >     *   Name   : Akihiro Takegama      *
> >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> >     *   Corp.  : Texas Instruments     *
> >     ************************************
> > ------- End of forwarded message -------
From owner-ibis  Mon Apr  6 08:50:44 1998
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Hi,

I would like to generate IBIS models from the Spectre software.
Is this really possible through s2ibis2?
Anyone who is familiar with s2ibis2 please give me some advice.

Thank you,

Best regards,

Olivier Clere.
From owner-ibis  Mon Apr  6 10:30:24 1998
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804061729.KAA10835@rockie>
To: crokusek@qdt.com, tkgm@mario.tdc.tijp.ti.com
Subject: Re: About WARNING of ibischk2
Cc: ibis-users@vhdl.org

Hi,

I have been following this discussion regarding the parser WARNING
messages for V/T tables and have one comment.

>From a bench measured IBIS model, the DC V/I data is taken on
a testjig that is always different from the AC testjig. Also,
as expected, the DC and AC measurements are taken on different
equipments(DC on Curve Tracer, AC on Scope).

Knowing all these, the 2% WARNING on the parser does not make
much sense for V/T tables generated from measurements. Which 
means you may be violating this 2% rule all the time.

This check of the parser is ok for a SPICE translated model as the
same model was used for the V/I and V/T data.

What I would like to know is since this is a WARNING and not an
ERROR, how concerned does the model developer need to be ??

Regards,
Syed
National Semiconductor Corp. 
From owner-ibis  Mon Apr  6 11:05:48 1998
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Date: Mon, 06 Apr 1998 10:56:28 -0700
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: About WARNING of ibischk2
References: <199804061334.WAA20640@mario.tdc.tijp.ti.com>
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Akihiro,

I'm not sure I understand your question exactly.

The slope of the load line designated by "x"'s in your diagram is just
the load resistance 50 Ohms (= 50 Volts/Amp).  Its actually -50 due to
the current polarity.

The load-line represents the load resistor while the V/I curve
designated by "*" in your diagram represents the DC characteristics of
the totem pole output stage while driving low (top transistor off) shown
in Fig 2.

Hope this answers your question.

Chris


Akihiro Takegama wrote:
> 
>   Chris,
>     I'm sorry. I would like to cofirm my opinion, and I have one question.
> 
>    [1] Is slope of V(R) of <Fig 1> based on V(R) of <Fig 2>, isn't it ?
> 
>       <Fig 1>                                       <Fig 2>
>                        [Pulldown] + [GNDclamp]               --- Vcc         ---
>        (I)                     or [POWERclamp]                ^               ^
>            |                             *                    |   |           |
>      0.6A  x                    ****                          |   |           |
>            |  x            **                               |-+   | I         | V (Pch)
>            |     x     *                               +--o||     |           |
>            |        *                                  |    |-+   +------+    |
>            |     *  ^  x                             L |      |          |    V
>            |   *    |     x      slope = -50 Ohm     --+      +------+   |   ----
>            | *      |        x                         |      |      |   V    ^
>            *--------|-----------x---------             |    |-+      <        |
>          0.0V       |         3.3       (V)            +---||        < 50     | V (R)
>                             (V_fixture)                     |-+      <  Ohm   |
>            |<------>|<--------->|                             |      |        V
>              V(Pch)     V (R)                                ---    ---      ---
>                                                              ///    ///      ///
> 
>    [2] Could you tell me the reason why it is 2% ?
>       Is this must value ?
>        ( You decided the value on Oct. in 1996. )
>        If we decided the diode value, the value is lower the IV curve (leak).
> 
>       We have the IBIS check problem yet. The last warning disappeared by your
>      cooperation.
>       The max voltage value can't be up 2.81V. ( Below is in 3% margin )
>   ----------------------------------------------------------------------------
>   WARNING - Model 'inout': MAX AC Falling Endpoints (-0.00V,  2.73V) not within
>           0.055V (2%) of ( 0.00V,  2.81V) on VI curves for 50 Ohms to 0V
>   ----------------------------------------------------------------------------
> 
>  - Regards,
>     A.Takegama ( tkgm@tdc.tijp.ti.com )
> 
>     ************************************
>     *   Name   : Akihiro Takegama      *
>     *   E-mail : tkgm@tdc.tijp.ti.com  *
>     *   Corp.  : Texas Instruments     *
>     ************************************
> - -----------------------------------------------------------------------
> 
> - ------- Start of forwarded message -------
> Sender: crokusek@qdt.com
> Date: Wed, 01 Apr 1998 09:21:51 -0800
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: [Re: About WARNING of ibischk2]
> References: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Akihiro,
> 
> The "LOW" curve used in the DC vs. AC test is the sum of BOTH shunt
> curves (POWER_Clamp/GND_Clamp) + the Pulldown Curve.
> 
> Similarly the "HIGH" curve used in the test is the sum of BOTH shunt
> curves + Pullup Curve.
> 
> Chris
> 
> Akihiro Takegama wrote:
> >
> > Chris,
> >   thank you very much for your quick response and answer.
> >
> >   I would like to confirm my issue.
> >
> >   # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
> >    + [Gndclamp] ?
> >
> >
> >       (I)
> >           |                             *  [Pulldown] + [GNDclamp]
> >     0.6A  x                    ****
> >           |  x            **
> >           |     x     *
> >           |        *
> >           |     *  ^  x
> >           |   *    |     x           slope = 50 Ohm
> >           | *      |        x
> >           *--------|-----------x---------
> >         0.0V       |        3.0 V     (V)
> >                 (0.95V)
> >                  #####
> >
> >  - Regards,
> >     A.Takegma
> > >     ************************************
> > >     *   Name   : Akihiro Takegama      *
> > >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> > >     *   Corp.  : Texas Instruments     *
> > >     ************************************
> >
> > -----------------------------------------------------------------------
> > ------- Start of forwarded message -------
> > Sender: crokusek@qdt.com
> > Date: Tue, 31 Mar 1998 10:01:46 -0800
> > From: Chris Rokusek <crokusek@qdt.com>
> > Organization: Quad Design Technology
> > X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> > Mime-Version: 1.0
> > To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> > Cc: ibis-users@vhdl.org
> > Subject: Re: About WARNING of ibischk2
> > References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
> > Content-Type: text/plain; charset=us-ascii
> > Content-Transfer-Encoding: 7bit
> >
> > Akihiro,
> >
> > The ibishk2 program is checking the first and last point of your Rising
> > and Falling AC Waveforms against the DC VI curves and given test load
> > (50 Ohms).
> >
> > For your case the message indicates that the first point given in the
> > Rising Waveform table is .74V.
> >
> > If you were to plot the intersection of a 50 Ohm to 3V load line (slope
> > = 50 V/I) and the given DC VI curve you would see that they interesect
> > at .95V (this is fist value in [3] below).
> >
> > So since
> >
> >      abs(.95 - .74) > 2% * (3 - .74)
> >                .21  > .045
> >
> > The checker will print a warning.
> >
> > The reason for the check is that the first and last points of the AC
> > waveforms are supposed to be the stable DC value when driving the given
> > load.
> >
> > Chris Rokusek
> > Viewlogic
> >
> > Akihiro Takegama wrote:
> > >
> > > To: IBIS-users,
> > >
> > >   Hello, I'm making the IBIS model. But I am confused at ibischk.
> > >  Could you support me ?
> > >
> > >   I have one question.
> > >
> > >   1 ) I made the IBIS model within "Rising Waveform" and "Falling
> > >      Waveform" and I ran the ibischk2. But many warning appeares
> > >      it's IBIS model, which like as below.
> > >       Could you please tell me how to calculate the value [3]. ?
> > >
> > > - ----------------------------------------------------------------------------
> > > WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
> > >                                                    -------------
> > >                                                         [1]
> > >
> > >           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
> > >           -----------    ----------------
> > >              [2]               [3]
> > > - -----------------------------------------------------------------------------
> > >
> > >  - Regards,
> > >     A.Takegama
> > >
> > >     ************************************
> > >     *   Name   : Akihiro Takegama      *
> > >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> > >     *   Corp.  : Texas Instruments     *
> > >     ************************************
> > > ------- End of forwarded message -------
From owner-ibis  Mon Apr  6 11:32:00 1998
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Date: Mon, 6 Apr 1998 11:30:50 -0700
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804061830.LAA11072@rockie>
To: ibis-users@eda.org, Olivier.Clere@cern.ch
Subject: Re: IBIS models generation from Spectre - Yes.

Hi,

Yes, s2ibis2 supports Spectre. I am quoting from the s2ibis2
documentation. In the .s2i header file, use 'Spectre' for
[Spice type]

..from s2ibis2 documentation:
-----------------------------
  [Spice type]    spicetype

        spicetype = HSpice, PSpice, Spice2, Spice3, or Spectre

        Required.
        
        Describes which flavor of Spice to use when simulating the
        circuits.
------------------------------------------------------------------
Regards,
Syed.
National Semiconductor Corp.

> From owner-ibis@server.vhdl.org Mon Apr  6 09:57:33 1998
> X-Authentication-Warning: listbox2.cern.ch: Host pccnce02.cern.ch [137.138.33.35] claimed to be cern.ch
> Date: Mon, 06 Apr 1998 17:47:08 +0200
> From: Olivier CLERE <Olivier.Clere@cern.ch>
> Organization: CERN
> X-Mailer: Mozilla 4.04 [en] (Win95; I)
> To: ibis-users@eda.org
> Subject: IBIS models generation from Spectre
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
> 
> Hi,
> 
> I would like to generate IBIS models from the Spectre software.
> Is this really possible through s2ibis2?
> Anyone who is familiar with s2ibis2 please give me some advice.
> 
> Thank you,
> 
> Best regards,
> 
> Olivier Clere.
> 
From owner-ibis  Mon Apr  6 11:35:21 1998
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From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Syed Huq <huq@rockie.nsc.com>
Cc: ibis-users@vhdl.org
Subject: Re: About WARNING of ibischk2
References: <199804061729.KAA10835@rockie>
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Hi,

Perhaps the ability to set the % used in the check should be allowed.  I
recall that we discussed this before...

Or, perhaps the 2% should be increased to 5%.  What percentage would
allow these measured models to pass with some headroom? 

Chris
From owner-ibis  Mon Apr  6 11:45:51 1998
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Date: Mon, 06 Apr 1998 11:42:17 +0000
To: huq@rockie.nsc.com (Syed Huq), crokusek@qdt.com
From: Matthew Flora <mbflora@hyperlynx.com>
Subject: Re: About WARNING of ibischk2
Cc: ibis-users@vhdl.org
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Syed,

>>From a bench measured IBIS model, the DC V/I data is taken on
>a testjig that is always different from the AC testjig. Also,
>as expected, the DC and AC measurements are taken on different
>equipments(DC on Curve Tracer, AC on Scope).
>
>Knowing all these, the 2% WARNING on the parser does not make
>much sense for V/T tables generated from measurements. Which 
>means you may be violating this 2% rule all the time.
>
>What I would like to know is since this is a WARNING and not an
>ERROR, how concerned does the model developer need to be ??

Would changing the warning message around so that it gave the percentage
difference help?  (Currently, it just says that the difference is more
than 2%.)  Then the user could easily decide if the amount of mismatch is
acceptable.  In this way, someone that expects or is comfortable with a 5%
(or more) difference could ignore the warning.  (The program could still use
2% as the trigger for the warning.)

We could even expand the message beyond 2 lines of text to include a
description of how these numbers are generated.  I admit that many of
IBISCHK's messages are a bit too terse.

Regards,
Matthew Flora
Senior Engineer
HyperLynx
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
From owner-ibis  Mon Apr  6 11:51:28 1998
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Date: Mon, 06 Apr 1998 11:38:47 -0700
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
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To: Syed Huq <huq@rockie.nsc.com>
Cc: ibis-users@vhdl.org
Subject: Re: About WARNING of ibischk2
References: <199804061729.KAA10835@rockie>
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Syed,

Syed Huq wrote:
> What I would like to know is since this is a WARNING and not an
> ERROR, how concerned does the model developer need to be ??

When the warning is issued the model developer should determine the
cause of the warning as you have done (i.e. small discrepency due to
measurement technique) and then move on.  This is just a warning.

EDA tools: 

Viewlogic/Quad tools will use the VI curves as the basis for simulation
with the V/T waveforms as additional information so it turns out that a
small errors like 5% on waveform endpoints will **potentially** only
change simulation results on the order of uVolts (or not at all!) (DC
stable states remain same regardless of V/T waveforms).  I think most
EDA tools will operate in a similar manner.

The point of the warning is to let model developer know that something
major may be wrong like:

    They used a TYP VI curve with a MAX VT waveform
    They forgot to include a high curve!!
    They forgot to include a low curve!!
    They used a different load resistor than specified.
    The AC waveform wasn't done stabilizing at end of simulation.
    ...etc...

Any of the above would cause significant error so want to avoid.

Chris Rokusek
Viewlogic.
From owner-ibis  Mon Apr  6 14:05:42 1998
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From: Paul Gregory <pgregory@hpbs2933.boi.hp.com>
Message-Id: <199804062102.PAA01961@hpbs2933.boi.hp.com>
Subject: Re: About WARNING of ibischk2
To: ibis-users@vhdl.org
Date: Mon, 06 Apr 1998 15:02:37 MDT
Reply-to: paul_gregory@hp.com
X-Mailer: Elm [revision: 212.4]

>What I would like to know is since this is a WARNING and not an
>ERROR, how concerned does the model developer need to be ??

>Regards,
>Syed
>National Semiconductor Corp. 

I think that the concern is more with the model consumer, not
the developer.  Any time I get a model that does not pass the
ibischk utility, my confidence in the model goes down.  I 
usually notify the model supplier that the model had some
warnings and ask for clarification as to why it does not 
pass.  Then I spend time examining the model in closer detail 
to try to understand the warnings/errors. While this is a good 
thing from the point of view that I become more knowledgeable about
the model, it is not a desired thing.  I need to have confidence 
that the models are accurate, and passing the ibischk utility
is the first step.

 -- Paul Gregory

   phone: (208) 396-5086               USmail: Hewlett-Packard
     fax: (208) 396-4122                       M/S 143
   email: paul_gregory@hp.com                  11311 Chinden Blvd.
                                               Boise, ID  83714
From owner-ibis  Mon Apr  6 14:39:25 1998
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804062138.OAA11674@rockie>
To: huq@rockie.nsc.com, crokusek@qdt.com
Subject: Re: About WARNING of ibischk2
Cc: ibis-users@vhdl.org

Chris/Matthew:

Thanks for your comments. I would like to know the exact % delta between
the V/I and V/T and not just 'not within 2%'. This will really tell me
if I should be alarmed..Also, it would be nice to know
if a certain greater than 'x'% deviation can cause problems with simulators.

If a 5% difference causes uVolt variation on simulation, then this
WARNING is never a serious thing and it can always be ignored.

Regards,
Syed.
National Semiconductor Corp.

> From peterbilt!qdt.com!crokusek@uunet.uu.net Mon Apr  6 11:34:43 1998
> Sender: crokusek@qdt.com
> Date: Mon, 06 Apr 1998 11:25:37 -0700
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> To: Syed Huq <huq@rockie.nsc.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: About WARNING of ibischk2
> Content-Type> : > text/plain> ; > charset=us-ascii> 
> Content-Transfer-Encoding: 7bit
> 
> Hi,
> 
> Perhaps the ability to set the % used in the check should be allowed.  I
> recall that we discussed this before...
> 
> Or, perhaps the 2% should be increased to 5%.  What percentage would
> allow these measured models to pass with some headroom? 
> 
> Chris
> 
From owner-ibis  Mon Apr  6 15:30:04 1998
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From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <199804062229.PAA11839@rockie>
To: ibis-users@vhdl.org, paul_gregory@hp.com
Subject: Re: About WARNING of ibischk2

Paul,

A model can pass the parser and still get WARNINGS. That does
not mean that the model is **Bad**. We have devices whose V/I
characterisitcs are non-monotonic. So, the parser will ALWAYS
give you WARNINGS. I do agree that understanding the WARNINGS
is a good thing to do.

..and if the model never passes the parser...throw it away.

Regards,
Syed
National Semiconductor Corp.


> From owner-ibis@server.vhdl.org Mon Apr  6 15:05:50 1998
> From: Paul Gregory <pgregory@hpbs2933.boi.hp.com>
> Subject: Re: About WARNING of ibischk2
> To: ibis-users@vhdl.org
> Date: Mon, 06 Apr 1998 15:02:37 MDT
> Reply-to: paul_gregory@hp.com
> X-Mailer: Elm [revision: 212.4]
> 
> >What I would like to know is since this is a WARNING and not an
> >ERROR, how concerned does the model developer need to be ??
> 
> >Regards,
> >Syed
> >National Semiconductor Corp. 
> 
> I think that the concern is more with the model consumer, not
> the developer.  Any time I get a model that does not pass the
> ibischk utility, my confidence in the model goes down.  I 
> usually notify the model supplier that the model had some
> warnings and ask for clarification as to why it does not 
> pass.  Then I spend time examining the model in closer detail 
> to try to understand the warnings/errors. While this is a good 
> thing from the point of view that I become more knowledgeable about
> the model, it is not a desired thing.  I need to have confidence 
> that the models are accurate, and passing the ibischk utility
> is the first step.
> 
>  -- Paul Gregory
> 
>    phone: (208) 396-5086               USmail: Hewlett-Packard
>      fax: (208) 396-4122                       M/S 143
>    email: paul_gregory@hp.com                  11311 Chinden Blvd.
>                                                Boise, ID  83714
> 
From owner-ibis  Mon Apr  6 16:36:05 1998
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From: Paul Gregory <pgregory@hpbs2933.boi.hp.com>
Message-Id: <199804062332.RAA02594@hpbs2933.boi.hp.com>
Subject: Re: About WARNING of ibischk2
To: huq@rockie.nsc.com
Date: Mon, 06 Apr 1998 17:32:57 MDT
Cc: ibis-users@vhdl.org
In-Reply-To: <H00001470e21ac19@MHS>; from "huq@rockie.nsc.com" at Apr 6, 98 4:27 pm
Reply-to: paul_gregory@hp.com
X-Mailer: Elm [revision: 212.4]

>A model can pass the parser and still get WARNINGS. That does
>not mean that the model is **Bad**. We have devices whose V/I
>characterisitcs are non-monotonic. So, the parser will ALWAYS
>give you WARNINGS. I do agree that understanding the WARNINGS
>is a good thing to do.
>
>..and if the model never passes the parser...throw it away.
>
>Regards,
>Syed
>National Semiconductor Corp.


I never suggested that a model that has warnings/errors is
bad. Only that such models require more study to understand
the reasons for the warnings/errors.  And this is, in my
opinion, "not a desired thing".  It is at worst, an issue of
model accuracy and at best, an issue of model confidence.

 -- Paul Gregory

   phone: (208) 396-5086               USmail: Hewlett-Packard
     fax: (208) 396-4122                       M/S 143
   email: paul_gregory@hp.com                  11311 Chinden Blvd.
                                               Boise, ID  83714
From owner-ibis  Wed Apr  8 11:10:25 1998
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From: Kathy Breda <breda@nesa.com>
Subject: IBIS User Group minutes 3/19 - In future will only be sent to
  IBIS-user@eda.com.
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***Minutes of the IBIS Users Group Meeting
   held at DEC/Compaq on Thursday, March 19, 1998***


Thank you to Jeff Chu of DEC who coordinate the
meeting room and refreshments.  Also, thanks
to Bob Haller of DEC who chaired the meeting
in Ed Sayre's absence - a job well done!  

Next Meeting is Scheduled for Thursday, April 23, 1998
at 3:00PM.  The meeting will be hosted by Joe Socha
of TRILOGIC, Inc. in Wilmington, MA.  Directions and
Agenda to Follow.

Apologies for the late distribution of the minutes.

------------------------------------------
N.B.==>Distribution of IBIS Information<==
-----------------------------------------

To cut down the repeat messages and also e-mail sent to
uninterested parties, the IBIS business information will
be sent only to the IBIS-users@eda.com distribution list
after this point.

If you still want to receive IBIS minutes, but do not want
to subscribe to the ibis-users@eda.com list, please let me
know (breda@nesa.com)and I will create a special distribution list.

IBIS technical information, such as BIRDS may be sent
to a wider distribution list, including the SI distribution
list.  

To be added to the IBIS distribution list send mail to ibis-request@eda.org.
See directions for this and other interesting IBIS related addresses below.

  ibis-request@eda.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
       or both.  State your request.

   ibis-info@eda.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@eda.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@eda.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@eda.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

       To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
       which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
       /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
       respectively.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on eda.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.


IBIS Accuracy Sub-Committee Progress
------------------------------------

A proposal has been written for the IBIS Accuracy Specification.
Each member of the Accuracy sub-committee is assigned to one
part of the specification.  This was presented by Greg Edlund
and details from his presentation can be found below.  Please
send ideas to Greg (Greg.Edlund@digital.com) about the specification.

Scope:
	* Define which IBIS features and driver families to cover.
	* Define different levels of accuracy so the user can decide which
 	  is appropriate for his or her own application.

Test Loads:
	*  Define a minimum set of test loads appropriate for the IBIS
	   features and driver families covered.

Measurement Techniques:
	*  Provide selection criteria for test equipment.
	*  Describe how to account for the electrical characteristics  of
 	   the test environment.

Comparison Metrics:
	*  Define a curve overlay metric for use when IC processing 	   
	   conditions are known.
	*  Define an envelope metric for use when IC processing conditions 	   
	   are unknown.
	*  Define a tabular format for reporting the results of the above
	   comparisons.
	*  Write a C program which implements the above metrics and creates 	   
	   a summary table.

The IBIS model test board has been powered up and is in debug.  A board
respin will be taking place.  Once the IBIS Users' Web Page is ready the 
Gerber files and schematics will be posted.


Software Aspects of IBIS Sub-Committee Progress
-----------------------------------------------

Paul Galloway is leading this sub-committee and portions of his
presentation can be found below.

Need for an IBIS development kit: 
	*  It sounds like the recently announced Hyperlynx “IBIS
	   Development” Suite may cover this requirement.  See 2/26/98
	   e-mail message from breda@nesa.com regarding how to get 
	   the Hyperlynx Developer Tool Kit.

Need for enhanced s2ibis to correct issues with the existing s2ibis2: 
	*  Capture issues and problems with s2ibis2 and determine what
	   specific features of IBIS 3.0 should be added, basically develop
 	   a specification for the new s2ibis

	*  Proceed with soliciting funding by working with the IBIS Open 	  
	   Forum and solicit member organizations for development funds and
 	   researching available grants, etc. for development.
	
	*  Locate and schedule software development contractor for code
	   development of the new s2ibis utility

Action Item - Pursue funding through member organizations - Haruny Said
Action Item - Research potential availability of grants - Paul Galloway


Requirement for both a short (1 hour) "what is IBIS?" seminar:

	*  Material probably exists for this from several past IBIS
	   presentation we should leverage

Requirement for in depth course teaching IBIS model development(and usage?):
	*  Need to develop curriculum outline and materials

Action Item - Contact Ed Sayre to move forward on development

The European Summit
	*  It was an interesting forum where the hot topic seemed to be 
	   EMI in IBIS simulation. 
	*  <KB comment> I believe copies of the presentations can be found by
	   going to ftp://ftp.eda.org/pub/ibis/summits/
 

Fabrizio Zanella is heading up the effort that focuses on the usability 
of connector models.  The IBIS connector model discussion has taken place 
in the past and was shelved, but has become a pressing industry and user 
issue in the last one to two years. As a result, the sub-committee 
feels that IBIS should include a defined format for connectors in IBIS 3.1.

Highlights from Fabrizio's presentation follow:

Connector Models:

	*  The plan is to create a BIRD for the connector model - Fabrizio
	   was wondering if one existed already.
	*  Interconnect multiline models are created using EM tools that
	   output LRC matrices as SPICE sub circuits
	*  Last year connector vendors were not fully supporting IBIS.  
	   They did not want to recreate multi line models
	*  The solution is for the sub-committee to develop a standard
	   format for connector and package multi line matrix model that
	   can be used by all simulators (avoid convergence issues)
	*  Plan is for the BIRD to be created this year
	*  Fabrizio is looking for participation of connector vendors in this effort.

	
Other Business
--------------

User Web Page
-------------
An outline has been created for the User Web Page by Kathy Breda and web 
site construction is being handled by Andrew Philips.  

A copy of the web page outline was presented and seemed to get good feedback.
Comments are appreciated and should be sent to Kathy at breda@nesa.com.

(first page:)

Welcome to the IBIS User Forum Web Page...

   IBIS User Forum News - dates of next meetings...

IBIS User Forum Overview
IBIS User Meetings
Sub-Committee Activities
IBIS Tools
Useful IBIS related Links
On-line Chat

(and beyond first page:)

  |---->  IBIS User Forum Overview
                 - IBIS User Forum Mission
                 - IBIS User Forum Logistics (need better title)
                   --Who is involved (distribution list - maybe)
                   --meetings
                 --sub-committees and contacts
                   --current projects (link to IBIS User Meetings)

                 - What is IBIS
                   --Description of IBIS
                   --Contacts (i.e. Link to IBIS Forum page)
|----> IBIS User Meetings
                 - News Item, announcing next meeting detail for
                   user meeting and sub-committees
                 - Minutes & Agendas
                   -- User Forum
                        --- by date, meeting minutes, agenda for
                            upcoming meeting
                   -- Subcommittees
                        --- Subcommittee on accuracy
                            ---- by date, meeting minutes, agendas
                  --- Subcommittee on software aspects of IBIS
                      ---- by date, meeting minutes, agendas

                 - Presentations
                   -- Presentations from meetings (link back to meetings)
                        --- Abstract with PDF and ZIP availability?
                   -- Other Interesting presentations
                  --- Abstract with PDF and ZIP availability?
|----> Sub-committee Activities
                 - Sub-committee on accuracy
                   -- Members
                   -- link to minutes & Agendas
                   -- BIRDS
                   -- Test Board Design
                        --Test board schematics
                        --Test board simulation files
                        -- Other stuff?

                   -- Other?

                  - Sub-committee on Software Aspects....       
                    -- Members
                    -- links to minutes & Agendas
                  -- BIRDS
                    -- Education Topics
                   --?
                -- Other? 

  
<end>	


From owner-ibis  Wed Apr  8 18:21:25 1998
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From: John Lin - TAO <LinJohn@digital.com>
To: "'IBIS_USER'" <ibis-users@eda.org>,
        "'SI_LIST'"
	 <si-list@silab.eng.sun.com>
Cc: Dc Liu <Dc.Liu@digital.com>, Hw Cheng <chenghw@digital.com>,
        Jj Leu
	 <Jj.Leu@digital.com>, Steve Ting <Steve.Ting@digital.com>
Subject: How to do correlation with two extra Rising/Falling waveforms?
Date: Thu, 9 Apr 1998 09:13:26 +0800
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Hi ,

In the IBIS Forum's I/O BUFFER MODELING COOKBOOK, page 12, there is a 
table - "Recommended Load Circuits and Waveforms for V/T Data 
Extraction."

In the table, there are 4 waveforms to extract V/T data for [Rising 
Waveform] and [Falling Waveform] for a standard push/pull CMOS type 
buffer.

I/O buffer+ R-fixture+V_fixture.

For falling edge, two waveforms are obtained based on
(1)	V_fixture=0, and
(2)	V_fixture=VCC.

For rising edge, two waveforms are gathered based on
(3)	V_fixture=0, and
(4)	V_fixture=VCC.


The cookbook uses (2) and (3) to extract data in [Ramp] and says (1) 
and (4) are for correlation.

How is the correlation done?
 What information can be extracted from (1) and (4)?

Inside the Quad Design XTK manual, the (1) and (4) can be used to 
generate Ground
Bounce Model.  How?

Any inputs from you are appreciated.


Thanks,

JOHNLIN
CAE Engineer of EDA Department
Digital Equipment Corp. Taiwan Branch
Email: Linjohn@mail.dec.com
TEL: 1-886-3-3900000 ext. 2152


From owner-ibis  Thu Apr  9 06:12:30 1998
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Date: Thu, 9 Apr 1998 22:08:31 +0900 (JST)
Message-Id: <199804091308.WAA10247@mario.tdc.tijp.ti.com>
From: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
To: crokusek@qdt.com, huq@rockie.nsc.com
Cc: ibis-users@vhdl.org
Subject: [Re: Re: About WARNING of ibischk2]


  Chris, Syed, 
   thank you very much for your cooperation.

   We checked our spice netlist. The bugs were found in that.
  The warnings are cleared at the new IBIS model. Thank you 
  very much.

 - Regards,
    A.Takegama ( tkgm@tdc.tijp.ti.com )

     ************************************
     *   Name   : Akihiro Takegama      *
     *   E-mail : tkgm@tdc.tijp.ti.com  *
     *   Corp.  : Texas Instruments     *
     ************************************

------- Start of forwarded message -------
Sender: crokusek@qdt.com
Date: Mon, 06 Apr 1998 10:56:28 -0700
From: Chris Rokusek <crokusek@qdt.com>
Organization: Quad Design Technology
X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
Mime-Version: 1.0
To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
Cc: ibis-users@vhdl.org
Subject: Re: About WARNING of ibischk2
References: <199804061334.WAA20640@mario.tdc.tijp.ti.com>
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Akihiro,

I'm not sure I understand your question exactly.

The slope of the load line designated by "x"'s in your diagram is just
the load resistance 50 Ohms (= 50 Volts/Amp).  Its actually -50 due to
the current polarity.

The load-line represents the load resistor while the V/I curve
designated by "*" in your diagram represents the DC characteristics of
the totem pole output stage while driving low (top transistor off) shown
in Fig 2.

Hope this answers your question.

Chris


Akihiro Takegama wrote:
> 
>   Chris,
>     I'm sorry. I would like to cofirm my opinion, and I have one question.
> 
>    [1] Is slope of V(R) of <Fig 1> based on V(R) of <Fig 2>, isn't it ?
> 
>       <Fig 1>                                       <Fig 2>
>                        [Pulldown] + [GNDclamp]               --- Vcc         ---
>        (I)                     or [POWERclamp]                ^               ^
>            |                             *                    |   |           |
>      0.6A  x                    ****                          |   |           |
>            |  x            **                               |-+   | I         | V (Pch)
>            |     x     *                               +--o||     |           |
>            |        *                                  |    |-+   +------+    |
>            |     *  ^  x                             L |      |          |    V
>            |   *    |     x      slope = -50 Ohm     --+      +------+   |   ----
>            | *      |        x                         |      |      |   V    ^
>            *--------|-----------x---------             |    |-+      <        |
>          0.0V       |         3.3       (V)            +---||        < 50     | V (R)
>                             (V_fixture)                     |-+      <  Ohm   |
>            |<------>|<--------->|                             |      |        V
>              V(Pch)     V (R)                                ---    ---      ---
>                                                              ///    ///      ///
> 
>    [2] Could you tell me the reason why it is 2% ?
>       Is this must value ?
>        ( You decided the value on Oct. in 1996. )
>        If we decided the diode value, the value is lower the IV curve (leak).
> 
>       We have the IBIS check problem yet. The last warning disappeared by your
>      cooperation.
>       The max voltage value can't be up 2.81V. ( Below is in 3% margin )
>   ----------------------------------------------------------------------------
>   WARNING - Model 'inout': MAX AC Falling Endpoints (-0.00V,  2.73V) not within
>           0.055V (2%) of ( 0.00V,  2.81V) on VI curves for 50 Ohms to 0V
>   ----------------------------------------------------------------------------
> 
>  - Regards,
>     A.Takegama ( tkgm@tdc.tijp.ti.com )
> 
>     ************************************
>     *   Name   : Akihiro Takegama      *
>     *   E-mail : tkgm@tdc.tijp.ti.com  *
>     *   Corp.  : Texas Instruments     *
>     ************************************
> - -----------------------------------------------------------------------
> 
> - ------- Start of forwarded message -------
> Sender: crokusek@qdt.com
> Date: Wed, 01 Apr 1998 09:21:51 -0800
> From: Chris Rokusek <crokusek@qdt.com>
> Organization: Quad Design Technology
> X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> Mime-Version: 1.0
> To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> Cc: ibis-users@vhdl.org
> Subject: Re: [Re: About WARNING of ibischk2]
> References: <199804010915.SAA15589@mario.tdc.tijp.ti.com>
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Akihiro,
> 
> The "LOW" curve used in the DC vs. AC test is the sum of BOTH shunt
> curves (POWER_Clamp/GND_Clamp) + the Pulldown Curve.
> 
> Similarly the "HIGH" curve used in the test is the sum of BOTH shunt
> curves + Pullup Curve.
> 
> Chris
> 
> Akihiro Takegama wrote:
> >
> > Chris,
> >   thank you very much for your quick response and answer.
> >
> >   I would like to confirm my issue.
> >
> >   # Is it crosspoint 50 Ohm slope against the value of [Pulldown]
> >    + [Gndclamp] ?
> >
> >
> >       (I)
> >           |                             *  [Pulldown] + [GNDclamp]
> >     0.6A  x                    ****
> >           |  x            **
> >           |     x     *
> >           |        *
> >           |     *  ^  x
> >           |   *    |     x           slope = 50 Ohm
> >           | *      |        x
> >           *--------|-----------x---------
> >         0.0V       |        3.0 V     (V)
> >                 (0.95V)
> >                  #####
> >
> >  - Regards,
> >     A.Takegma
> > >     ************************************
> > >     *   Name   : Akihiro Takegama      *
> > >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> > >     *   Corp.  : Texas Instruments     *
> > >     ************************************
> >
> > -----------------------------------------------------------------------
> > ------- Start of forwarded message -------
> > Sender: crokusek@qdt.com
> > Date: Tue, 31 Mar 1998 10:01:46 -0800
> > From: Chris Rokusek <crokusek@qdt.com>
> > Organization: Quad Design Technology
> > X-Mailer: Mozilla 3.01 (X11; I; SunOS 4.1.4 sun4m)
> > Mime-Version: 1.0
> > To: Akihiro Takegama <tkgm@mario.tdc.tijp.ti.com>
> > Cc: ibis-users@vhdl.org
> > Subject: Re: About WARNING of ibischk2
> > References: <199803311308.WAA12838@mario.tdc.tijp.ti.com>
> > Content-Type: text/plain; charset=us-ascii
> > Content-Transfer-Encoding: 7bit
> >
> > Akihiro,
> >
> > The ibishk2 program is checking the first and last point of your Rising
> > and Falling AC Waveforms against the DC VI curves and given test load
> > (50 Ohms).
> >
> > For your case the message indicates that the first point given in the
> > Rising Waveform table is .74V.
> >
> > If you were to plot the intersection of a 50 Ohm to 3V load line (slope
> > = 50 V/I) and the given DC VI curve you would see that they interesect
> > at .95V (this is fist value in [3] below).
> >
> > So since
> >
> >      abs(.95 - .74) > 2% * (3 - .74)
> >                .21  > .045
> >
> > The checker will print a warning.
> >
> > The reason for the check is that the first and last points of the AC
> > waveforms are supposed to be the stable DC value when driving the given
> > load.
> >
> > Chris Rokusek
> > Viewlogic
> >
> > Akihiro Takegama wrote:
> > >
> > > To: IBIS-users,
> > >
> > >   Hello, I'm making the IBIS model. But I am confused at ibischk.
> > >  Could you support me ?
> > >
> > >   I have one question.
> > >
> > >   1 ) I made the IBIS model within "Rising Waveform" and "Falling
> > >      Waveform" and I ran the ibischk2. But many warning appeares
> > >      it's IBIS model, which like as below.
> > >       Could you please tell me how to calculate the value [3]. ?
> > >
> > > - ----------------------------------------------------------------------------
> > > WARNING - Model 'inout': MIN AC Rising Endpoints ( 0.74V,  3.00V) not within
> > >                                                    -------------
> > >                                                         [1]
> > >
> > >           0.045V (2%) of ( 0.95V,  3.00V) on VI curves for 50 Ohms to 3V
> > >           -----------    ----------------
> > >              [2]               [3]
> > > - -----------------------------------------------------------------------------
> > >
> > >  - Regards,
> > >     A.Takegama
> > >
> > >     ************************************
> > >     *   Name   : Akihiro Takegama      *
> > >     *   E-mail : tkgm@tdc.tijp.ti.com  *
> > >     *   Corp.  : Texas Instruments     *
> > >     ************************************
> > > ------- End of forwarded message -------
------- End of forwarded message -------
From owner-ibis  Fri Apr 10 07:21:02 1998
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From: BENOIT.B.M.MEYNIEL@RCM.thomson.fr
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To: ibis-users@vhdl.org
Subject: Question about differential devices
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Message-Id: <4218171610041998/A97171/BIGMAN/11C454111000@MHS>
Date: 10 Apr 1998 15:17:26 +0000
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Hey,

I would like to know if the value of the differantial input impedance of the
differential  receivers is taking into account into the IBIS specifications.
This value is typically very high but its influence can be important concerning
the quiecent points of the numerical links.
Anyone who is familiar with this please give me some coments .

Thank you,

Best regards,

Benoit MEYNIEL
From owner-ibis  Fri Apr 10 13:46:13 1998
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-- 
============================================================================
Steven Applen         Tel: (916) 356-6243       Office: FM3/2/A7           =
Intel Corporation, FM3-37                       Pgr: (916) 328-5447        =
1900 Prairie City Road, Folsom, CA 95630        Fax: (916) 356-6030        =
=     'There is no fate that cannot be surmounted by scorn,' Camus         =
============================================================================

From owner-ibis  Fri Apr 10 14:28:56 1998
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To: John Lin - TAO <LinJohn@digital.com>
cc: "'IBIS_USER'" <ibis-users@eda.org>,
        "'SI_LIST'" <si-list@silab.eng.sun.com>, Dc Liu <Dc.Liu@digital.com>,
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        Steve Ting <Steve.Ting@digital.com>
Subject: Re: How to do correlation with two extra Rising/Falling waveforms? 
In-reply-to: Your message of "Thu, 09 Apr 1998 09:13:26 +0800."
             <c=US%a=_%p=Digital%l=TAOEXC1-980409011326Z-609@hgobh1.hgo.dec.com> 
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From: Stephen Peters <sjpeters@ichips.intel.com>


Hello John:

   My comments are below:

    Regards,
    Stephen Peters
    Intel Corp.

> Hi ,
> 
> In the IBIS Forum's I/O BUFFER MODELING COOKBOOK, page 12, there is a 
> table - "Recommended Load Circuits and Waveforms for V/T Data 
> Extraction."
> 
> In the table, there are 4 waveforms to extract V/T data for [Rising 
> Waveform] and [Falling Waveform] for a standard push/pull CMOS type 
> buffer.
> 
> I/O buffer+ R-fixture+V_fixture.
> 
> For falling edge, two waveforms are obtained based on
> (1)	V_fixture=0, and
> (2)	V_fixture=VCC.
> 
> For rising edge, two waveforms are gathered based on
> (3)	V_fixture=0, and
> (4)	V_fixture=VCC.
> 
> 
> The cookbook uses (2) and (3) to extract data in [Ramp] and says (1) 
> and (4) are for correlation.

Yes, the 50 ohms to VCC and 50 ohms to gnd fixtures are used to extract
the data for the [Ramp] table, but the other two conditions are used to 
provides further detail about the switching characteristics of the 
buffer, so the simulator can build a better model.  I don't belive the 
cookbook says these waveforms are used only for corelation. 

> 
> How is the correlation done?
>  What information can be extracted from (1) and (4)?
> 
> Inside the Quad Design XTK manual, the (1) and (4) can be used to 
> generate Ground
> Bounce Model.  How?
> 
> Any inputs from you are appreciated.
> 
> 
> Thanks,


> 
> JOHNLIN
> CAE Engineer of EDA Department
> Digital Equipment Corp. Taiwan Branch
> Email: Linjohn@mail.dec.com
> TEL: 1-886-3-3900000 ext. 2152
> 


From owner-ibis  Sun Apr 12 14:40:46 1998
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 unsubscribe my hotmail account rajdang@hotmail.com

Thanks
Rajeev
From owner-ibis  Sun Apr 12 21:25:25 1998
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From owner-ibis  Mon Apr 13 09:38:17 1998
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Subject: Re: Question about differential devices
References: <4218171610041998/A97171/BIGMAN/11C454111000@MHS>
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BENOIT.B.M.MEYNIEL@RCM.thomson.fr wrote:
> 
> Hey,
> 
> I would like to know if the value of the differantial input impedance of the
> differential  receivers is taking into account into the IBIS specifications.
> This value is typically very high but its influence can be important concerning
> the quiecent points of the numerical links.
> Anyone who is familiar with this please give me some coments .

There is at present no explicit differential-impedance characterization.
OTOH:

1) I'm not aware of many devices which actually have a path directly
   between the two inputs.  What paths there are are typically
   reactive anyway.

2) The clamp curves are actually more general than a single scalar
   impedance for the inputs in isolation.

3) The v3 extensions make it possible to add explicit paths between
   pins, even to the extent of multiport networks.  Not fun, but
   then again shouldn't be needed very often.

-- 
D. C. Sessions
dc.sessions@tempe.vlsi.com
From owner-ibis  Tue Apr 14 10:44:18 1998
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From: "Charles Hymowitz" <charles@intusoft.com>
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Subject: Re: FW: EIAJ home page
Priority: normal
In-reply-to: <199804141526.KAA24865@hawk.us-power.com>

Thanks John. I looked at the EIAJ prED -5302 standards page on I/O
Interface Model Project Group. The pdf file for the standard doesn't
have all the fonts embedded so its kind of hard to download but
attached is the letter I sent the webmaster. What do you (and
others) think of my conclusion??

Dear prED -5302 Standards Webmaster
We are about to post a free utility to convert IBIS models into SPICE
models on our web site; a very important utility that is missing from
most SPICE users software. So we are very interested in the SPICE 
side of things. We would, in future, like to support the I/O modeling 
standard.

But one big problem, unless I am missing something with regard to the
proposed syntax, is that you are using non-standard Berkeley SPICE
syntax for the MOSFET element. I don't know who proposed this but it
won't work with anyone's SPICE simulator (except the one who proposed
the syntax I imagine)

Therefore this will slow acceptance of this standard dramatically
unless one of three things happen:

1) someone modifies the MOSFET code or B element behavioral model code
in Berkeley SPICE 3 to accept the syntax (then every SPICE vendor
could adapt the free Berkeley code into their simulator) or 

2) someone creates an XSPICE model (public domain AHDL available from
Georgia Tech Institute) using C code (again, then every SPICE vendor
could adapt the XSPICE code into their simulator) 

3) someone creates a utility to convert the prED-5302 model code into
a SPICE 2G.6 or SPICE 3 style model.

The problem with 3) is that you can't easily do table models in
SPICE2G syntax which is the only compatible standard SPICE syntax, and
SPICE 3 doesn't support a table model. Therefore unless 1) or 2) are
accomplished it appears that this "standard" will not become one.
 

Charles Hymowitz - V.P. Prod. Dev.
Intusoft
email: charles@intusoft.com, CompuServe: intusoft@compuserve.com
Web: http://www.intusoft.com
Tel. (310) 833-0710, Fax (310) 833-9658
P.O. Box 710, San Pedro CA. 90733-0710

Please visit our web site @ http://www.intusoft.com for more information
and lots of SPICE goodies.
From owner-ibis  Tue Apr 14 13:05:58 1998
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Charles Hymowitz wrote:
> 
> Thanks John. I looked at the EIAJ prED -5302 standards page on I/O
> Interface Model Project Group. The pdf file for the standard doesn't
> have all the fonts embedded so its kind of hard to download but
> attached is the letter I sent the webmaster. What do you (and
> others) think of my conclusion??
> 
> Dear prED -5302 Standards Webmaster
> We are about to post a free utility to convert IBIS models into SPICE
> models on our web site; a very important utility that is missing from
> most SPICE users software. So we are very interested in the SPICE
> side of things. We would, in future, like to support the I/O modeling
> standard.
> 
> But one big problem, unless I am missing something with regard to the
> proposed syntax, is that you are using non-standard Berkeley SPICE
> syntax for the MOSFET element. I don't know who proposed this but it
> won't work with anyone's SPICE simulator (except the one who proposed
> the syntax I imagine)
> 
> Therefore this will slow acceptance of this standard dramatically
> unless one of three things happen:
> 
> 1) someone modifies the MOSFET code or B element behavioral model code
> in Berkeley SPICE 3 to accept the syntax (then every SPICE vendor
> could adapt the free Berkeley code into their simulator) or
> 
> 2) someone creates an XSPICE model (public domain AHDL available from
> Georgia Tech Institute) using C code (again, then every SPICE vendor
> could adapt the XSPICE code into their simulator)
> 
> 3) someone creates a utility to convert the prED-5302 model code into
> a SPICE 2G.6 or SPICE 3 style model.
> 
> The problem with 3) is that you can't easily do table models in
> SPICE2G syntax which is the only compatible standard SPICE syntax, and
> SPICE 3 doesn't support a table model. Therefore unless 1) or 2) are
> accomplished it appears that this "standard" will not become one.
> 
> 
> Charles Hymowitz - V.P. Prod. Dev.
> Intusoft
> email: charles@intusoft.com, CompuServe: intusoft@compuserve.com
> Web: http://www.intusoft.com
> Tel. (310) 833-0710, Fax (310) 833-9658
> P.O. Box 710, San Pedro CA. 90733-0710
> 
> Please visit our web site @ http://www.intusoft.com for more information
> and lots of SPICE goodies.

The syntax is a proposal that can unify and null out some of the 
objections IC vendors have in giving out Spice models. It is true that
this is a new model and Spice vendors will have to impliment this in
their particuliar brand of Spice. Once done the model is portable in
any Spice that supports it. And there lies the advantage. There is no
standard for Spice. Therefore Berekley models are supported as they
evolve but not in the Berekley form. Hspice routinely modifies both
the model parasitics and syntax for example. They then may "fix" some
bugs and whala a non-standard model that only Hspice can support. There
are certain advantages in everybody's Spice. And I'm sure EDA vendors
want to keep it that way to distinguish and differentiate themselves. 
This proposal if adapted can become a standard for Spice vendors. It
will take some work on the part of the Spice vendors just like it took
work to support IBIS models in any Simulator. There are Spice vendors
who do support IBIS by the way. Again each Spice simulator takes 
advantage of the features implimented in their Spice to accomplish this.
Bob Ross posted an example IBIS Spice behavioral model that can be used
in most generic Spice programs. 

Best Regards,
From owner-ibis  Tue Apr 21 13:05:23 1998
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To: ibis-users@eda.org
From: Kathy Breda <breda@nesa.com> (by way of Kathy Breda <breda@nesa.com>)
Subject: REMINDER - IBIS USER MEETING THURS. 4/23 @3:00PM
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Hello!

Reminder - IBIS User meeting - This Week!
	
	Date:  Thursday, April 23, 1998
	Time:  3:00 PM - 5:00 PM
	Place: TRILOGIC (see directions below)

Please feel free to forward this message.  It has been
sent only to the IBIS-users@eda.com distribution list
to cut down on repeat messages.

	IBIS USER MEETING AGENDA
      -------------------------

Topic 1	Subcommittee on Accuracy - Greg Edlund
       A lot of activity has taken place and Greg will
       be presenting the details and looking for input

Topic 2	Subcommittee on Software Aspects of IBIS - Paul Galloway
       Ed Sayre and Paul recently met to discuss curriculum
       development on IBIS education.  Paul to provide report
       on those discussions.

Topic 3     Quick update on IBIS connector model BIRD - Fabrizio Zanella

      
Other Business - Kathy Breda, et al
	 Quick web page update
       IBIS summit hosted by local companies to coincide with PCB-East
	 Agenda and location for next meeting
	 Any other business of interest to the group


Directions to TRILOGIC:

301 Ballardvale St. Wilmington, MA 01887 
Phone: 978-658-3800 Fax: 978-657-5927


	From the North:

      Traveling South on Route 93, take exit # 41 “Route 125”. 
      At the end of the ramp, turn left onto Route 125. 
      At the first traffic light take a left onto Ballardvale Street. 
      Travel ~1 mile on Ballardvale Street. 
      When you see the ADC sign on your left, 
      look for TRILOGIC's driveway - the second one on the right.
      It is a blind driveway on the curve of the road - 
      93 Corporate Place South, 301 Ballardvale Street.
      TRILOGIC is located in suite # 3 at the end of the building.

      From the South:

      Traveling North on Route 93, take exit #41 “Route 125”. 
      At the end of the ramp, turn right onto route 125.
      At the first traffic light take a left onto Ballardvale Street. 
      Travel ~1 mile on Ballardvale Street. 
      When you see the ADC sign on your left, 
      look for TRILOGIC's driveway - the second on the right.
      It is a blind driveway on the curve of the road - 
      93 Corporate Place South, 301 Ballardvale Street.
      TRILOGIC is located in suite # 3 at the end of the building.

  PLEASE NOTE: 
There are several visitor parking spots reserved for your use at the 
front doors to the building.  Please ask the receptionist what
room we will be meeting in.
	
From owner-ibis  Fri Apr 24 11:25:23 1998
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From: "Domnitei, Michael" <michael.domnitei@intel.com>
To: ibis-users@eda.org
Subject: subscribe  to IBIS e-mail reflectors
Date: Fri, 24 Apr 1998 11:05:00 -0700
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   The following e-mail addresses are used:
  
     ibis-request@eda.org
      I request to join both:
                the IBIS Open Forum Reflector(ibis@eda.org), 
                the IBIS Users' Group Reflector (ibis-users@eda.org)
  
  
  thanks,
         Michael Domnitei, Intel, MMO - Simulation group,(503)-696-4692.  
                           michael.domnitei@intel.com
     
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Date: Thu, 30 Apr 1998 16:08:48 -0400
To: ibis-users@eda.org
From: Kathy Breda <breda@nesa.com>
Subject: IBIS User Group Minutes - 4/23/98 meeting
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--=====================_893981328==_
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***Minutes of the IBIS Users Group Meeting
   held at TRILOGIC on Thursday, April 23, 1998***


Thank you to Joe Socha for hosting the meeting at
TRILOGIC and providing refreshments.  

Next Meeting is Scheduled for Thursday, May 21, 1998
at 3:00PM.  The meeting will be hosted by Bruce Heilbrunn
of Stratus in Marlboro, MA.  We've met at Stratus
once before.  Directions to follow shortly.

Greg Edlund and Paul Galloway presented updates from their
respective sub-committees.  Greg discussed the IBIS accuracy
specification in terms of limiting its scope, test loads for 
the specification, the developer's tool kit and the test board.
Paul's focus was primarily on providing IBIS training.  Paul
also announced that he is changing positions within Cadence
and will no longer be heading up this Sub-Committee on IBIS
Software Aspects.  We're looking for a volunteer to step into
Paul's spot. Anyone??

Attached to this message are the presentations made by
Greg and Paul.  If you can't read the presentations, and
would like to send me your address or fax number
I will get the presentations to you.

Sub-Committee on Accuracy:
-------------------------


*  IBIS Accuracy Specification Scope -Proposed coverage of 
I/O buffer families is equivalent to IBIS 1.1.  
Limiting the scope allows the sub-committee to complete their task.

*  There is the hopeful belief that most simulation engines
output will match for IBIS 1.1 data sheet information.

*  The IBIS accuracy specification test loads include:
	For both Push-Pull and Open Drain -
	Standard load, T-Line Termm to VDD, T-Line Term GND,
	Open T-Line and DRV to RCV  
 
*  Request from Bruce Helbrunn to EDA vendors that free simulation
engine be made available to IC vendors  has received
a positive response from Quad Design, Interconnectix/Mentor and Cadence

*  User Group discussions/comments - Could IC vendors create models 
that match the EDA vendors model development tools?  There 
should be a common core that is an IBIS (1.1?) standard compliant model.  
Since IC and EDA vendors will probably be ahead of the IBIS standard, 
then comment section is needed to discuss enhancements.  Within
a level of accuracy, the EDA vendors IBIS models should all produce
the same answer.

*  Test board update - at least six weeks away from power-up of rev 2
test board.  Schematic rework is taking place right now.

*  Suggestion made that a round-robin type of testing activity take
place once the board is done.  Another suggestion is that a family
of test boards be designed to address different design environments.

* The next Accuracy sub-committee meeting is scheduled for 
Thursday, April 10th.  

Sub-Committee on Software Aspects of IBIS
-----------------------------------------

*  We're going to start having a IBIS topic presented at each meeting
for education purposes.

*  Cadence has just made available new IBIS software utilities
(http://www.cadence.com/software/pcb_info.htm)

*  Web page is moving along - Andrew has a first pass design in
place and a lot of information has been added into it.  A ways
to go, but it is going...

*  We would like to coordinate IBIS training with PCB-East in October,
and then perhaps repeat it at DesignCon99 in January.  Paul presented
a possible curriculum which is in one of the attached files(
U:\ibis_ug_.ppt;).

*  The idea is that the training will be available for use - no charge.

*  There is discussion that there should be a one day course, two day
course (with labs) and perhaps a shorter introductory course - like
a lunch time seminar to get the word around.

*  Regarding connector models - Fabrizio Zanella is heading up the effort
to resurrect BIRD 31.3 "Multiline Models".  The BIRD is being modified, but
it will not make IBIS 3.1 release. 

*  So far the following Connector/tools vendors have signed up for this effort
including:  Eric Bogatin of Ansoft, Gus Panella of Molex, 
Kellee Crisafulli of Hyperlynx, John Ellis of Berg 

Proposed Agenda for meeting on Thursday, May 21, 1998
-----------------------------------------------------

*  IBIS education topic - Review/Overview of IBIS versions
*  Update on Connector Modeling BIRD
*  Accuracy Specification and Test Board Update
*  More on IBIS education curriculum


Other Business
---------------

A lot of people seemed to miss the last meeting announcement and
directions because I sent it only to the ibis-users@eda.org distribution.  
I'm now sending it to a wider distribution to make sure I reach those
interested.
Let me know if you want you name pulled off of my distribution list.  I do
not have control of the ibis-users@eda.org list.

<end>   
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