From owner-ibis  Wed Apr 10 17:04:04 1996
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Date: Wed, 10 Apr 96 16:57:35 PDT
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9604102357.AA18632@rockie.nsc.com>
To: ibis-users@vhdl.org
Subject: Ramp rate and Rising/Falling waveform

IBISgurus:

Ramp rate has been defined to be measured WITHOUT package information.
Rising/Falling waveform has been defined to include the pkg and fixture
information seperately.

I think Ramp rate should have the same options as Rising/Falling, ie. the
ability to add pkg and fixture parameters. This will allow an easy way
to measure Ramp rate WITH a packaged unit and not on a 'bare die' !

I also wonder what inaccuracies I can expect if I provide Ramp rate
data on a packaged unit instead of a bare die.

Regards,
Syed
National Semiconductor

From owner-ibis  Thu Apr 18 03:37:55 1996
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Sender: fitzpat1@ln.cit.alcatel.fr
Message-Id: <317619EC.15FB7483@ln.cit.alcatel.fr>
Date: Thu, 18 Apr 1996 12:31:08 +0200
From: FITZPATRICK John <John.Fitzpatrick@ln.cit.alcatel.fr>
Organization: Alcatel CIT, 22304 Lannion, France
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To: ibis-users@vhdl.org
Subject: Switched clamping diodes & input I/V curves with hysteresis
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Hello all,

Yesterday, I discussed IBIS with one of our standard logic suppliers. 
They provide good Spice support, but are only beginning to get
interested in behavioural models.

Two issues were raised, summarized here for your information:

1) One family of components has a static input I/V characteristics
   which show a hysteresis effect: the response for a 0->1 transition
   is not the same as for a 1->0 transition, due to the design of
   a bus-hold circuit.

   My view is that IBIS doesn't allow this effect to be modelled.


2) One family of components switches out the power clamp
   diode whenever the output buffer is in tri-state.

   My view is that IBIS can model this buffer if the clamping diode
   characteristics are put in the [Pullup] table and the high-impedance
   characteristics in the [POWER Clamp] table.

   However, is there is a potential risk because the simulator
   will assume that the high-impedance characteristic is 
   constantly present, which is not the case? The risk is serious
   only if the high-impedance state is not so high (not the
   case for the logic family under discussion)


(There were some concerns also re internal feedback structures,
but the actual problems were not very clear to me.)

Any comments?

John

 
-- 
John Fitzpatrick   <John.Fitzpatrick@ln.cit.alcatel.fr>    
Alcatel CIT, 4 rue de Broglie, 22304 Lannion, France
Tel: (+33)96.04.79.33  Fax: (+33)96.04.85.09

From owner-ibis  Thu Apr 18 05:51:10 1996
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From: mellitz@eagle.ColumbiaSC.NCR.COM
>From: mellitz@eagle (Richard.Mellitz)
Content-Type: text
Message-Id: <9604180844.ZM12902@eagle>
Date: Thu, 18 Apr 1996 08:44:35 -0400
In-Reply-To: ln.cit.alcatel.fr!John.Fitzpatrick (FITZPATRICK John)
        "Switched clamping diodes & input I/V curves with hysteresis" (Apr 18, 12:31pm)
References: <317619EC.15FB7483@ln.cit.alcatel.fr>
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To: John.Fitzpatrick@ln.cit.alcatel.fr (FITZPATRICK John), ibis-users@vhdl.org
Subject: Re: Switched clamping diodes & input I/V curves with hysteresis

All,

I'd like to add to the list. I've recently encounter quite a few devices that
have basically 2 I-V curves. One for switching and one a few nanoseconds later.
I think this was discussed a while back but I can't remember the outcome.


Richard Mellitz, NCR

On Apr 18, 12:31pm, FITZPATRICK John wrote:
> Subject: Switched clamping diodes & input I/V curves with hysteresis
> Hello all,
> 
> Yesterday, I discussed IBIS with one of our standard logic suppliers. 
> They provide good Spice support, but are only beginning to get
> interested in behavioural models.
> 
> Two issues were raised, summarized here for your information:
> 
> 1) One family of components has a static input I/V characteristics
>    which show a hysteresis effect: the response for a 0->1 transition
>    is not the same as for a 1->0 transition, due to the design of
>    a bus-hold circuit.
> 
>    My view is that IBIS doesn't allow this effect to be modelled.
> 
> 
> 2) One family of components switches out the power clamp
>    diode whenever the output buffer is in tri-state.
> 
>    My view is that IBIS can model this buffer if the clamping diode
>    characteristics are put in the [Pullup] table and the high-impedance
>    characteristics in the [POWER Clamp] table.
> 
>    However, is there is a potential risk because the simulator
>    will assume that the high-impedance characteristic is 
>    constantly present, which is not the case? The risk is serious
>    only if the high-impedance state is not so high (not the
>    case for the logic family under discussion)
> 
> 
> (There were some concerns also re internal feedback structures,
> but the actual problems were not very clear to me.)
> 
> Any comments?
> 
> John
> 
>  
> -- 
> John Fitzpatrick   <John.Fitzpatrick@ln.cit.alcatel.fr>    
> Alcatel CIT, 4 rue de Broglie, 22304 Lannion, France
> Tel: (+33)96.04.79.33  Fax: (+33)96.04.85.09
>-- End of excerpt from FITZPATRICK John



