
From owner-ibis  Thu Mar  2 06:28:05 2000
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: Support of IBIS and IMIC
Date: Thu, 2 Mar 2000 09:26:15 -0500 
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>As far as I know, HSPICE supports IMIC also.  To what extent, I don't know.
 
I just came across this in the Release Notes for HSPICE version 1999.4:

>Pre-release Features
...
>Star-Hspice IMIC Table Model and IMIC to Hspice Interpreter
 
There is no mention of IMIC in the 99.2 HSPICE manual, and only a brief
paragraph in the 99.4 Release Notes.

From owner-ibis  Mon Mar  6 09:26:17 2000
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To All:

I am forwarding this offer to the IBIS reflectors for
DesignCon 2000 Proceedings.  

Note, that employees of EIA IBIS Open Forum Members will
receive the best discount.

Bob Ross
Mentor Graphics
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From: David Erickson <DErickson@iec.org>
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Bob, thank you, and IBIS for all of your participation at DesignCon 2000.
We are looking forward to continuing the relationship in 2001.  Below is the
text for our CD-Rom Discounts, that we request be placed on the IBIS
reflector, and included in an e-mail to your recipients, as appropriate.
Please let me know your thoughts about this, and get back to me when you
have a moment.  

 

Save more than 25% with post conference discounts!  <?xml:namespace prefix =
o ns = "urn:schemas-microsoft-com:office:office" />

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Full CD-ROM was $325.00 - now $240.00! 

 

Take advantage of these special discounts: 

 Receive an additional 10% off the discounted price if your company is a
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EXP _____/______  (MM/YY)

 

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[  ] VISA  [  ]   MASTERCARD  [  ] AMEX   [  ] DISCOVER   [  ] DINERS


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style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><SPAN 
class=634124219-03032000>Bob, thank you, and IBIS for all of your participation 
at DesignCon 2000.&nbsp; We are looking forward to continuing the relationship 
in 2001.&nbsp; Below is the text for our CD-Rom Discounts, that we request be 
placed on the IBIS reflector, and included in an e-mail to your recipients, as 
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<P class=MsoNormal style="mso-pagination: none"><SPAN 
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style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Full 
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style="BORDER-COLLAPSE: collapse; WIDTH: 483.3pt; mso-padding-alt: 0in 5.4pt 0in 5.4pt" 
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  <TBODY>
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      <P class=MsoNormal style="mso-pagination: none"><SPAN 
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      <P class=MsoNormal style="mso-pagination: none"><SPAN 
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      <P class=MsoNormal style="mso-pagination: none"><SPAN 
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    vAlign=top width=132>
      <P class=MsoNormal style="MARGIN-LEFT: 17.1pt; mso-pagination: none"><FONT 
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      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD>
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      <P class=MsoNormal style="mso-pagination: none"><SPAN 
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      <P class=MsoNormal style="mso-pagination: none"><FONT 
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<P class=MsoNormal style="mso-pagination: none"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></P>
<P class=MsoNormal style="mso-pagination: none"><SPAN 
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</SPAN>$240.00 (121 papers)<SPAN 
style="mso-tab-count: 1">&nbsp;&nbsp;&nbsp;&nbsp; </SPAN><SPAN 
style="mso-tab-count: 1">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
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<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
<TABLE border=0 cellPadding=0 cellSpacing=0 
style="BORDER-COLLAPSE: collapse; mso-padding-alt: 0in 5.4pt 0in 5.4pt; mso-table-layout-alt: fixed">
  <TBODY>
  <TR style="HEIGHT: 27.4pt">
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 171.9pt" 
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      <P class=MsoNormal style="mso-pagination: none"><B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Subtotal<o:p></o:p></SPAN></B></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.75in" 
    vAlign=top width=72>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.5in" 
    vAlign=top width=48>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 94.5pt" 
    vAlign=top width=126>
      <P class=MsoNormal style="mso-pagination: none"><B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$____________<o:p></o:p></SPAN></B></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 37.65pt" 
    vAlign=top width=50>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 27.4pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD></TR>
  <TR style="HEIGHT: 26.95pt">
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 171.9pt" 
    vAlign=top width=229>
      <P class=MsoNormal style="mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Domestic 
      Order Processing<o:p></o:p></SPAN></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.75in" 
    vAlign=top width=72>
      <P class=MsoNormal 
      style="MARGIN-LEFT: 3pt; TEXT-INDENT: -3.9pt; mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$10.00<o:p></o:p></SPAN></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.5in" 
    vAlign=top width=48>
      <P class=MsoNormal style="mso-pagination: none"><FONT 
      face=Arial>&nbsp;<SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 94.5pt" 
    vAlign=top width=126>
      <P class=MsoNormal style="mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$____________<o:p></o:p></SPAN></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 37.65pt" 
    vAlign=top width=50>
      <P class=MsoNormal style="mso-pagination: none"><FONT 
      face=Arial>&nbsp;<SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT 
      face=Arial>&nbsp;<SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.95pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT 
      face=Arial>&nbsp;<SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD></TR>
  <TR style="HEIGHT: 45.9pt">
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 171.9pt" 
    vAlign=top width=229>
      <P class=MsoNormal style="mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">International 
      Order Processing<o:p></o:p></SPAN></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.75in" 
    vAlign=top width=72>
      <P class=MsoNormal style="mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$25.00<o:p></o:p></SPAN></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.5in" 
    vAlign=top width=48>
      <P class=MsoNormal style="mso-pagination: none"><FONT 
      face=Arial>&nbsp;<SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></FONT></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 94.5pt" 
    vAlign=top width=126>
      <P class=MsoNormal style="mso-pagination: none"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$____________<B 
      style="mso-bidi-font-weight: normal"><o:p></o:p></B></SPAN></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 37.65pt" 
    vAlign=top width=50>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 45.9pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD></TR>
  <TR style="HEIGHT: 26.05pt">
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 171.9pt" 
    vAlign=top width=229>
      <P class=MsoNormal style="mso-pagination: none"><B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Total<o:p></o:p></SPAN></B></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.75in" 
    vAlign=top width=72>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 0.5in" 
    vAlign=top width=48>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 94.5pt" 
    vAlign=top width=126>
      <P class=MsoNormal style="mso-pagination: none"><B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">$____________<o:p></o:p></SPAN></B></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 37.65pt" 
    vAlign=top width=50>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD>
    <TD 
    style="HEIGHT: 26.05pt; PADDING-BOTTOM: 0in; PADDING-LEFT: 5.4pt; PADDING-RIGHT: 5.4pt; PADDING-TOP: 0in; WIDTH: 83.1pt" 
    vAlign=top width=111>
      <P class=MsoNormal style="mso-pagination: none"><FONT face=Arial>&nbsp;<B 
      style="mso-bidi-font-weight: normal"><SPAN 
      style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><o:p></o:p></SPAN></B></FONT></P></TD></TR></TBODY></TABLE>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'"><SPAN 
style="mso-tab-count: 1">&nbsp;</SPAN></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">To 
order via credit card, return this fax form today to +1-312-559-4111 or call 
Julie Brandt at +1-312-559-4609. <o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Credit 
Card #______________________________________________<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">EXP 
_____/______<SPAN style="mso-spacerun: yes">&nbsp; 
</SPAN>(MM/YY)<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">Name 
of Cardholder: _______________________________________<o:p></o:p></SPAN></B></P>
<P class=MsoNormal style="mso-pagination: none"><B 
style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">&nbsp;<o:p></o:p></SPAN></B></P>
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style="mso-bidi-font-weight: normal"><SPAN 
style="FONT-FAMILY: Arial; LAYOUT-GRID-MODE: line; mso-bidi-font-family: 'Times New Roman'">[<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>] VISA<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>[<SPAN style="mso-spacerun: yes">&nbsp; 
</SPAN>]<SPAN style="mso-spacerun: yes">&nbsp;&nbsp; </SPAN>MASTERCARD<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>[<SPAN style="mso-spacerun: yes">&nbsp; 
</SPAN>] AMEX<SPAN style="mso-spacerun: yes">&nbsp;&nbsp; </SPAN>[<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>] DISCOVER<SPAN 
style="mso-spacerun: yes">&nbsp;&nbsp; </SPAN>[<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>] 
DINERS</SPAN></B></P></DIV></FONT></BODY></HTML>

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From owner-ibis  Tue Mar  7 17:30:12 2000
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Date: Tue, 07 Mar 2000 17:28:19 -0800
From: Bob Ross <bob_ross@mentorg.com>
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
Subject: IBIS EUROPEAN SUMMIT MEETING THIRD ANNOUNCEMENT
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To All:

Please signup if you plan to attend.  Note, the signup person
has changed.  If you have any questions, contact me at the 
number at the end.

Bob Ross
Mentor Graphics

            E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                      T H I R D   A N N O U N C E M E N T

Time/Date:     8:30 AM - 2 PM, Friday, March 31, 2000

Location:      Concorde-Lafayette Hotel (adjacent to Le Palais des 
               Congress de Paris Porte Mailot - site of the DATE2000
               Conference in Paris, France

Rooms:         Salon Van Gogh/Pissarro

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      Cadence, INCASES, Mentor Graphics and Viewlogic

DATE2000:      March 27-30, 2000.  The IBIS meeting is scheduled the day
               following the trade show portion of the Conference and the
               PCB Symposium.

               See http://www.date-conference.com for more information.


BACKGROUND

For the last several years we have been holding very successful European IBIS
Summit Meetings.  We plan a combination of the following:

  Submitted Presentations on IBIS Topics (See below)
  Less formal Ad Hoc Presentations and Discussions
  IBIS Questions and Answers
  

TENTATIVE AGENDA SO FAR (titles may change)

Agenda includes presentations, discussions and a free lunch.  Some
presentations planned so far include:

Siemens IBIS Modeling Requirements for Semiconductor Vendors
Gerald Bannert, Siemens

IEC EMC/EMI Standardization Update
Jean Claude Perrin, Texas Instruments

Tips and Techniques for Creating IBIS Models
Cary Mandell, Viewlogic

IBIS Accuracy Study
Sherif Hammad, Mentor Graphics

Behavioral Receiver Modeling
Patrick Dos Santos, Cadence Design Systems

IBIS Future Directions
Bob Ross, Mentor Graphic


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please supply the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Francoise Lindecker (francoise_lindecker@mentor.com

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.  Some suggested subjects of interest are:

  IBIS Model Development Experiences
  Company IBIS Standards and Requirements
  Generating and Validating IBIS Models
  Future IBIS Requirements
  EMC/EMI IBIS Issues


Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Bob Ross (bob_ross@mentor.com)


FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com
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IBISgurus:

In many SRAM datasheets, they have a 'Undershoot Voltage' spec that looks 
like this:

     Vih________
		\
		 \
		  \          /\    ___________ Vss
		   \        /  \  /
		    \      /    \/
		---------------------     
		     |\  /|
		     | \/ |
	        --------------------- Vss - 1.0V
		---->|    |<---
		 
		"20% of Cycle time"
		
Question:
---------
1) Can this be modeled in IBIS ? if yes, by using which keyword ?

If the cool ASCII drawing got messed up by your mail system, refer to
Motorola SRAM databook for MCM63F737K/MCM63F819K.

Thanks,
Syed
Cisco Systems, Inc

From owner-ibis  Sun Mar 12 12:33:38 2000
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Date: Sun, 12 Mar 2000 12:32:15 -0800
To: ibis-users@eda.org
From: Gaurang Shah <gaurang.shah@icube.com>
Subject: Initial Help
Cc: ibis-info@eda.org
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Hello,

I am currently initiating IBIS model development here and I need a couple 
of clarifications.

1) Which version of model should I be developing?? Seems like Version 2.1 
seems to be the most commonly used models. Are most people developing in 
2.1 or customers demand version 3.1 and higher?

2) I plan to use the SPICE2IBIS utility, but it appears that shareware from 
North Carolina State  University generate 2.1 models only. Are there free 
tools available for higher version models or does one have to buy 
commercial tools?? If latter is the case what is the cost of them and who 
are the vendors??

Please help.

--Thanks

--Gaurang
From owner-ibis  Sun Mar 12 16:22:31 2000
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To: Gaurang Shah <gaurang.shah@icube.com>, ibis-users@eda.org
From: Kellee Crisafulli <kellee@nwlink.com>
Subject: Re: Initial Help
Cc: ibis-info@eda.org
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Most simulators and development tools support Version 2.1 IBIS models.
Tools and simulators in general support portions of the new version 3.2
features.
Not all version 3.2 features are supported by all tools and the current 
release of the Spice2Ibis only outputs Version 2.1.

I recommend you continue to create version 2.1 models unless you need
the extra features provided by 3.2  If you do then by all means create a
version 3.2
model.  In general most simulators will support the version number being 3.2
even if you are only using the version 2.1 feature set so you could choose
to always make version 3.2 models.  I don't know this for a fact so if you
want
your models to run on the most simulators possible than build v2.1 models
when possible.

my 2 cents worth...
Kellee


At 12:32 PM 3/12/00 -0800, Gaurang Shah wrote:
>Hello,
>
>I am currently initiating IBIS model development here and I need a couple 
>of clarifications.
>
>1) Which version of model should I be developing?? Seems like Version 2.1 
>seems to be the most commonly used models. Are most people developing in 
>2.1 or customers demand version 3.1 and higher?
>
>2) I plan to use the SPICE2IBIS utility, but it appears that shareware from 
>North Carolina State  University generate 2.1 models only. Are there free 
>tools available for higher version models or does one have to buy 
>commercial tools?? If latter is the case what is the cost of them and who 
>are the vendors??
>
>Please help.
>
>--Thanks
>
>--Gaurang
> 
From owner-ibis  Mon Mar 13 06:03:17 2000
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Subject: Re: Initial Help
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As an IBIS user and developer, I would strongly recommend

1) correlating IBIS-based behavioral simulations with HSPICE simulations
for a given set of test circuits, and
2) correlating HSPICE simulations with hardware.

There are some I/O circuit designs whose electrical behavior s2ibis2 will
miss.  Here's a list of things that you should watch out for:  multi-stage
drivers, dynamic clamping, dynamic impedance or edge rate control, any kind
of feedback, and stored charge effects.  Some of these things are covered
by IBIS 3.2, and some of them are not.  Sometimes you'll also find things
in hardware that aren't in your HSPICE model, for various reasons.

Item one above will be easier to accomplish than item two, which involves
adding some extra circuitry to your component characterization test bed.  A
few years ago a group of IBIS users got together and tried to spec some of
these things.  Have a look at the IBIS web page under "accuracy," and
you'll find a document that addresses the topic of correlation.  It's not
any official spec, but it does have some pretty helpful background
information.  I'd also strongly recommend documenting your correlation
results in a format that your users can quickly digest.

Speaking from experience, a behavioral model can seem simple at first
glance.  You may actually get IBIS code from s2ibis2 in less than a day.
However, there can be many little gotchas that you won't find until you do
the correlation work.

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


Gaurang Shah <gaurang.shah@icube.com> on 03/12/2000 02:32:15 PM

To:   ibis-users@eda.org
cc:   ibis-info@eda.org
Subject:  Initial Help




Hello,

I am currently initiating IBIS model development here and I need a couple
of clarifications.

1) Which version of model should I be developing?? Seems like Version 2.1
seems to be the most commonly used models. Are most people developing in
2.1 or customers demand version 3.1 and higher?

2) I plan to use the SPICE2IBIS utility, but it appears that shareware from
North Carolina State  University generate 2.1 models only. Are there free
tools available for higher version models or does one have to buy
commercial tools?? If latter is the case what is the cost of them and who
are the vendors??

Please help.

--Thanks

--Gaurang



From owner-ibis  Mon Mar 13 08:54:33 2000
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From: "Weston Beal" <weston_beal@mentorg.com>
To: "'Gaurang Shah'" <gaurang.shah@icube.com>
Cc: <ibis-users@eda.org>
Subject: RE: Initial Help
Date: Mon, 13 Mar 2000 08:55:53 -0800
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Gaurang,

The version of IBIS that you use depends on what features you need in order
to accurately describe your device.  If you don't need the advanced features
in IBIS 3.2 then use 2.1.

Be very careful with whatever tool you use to create IBIS files.  Remember
that these are just tools.  They are not engineers.  It takes an engineer
with a good understanding of IBIS to create good IBIS files with any tool.
The only tool that I know of that is not a derivative of the NCSU s2ibis is
from Applied Simulation Technology http://www.apsimtech.com/.  I saw a beta
version of their tool and it looked very good.

Regards,
Weston Beal


-----Original Message-----
From: Gaurang Shah [mailto:gaurang.shah@icube.com]
Sent: Sunday, March 12, 2000 12:32 PM
To: ibis-users@eda.org
Cc: ibis-info@eda.org
Subject: Initial Help


Hello,

I am currently initiating IBIS model development here and I need a couple
of clarifications.

1) Which version of model should I be developing?? Seems like Version 2.1
seems to be the most commonly used models. Are most people developing in
2.1 or customers demand version 3.1 and higher?

2) I plan to use the SPICE2IBIS utility, but it appears that shareware from
North Carolina State  University generate 2.1 models only. Are there free
tools available for higher version models or does one have to buy
commercial tools?? If latter is the case what is the cost of them and who
are the vendors??

Please help.

--Thanks

--Gaurang

From owner-ibis  Mon Mar 13 11:00:04 2000
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To: Syed Huq <shuq@cisco.com>
CC: ibis-users@eda.org
Subject: Re: SRAM undershoot and IBIS models
References: <200003110032.QAA27855@jasper.cisco.com>
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Syed Huq wrote:
> 
> IBISgurus:
> 
> In many SRAM datasheets, they have a 'Undershoot Voltage' spec that looks
> like this:
> 
>      Vih________
>                 \
>                  \
>                   \          /\    ___________ Vss
>                    \        /  \  /
>                     \      /    \/
>                 ---------------------
>                      |\  /|
>                      | \/ |
>                 --------------------- Vss - 1.0V
>                 ---->|    |<---
> 
>                 "20% of Cycle time"
> 
> Question:
> ---------
> 1) Can this be modeled in IBIS ? if yes, by using which keyword ?
> 
> If the cool ASCII drawing got messed up by your mail system, refer to
> Motorola SRAM databook for MCM63F737K/MCM63F819K.

Syed, how do you DO it?  This very question came up in last week's
JEDEC JC-42 meeting.  They're trying to write overshoot specs into
new standards but since this is a lifetime degradation issue there
MUST be something to enable duty-cycle limitations, which are
presently not supported in IBIS.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Thu Mar 16 11:49:24 2000
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Message-ID: <38D13A71.9414F384@vasthorizons.com>
Date: Thu, 16 Mar 2000 11:48:01 -0800
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: ibis <ibis-users@eda.org>
Subject: LVDS receivers with internal termination
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Anyone have any suggestions on how to use IBIS to
model LVDS receivers with built in internal 100 ohm
differential terminators?



--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


From owner-ibis  Thu Mar 16 14:12:50 2000
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To: Stephen_Miller@ne.3com.com, ibis <ibis-users@eda.org>
Subject: Re: LVDS receivers with internal termination
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Stephen,

Thanks for your reply. I will keep your thoughts in mind.
Unfortunately, HSPICE is not appropriate for full board and system
simulations with 100's or 1000's of differential pair nets.

I expect to perform some spice to ibis extractions and
correlations to Hspice in the next week.
I will let the reflector know what the results of my work are.


regards,

scott




Stephen_Miller@ne.3com.com wrote:

> Scott: We've found that Spice (we use HSPICE) is the only thing that works
> correctly so far. Our IBIS-based simulators aren't quite up to this just yet.
> Hope this helps.
>
>           Steve

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


From owner-ibis  Thu Mar 16 15:33:35 2000
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Reply-To: <jallen@IronBridgeNetworks.com>
From: "John D. Allen" <jallen@IronBridgeNetworks.com>
To: "ibis" <ibis-users@eda.org>
Subject: RE: LVDS receivers with internal termination
Date: Thu, 16 Mar 2000 18:33:09 -0500
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FYI: I know of two large companies that simulated entire boards with
thousands of nets with HSpice in order to get the accuracy that was needed.
In at least one of the cases, we built pre and post processor software to
generate the HSpice inputs with multiple VTT and Zo and Rt etc. and to sort
through the outputs to find potential violations.  This was in 1991.

The board took from Friday PM until Monday to run.  (On a Sun3 I think).

Regards, John Allen

John Allen  Sr. Consulting Engineer   jallen@IronBridgeNetworks.com
<mailto:jallen@IronBridgeNetworks.com>
IronBridge Networks / 55 Hayden Avenue / Lexington MA  02421 / USA
phone: 781-372-8151  fax:   781-372-8092  Main Number 781-372-8000
 
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Thursday, March 16, 2000 5:11 PM
> To: Stephen_Miller@ne.3com.com; ibis
> Subject: Re: LVDS receivers with internal termination
>
>
> Stephen,
>
> Thanks for your reply. I will keep your thoughts in mind.
> Unfortunately, HSPICE is not appropriate for full board and system
> simulations with 100's or 1000's of differential pair nets.
>
> I expect to perform some spice to ibis extractions and
> correlations to Hspice in the next week.
> I will let the reflector know what the results of my work are.
>
>
> regards,
>
> scott
>
> Stephen_Miller@ne.3com.com wrote:
>
> > Scott: We've found that Spice (we use HSPICE) is the only thing
> that works
> > correctly so far. Our IBIS-based simulators aren't quite up to
> this just yet.
> > Hope this helps.
> >
> >           Steve
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
>
>

From owner-ibis  Thu Mar 16 17:00:28 2000
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To: Scott McMorrow <scott@vasthorizons.com>, ibis <ibis-users@eda.org>
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: LVDS receivers with internal termination
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Hi Scott,

At 11:48 AM 3/16/00 -0800, Scott McMorrow wrote:
>Anyone have any suggestions on how to use IBIS to
>model LVDS receivers with built in internal 100 ohm
>differential terminators?

The existing IBIS specification allows this with 
the series resistor.

There is a bug in the IBIS golden parser that gives an
error message if you do it though.

It is also not supported by all simulators today but is
something I think most are adding.

Kellee


---------------------------------------------------------
Have a great day....
Kellee Crisafulli 
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Thu Mar 16 17:15:30 2000
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Scott:

To add to Kellee's comment, the support of allowing [R Series]
and other series elements connected to pins that are not just
Terminators or NC pins was changed in IBIS Version 3.2.  The
current text under the [Series Pin Mapping] keyword, Other Notes
section has this paragraph:

|               This mapping covers only the series paths between pins.  The
|               package parasitics and any other elements such as additional
|               capacitance or clamping circuitry are defined by the
|               model_name that is referenced in the [Pin] keyword.  The
|               model_names under the [Pin] keyword that are also referenced
|               by the [Series Pin Mapping] keyword may include any legal
|               model or reserved model except for Series and Series_switch
|               models.  Normally the pins will reference a [Model] whose
|               Model_type is 'Terminator'.  For example, a Series_switch
|               model may contain Terminator models on EACH of the pins to
|               describe both the capacitance on each pin and some clamping
|               circuitry that may exist on each pin.  In a similar manner,
|               Input, I/O or Output models may exist on each pin of a Series
|               model that is serving as a differential termination.  


Bob Ross
Mentor Graphics


Scott McMorrow wrote:
> 
> Anyone have any suggestions on how to use IBIS to
> model LVDS receivers with built in internal 100 ohm
> differential terminators?
> 
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
From owner-ibis  Fri Mar 17 02:11:49 2000
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From: "Sylvain Kubler" <skubl@hotmail.com>
To: ibis-users@eda.org
Subject: questions
Date: Fri, 17 Mar 2000 10:09:55 GMT
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Hi

I work in this moment on a project which uses the software of simulation 
PSpice I must use a model of LVDS (Low Voltage Differential signaling)which 
intervenes in my diagram of simulation. Thus I have telecharger a model IBIS 
corresponding exactly to the type of LVDS has to use (the sn65lvds31). The 
model is clear and decrit with precision its behavior electric.

Thus I have use a converter " IBIS to PSpice " in order to be able
to use this model. Conversion is well operee but the model, which was
initially in a block, is divided into 4 different modeles, each model
corresponding has a part private individual.
I am a little astonish in measurement where I expected has to have after 
conversion only one model PSpice decrivant a part.

You could can be to indicate to me if it is                                  
           correct (1 model IBIS generates 4 modeles PSpice) or if I made an 
error of handling.

Your answer could really help me. I thank you in advance for
your answer and asks you to accept the my most sincere greetings.


Sylvain Kubler.
______________________________________________________
Get Your Private, Free Email at http://www.hotmail.com

From owner-ibis  Mon Mar 20 10:30:10 2000
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From: "Mirmak, Michael" <michael.mirmak@intel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: Why no variable Vref in 3.2?
Date: Mon, 20 Mar 2000 10:28:39 -0800
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Fellow IBIS-fans,

We are seeing increasing numbers of buffers which require, per their
interface specifications, delay fixtures with variable reference voltages
(the pullup/pulldown voltage "Vref," not the measurement voltage "Vmeas").
A notable example is PCI, which has several recommended buffer delay
fixtures for timings generation, each with a resistor pullup voltage which
varies as the supply varies (in other words, with buffer corner).

I have two questions related to variable Vref:

1) IBIS 3.2 only supports [Model Spec] variation of input thresholds,
overshoots, pulse immunity and Vmeas; Vref cannot be varied using [Model
Spec].  Short of using [Model Selector], is their any convenient way to
specify Vref variation in an IBIS 3.2 model?  

2) I believe that a BIRD was proposed some time ago which added Vref, as
well as Cref and Rref, to the [Model Spec] keyword.  The BIRD was not
approved.  What was the reasoning behind keeping Vref, Cref and Rref out of
[Model Spec]?

Thanks in advance!

- Michael Mirmak
  Intel Corp.
  (916) 356-4261
  michael.mirmak@intel.com

From owner-ibis  Mon Mar 20 14:02:31 2000
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From: Bob Ross <bob_ross@mentorg.com>
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To: "Mirmak, Michael" <michael.mirmak@intel.com>
CC: "'ibis-users@eda.org'" <ibis-users@eda.org>, bob_ross@mentorg.com
Subject: Re: Why no variable Vref in 3.2?
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Michael:

BIRD66 has not been rejected.  It is still pending for
an IBIS Version 4.0 release.

We have not had time yet to consider it and some implications
of conflicting definitions and applications of timing measurement,
and also some possiblity of additional extensions in this area
(e.g., separate loads for rising and falling edges.)

I expect that some full discussions to be conducted
in the next teleconference meeting and possibly on the
IBIS reflectors.

Best Regards,
Bob Ross
Mentor Graphics


"Mirmak, Michael" wrote:
> 
> Fellow IBIS-fans,
> 
> We are seeing increasing numbers of buffers which require, per their
> interface specifications, delay fixtures with variable reference voltages
> (the pullup/pulldown voltage "Vref," not the measurement voltage "Vmeas").
> A notable example is PCI, which has several recommended buffer delay
> fixtures for timings generation, each with a resistor pullup voltage which
> varies as the supply varies (in other words, with buffer corner).
> 
> I have two questions related to variable Vref:
> 
> 1) IBIS 3.2 only supports [Model Spec] variation of input thresholds,
> overshoots, pulse immunity and Vmeas; Vref cannot be varied using [Model
> Spec].  Short of using [Model Selector], is their any convenient way to
> specify Vref variation in an IBIS 3.2 model?
> 
> 2) I believe that a BIRD was proposed some time ago which added Vref, as
> well as Cref and Rref, to the [Model Spec] keyword.  The BIRD was not
> approved.  What was the reasoning behind keeping Vref, Cref and Rref out of
> [Model Spec]?
> 
> Thanks in advance!
> 
> - Michael Mirmak
>   Intel Corp.
>   (916) 356-4261
>   michael.mirmak@intel.com
From owner-ibis  Mon Mar 20 15:10:48 2000
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To: "Mirmak, Michael" <michael.mirmak@intel.com>
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Subject: Re: Why no variable Vref in 3.2?
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On Mon, 20 Mar 2000, Mirmak, Michael wrote:
> 2) I believe that a BIRD was proposed some time ago which added Vref, as
> well as Cref and Rref, to the [Model Spec] keyword.  The BIRD was not
> approved.  What was the reasoning behind keeping Vref, Cref and Rref out of
> [Model Spec]?

I was not involved in that decision but ....

One of the problems we are facing with the growing ibis standard is
consistency.  Originally, there were some parameters, then [Model Spec]
was added.  Some parameters under it are new.  Some are repackaging of
some original parameters, with min and max added.  Now, we have some
twice.

Why can't they all have typ,min,max?  Just extend it on the same line
where it is.  Since we have [Model Spec], why not move them all there? and
obsolete the ones not under [Model Spec]?  Why do we need the duplication?

If all parameters were handled consistently, that would make it easier for
everyone, even if some of them have no real use.


From owner-ibis  Tue Mar 21 08:58:48 2000
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Message-ID: <38D8531F.FCF86B45@ti.com>
Date: Tue, 21 Mar 2000 22:59:11 -0600
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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Hello All,

I am attempting to create an IBIS model of an SSTL register. The register has 14 differential data inputs that are referenced to a common Vref input. How do I spec this in the IBIS model?

When they are added to the differential list I get an error stating:
"ERROR - Component 'sstv16857': inv_pin '35' is not unique." 

See pin list:
[Diff Pin]    inv_pin  vdiff   tdelay_typ
38              39       0        NA         <-clock pins.
48              35     150mv      NA         <-Here down are data pins.
47              35     150mv      NA
44              35     150mv      NA                          
43              35     150mv      NA
42              35     150mv      NA
41              35     150mv      NA
40              35     150mv      NA
33              35     150mv      NA
32              35     150mv      NA
31              35     150mv      NA
30              35     150mv      NA
29              35     150mv      NA
26              35     150mv      NA
25              35     150mv      NA

For a datasheet reference of a similar device please see:
http://www-s.ti.com/sc/psheets/scas625c/scas625c.pdf

Thanks.

-- 
Regards,
Stephen M. Nolan
From owner-ibis  Tue Mar 21 09:48:54 2000
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From: "Weston Beal" <weston_beal@mentorg.com>
To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
Subject: RE: Differential pins in IBIS
Date: Tue, 21 Mar 2000 09:50:15 -0800
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Stephen,

Although this receiver is implemented as a differential receiver, from the
outside it looks more like a single ended receiver because the system really
only feeds in one data signal.  Vref is held constant at 1.25V.  You can
simply use the parameters Vinl and Vinh to specify the thresholds Vref -
350mV (0.9V) and Vref + 350mv (1.6V).

Now, since Vref should follow Vcc, it changes for min and max cases.  For
this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
same but now have typ, min, and max values.

The IBIS committee is still working on the AC thresholds vs. DC thresholds
problem.

Regards,
Weston


-----Original Message-----
From: Stephen Nolan [mailto:s-nolan1@ti.com]
Sent: Tuesday, March 21, 2000 8:59 PM
To: ibis-users@eda.org
Subject: Differential pins in IBIS


Hello All,

I am attempting to create an IBIS model of an SSTL register. The register
has 14 differential data inputs that are referenced to a common Vref input.
How do I spec this in the IBIS model?

When they are added to the differential list I get an error stating:
"ERROR - Component 'sstv16857': inv_pin '35' is not unique."

See pin list:
[Diff Pin]    inv_pin  vdiff   tdelay_typ
38              39       0        NA         <-clock pins.
48              35     150mv      NA         <-Here down are data pins.
47              35     150mv      NA
44              35     150mv      NA
43              35     150mv      NA
42              35     150mv      NA
41              35     150mv      NA
40              35     150mv      NA
33              35     150mv      NA
32              35     150mv      NA
31              35     150mv      NA
30              35     150mv      NA
29              35     150mv      NA
26              35     150mv      NA
25              35     150mv      NA

For a datasheet reference of a similar device please see:
http://www-s.ti.com/sc/psheets/scas625c/scas625c.pdf

Thanks.

--
Regards,
Stephen M. Nolan

From owner-ibis  Tue Mar 21 11:00:29 2000
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Weston Beal wrote:
> 
> Stephen,
> 
> Although this receiver is implemented as a differential receiver, from the
> outside it looks more like a single ended receiver because the system really
> only feeds in one data signal.  Vref is held constant at 1.25V.  You can
> simply use the parameters Vinl and Vinh to specify the thresholds Vref -
> 350mV (0.9V) and Vref + 350mv (1.6V).
> 
> Now, since Vref should follow Vcc, it changes for min and max cases.  For
> this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
> same but now have typ, min, and max values.

Not good enough.  Vref and Vtt are related to Vddq, but there are both
tolerances and noise terms involved which don't track the simplistic
typ/min/max axis.  In particular, for the devices Mr. Nolan is discussing,
the common-mode rejection of the receivers is an issue.  Differential is
a must.

For instance, right now there is a JC-42.3 task group dealing with the
impact of SSI noise on Vref.  Crosstalk analysis where is can make or
break standard technology.

> The IBIS committee is still working on the AC thresholds vs. DC thresholds
> problem.

One of the reasons that Mr. Nolan now represents TI on the IBIS committee.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Mar 21 12:18:37 2000
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From: "Weston Beal" <weston_beal@mentorg.com>
To: <si-list@silab.eng.sun.com>, <ibis-users@eda.org>
Subject: meaning and value of C_comp
Date: Tue, 21 Mar 2000 12:19:57 -0800
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Dear IC experts,

I've been working a problem that might involve the C_comp parameter in an
IBIS file.  In discussion with others, I find some difference of opinion.
the IBIS spec says that C_comp represents the capacitance on the die.  I
understand this to be the bond pad, clamp diode reverse bias capacitance,
and final stage transistor channel capacitance.  What other effects are
important contributors to C_comp?  I suspect that the bond pad is the
dominant factor in todays technology.  Is that correct?  What are typical
values for the components I've listed?

I appreciate your insight on this matter.

Regards,
Weston

From owner-ibis  Tue Mar 21 12:55:18 2000
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Weston Beal wrote:
> 
> Dear IC experts,
> 
> I've been working a problem that might involve the C_comp parameter in an
> IBIS file.  In discussion with others, I find some difference of opinion.
> the IBIS spec says that C_comp represents the capacitance on the die.  I
> understand this to be the bond pad, clamp diode reverse bias capacitance,
> and final stage transistor channel capacitance.  What other effects are
> important contributors to C_comp?  I suspect that the bond pad is the
> dominant factor in todays technology.  Is that correct?  What are typical
> values for the components I've listed?

C_Comp is whatever value most closely approximates the high-frequency
response that an incoming wave 'sees' hitting the IC.  Personally, I
prefer deriving it from doing a best-fit optimization matching a cap
to a fully extracted SPICE netlist of the physical part.  For most
I/O cells this runs just a bit over 1.0 pf, mostly in the gate/drain
capacitance of the output devices.  The other contributors (diffusion
to bulk, pad to substrate) have such high ESR as to be negligible.

Warning: most test groups want to measure input capacitance at 1 MHz,
and this gives dramatically higher values.  There's been blood on the
floor in JEDEC meetings over this very difference.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Tue Mar 21 14:14:59 2000
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Subject: Re: [SI-LIST] : meaning and value of C_comp
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Here's another thing to consider:  what if you have an on-chip series
resistor?  Physically speaking, some of the C_comp is distributed on the
FET side of the resistor, and some of it is on the pad side.  Behavioral
simulators assume that all C_comp is in once place and all of the impedance
is in one place (from a network topology point of view).  When the device
is tri-stated you still have a distributed network in real life, but you
have a very high impedance plus a lumped capacitance in your behavioral
model.  This almost begs for a distributed model.

I like to use a TDR to measure pin capacitance in the lab, but I'm not even
sure that a TDR will give you the right answer in this case.

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
03/21/2000 04:06 PM ---------------------------

"D. C. Sessions" <dc.sessions@vlsi.com> on 03/21/2000 02:53:40 PM

To:   si-list@silab.eng.sun.com
cc:   ibis-users@eda.org
Subject:  Re: [SI-LIST] : meaning and value of C_comp




Weston Beal wrote:
>
> Dear IC experts,
>
> I've been working a problem that might involve the C_comp parameter in an
> IBIS file.  In discussion with others, I find some difference of opinion.
> the IBIS spec says that C_comp represents the capacitance on the die.  I
> understand this to be the bond pad, clamp diode reverse bias capacitance,
> and final stage transistor channel capacitance.  What other effects are
> important contributors to C_comp?  I suspect that the bond pad is the
> dominant factor in todays technology.  Is that correct?  What are typical
> values for the components I've listed?

C_Comp is whatever value most closely approximates the high-frequency
response that an incoming wave 'sees' hitting the IC.  Personally, I
prefer deriving it from doing a best-fit optimization matching a cap
to a fully extracted SPICE netlist of the physical part.  For most
I/O cells this runs just a bit over 1.0 pf, mostly in the gate/drain
capacitance of the output devices.  The other contributors (diffusion
to bulk, pad to substrate) have such high ESR as to be negligible.

Warning: most test groups want to measure input capacitance at 1 MHz,
and this gives dramatically higher values.  There's been blood on the
floor in JEDEC meetings over this very difference.

--
D. C. Sessions
dc.sessions@vlsi.com



From owner-ibis  Tue Mar 21 14:34:45 2000
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CC: ibis-users@vhdl.org
Subject: Re: [SI-LIST] : meaning and value of C_comp
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gedlund@us.ibm.com wrote:
> 
> Here's another thing to consider:  what if you have an on-chip series
> resistor?  Physically speaking, some of the C_comp is distributed on the
> FET side of the resistor, and some of it is on the pad side.  Behavioral
> simulators assume that all C_comp is in once place and all of the impedance
> is in one place (from a network topology point of view).  When the device
> is tri-stated you still have a distributed network in real life, but you
> have a very high impedance plus a lumped capacitance in your behavioral
> model.  This almost begs for a distributed model.
> 
> I like to use a TDR to measure pin capacitance in the lab, but I'm not even
> sure that a TDR will give you the right answer in this case.

The good news is that it doesn't matter.
Even the dominant effect of C_comp is down in the ~50 ps ballpark; the
second- and third-order contributors are truly in the noise.

> ---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
> 03/21/2000 04:06 PM ---------------------------
> 
> "D. C. Sessions" <dc.sessions@vlsi.com> on 03/21/2000 02:53:40 PM
> 
> To:   si-list@silab.eng.sun.com
> cc:   ibis-users@eda.org
> Subject:  Re: [SI-LIST] : meaning and value of C_comp
> 
> Weston Beal wrote:
> >
> > Dear IC experts,
> >
> > I've been working a problem that might involve the C_comp parameter in an
> > IBIS file.  In discussion with others, I find some difference of opinion.
> > the IBIS spec says that C_comp represents the capacitance on the die.  I
> > understand this to be the bond pad, clamp diode reverse bias capacitance,
> > and final stage transistor channel capacitance.  What other effects are
> > important contributors to C_comp?  I suspect that the bond pad is the
> > dominant factor in todays technology.  Is that correct?  What are typical
> > values for the components I've listed?
> 
> C_Comp is whatever value most closely approximates the high-frequency
> response that an incoming wave 'sees' hitting the IC.  Personally, I
> prefer deriving it from doing a best-fit optimization matching a cap
> to a fully extracted SPICE netlist of the physical part.  For most
> I/O cells this runs just a bit over 1.0 pf, mostly in the gate/drain
> capacitance of the output devices.  The other contributors (diffusion
> to bulk, pad to substrate) have such high ESR as to be negligible.
> 
> Warning: most test groups want to measure input capacitance at 1 MHz,
> and this gives dramatically higher values.  There's been blood on the
> floor in JEDEC meetings over this very difference.
> 
> --
> D. C. Sessions
> dc.sessions@vlsi.com

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Wed Mar 22 00:20:20 2000
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From: ecalvo <Eva.Calvo.Giraldo@cern.ch>
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Hello!

I'm not an expert in IBIS models, neither in Pspice, but I'm doing
something that I think is very similar what you explained here, and
perhaps I could help you.
I am simulating with Pspice a backplane that uses LVDS technology, and I
need the Pspice models of some transceivers (DS92LV090A). Unfortunately,
the only that I have is the IBIS model of this devices.
I don't know what translator are you using,but I used the shareware
software Ibis2spice from Intusoft, with a template that Microsim(/Orcad)
gives.
This software gives to you the next Pspice models:
	- One Pspice model for every pin of the device that you select.
	- The Pspice model of the Pull_Down.
	- The Pspice model of the Pull_Up.
	- The Pspice model of the Gnd_clamp.
	- The Pspice model of the Power_Clamp.   

The Gnd_clamp and/or Power_clamp could not be present depending of your
device.

I can't garantee the fidelity of this translation already, because now
I'm working in the validation of the models obtained.

I hope this information have been helpful. If you have any doubt more,
don't doubt aks me, I will do what I can. Perhaps we can help each
other.

Best regards,

	Eva.

> 
> Subject: questions
> Date: Fri, 17 Mar 2000 10:09:55 GMT
> From: "Sylvain Kubler" <skubl@hotmail.com>
> To: ibis-users@eda.org
> 
> Hi
> 
> I work in this moment on a project which uses the software of simulation
> PSpice I must use a model of LVDS (Low Voltage Differential signaling)which
> intervenes in my diagram of simulation. Thus I have telecharger a model IBIS
> corresponding exactly to the type of LVDS has to use (the sn65lvds31). The
> model is clear and decrit with precision its behavior electric.
> 
> Thus I have use a converter " IBIS to PSpice " in order to be able
> to use this model. Conversion is well operee but the model, which was
> initially in a block, is divided into 4 different modeles, each model
> corresponding has a part private individual.
> I am a little astonish in measurement where I expected has to have after
> conversion only one model PSpice decrivant a part.
> 
> You could can be to indicate to me if it is
>            correct (1 model IBIS generates 4 modeles PSpice) or if I made an
> error of handling.
> 
> Your answer could really help me. I thank you in advance for
> your answer and asks you to accept the my most sincere greetings.
> 
> Sylvain Kubler.
> ______________________________________________________
> Get Your Private, Free Email at http://www.hotmail.com

-- 
--------------------------------------------------------------
|  Eva M. Calvo                                              |
|  CERN - European Laboratory for Particle Physics	     |
|  IT/CE/AE                                                  |
|  							     |
|  Building 31/S-022			                     |
|  CH-1211 Geneva 23            			     |
|  tel    : +41 22 76 74830   				     |
|  fax    : +41 22 76 77155 				     |
|  mailto:eva.calvo.giraldo@cern.ch        		     |
|                     					     |
--------------------------------------------------------------
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Date: Wed, 22 Mar 2000 13:25:25 -0500
From: Christian Klein <Christian.Klein@fairchildsemi.com>
Subject: Re: Differential pins in IBIS
To: "D. C. Sessions" <dc.sessions@vlsi.com>
Cc: ibis-users@eda.org
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DC, Stephen,

What if you  created additional "virtual" Vref pins, and referenced each
differential input to a different pin? I don't think this would be a problem, as
long as they share the same POWER and GND busses.

Regards,
Christian Klein

"D. C. Sessions" wrote:

> Weston Beal wrote:
> >
> > Stephen,
> >
> > Although this receiver is implemented as a differential receiver, from the
> > outside it looks more like a single ended receiver because the system really
> > only feeds in one data signal.  Vref is held constant at 1.25V.  You can
> > simply use the parameters Vinl and Vinh to specify the thresholds Vref -
> > 350mV (0.9V) and Vref + 350mv (1.6V).
> >
> > Now, since Vref should follow Vcc, it changes for min and max cases.  For
> > this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
> > same but now have typ, min, and max values.
>
> Not good enough.  Vref and Vtt are related to Vddq, but there are both
> tolerances and noise terms involved which don't track the simplistic
> typ/min/max axis.  In particular, for the devices Mr. Nolan is discussing,
> the common-mode rejection of the receivers is an issue.  Differential is
> a must.
>
> For instance, right now there is a JC-42.3 task group dealing with the
> impact of SSI noise on Vref.  Crosstalk analysis where is can make or
> break standard technology.
>
> > The IBIS committee is still working on the AC thresholds vs. DC thresholds
> > problem.
>
> One of the reasons that Mr. Nolan now represents TI on the IBIS committee.
>
> --
> D. C. Sessions
> dc.sessions@vlsi.com

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From owner-ibis  Wed Mar 22 10:52:13 2000
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Christian Klein wrote:
> 
> DC, Stephen,
> 
> What if you  created additional "virtual" Vref pins, and referenced each
> differential input to a different pin? I don't think this would be a problem, as
> long as they share the same POWER and GND busses.

I talked about this with Bob Ross (Please chime in, Bob) and it seems
that this is one of those cases where Mr. Nolan's IBIS files are
within the letter of the specification but violate tool requirements.

Arguably, we don't need to make any changes in IBIS to accomodate this
application, except maybe some comments to the effect that this is a
supported use.  The tool companies just need a nudge to get them to
support this.

In the meantime, your proposed workaround might trick them into doing
what they Should Have In the First Place.

> "D. C. Sessions" wrote:
> 
> > Weston Beal wrote:
> > >
> > > Stephen,
> > >
> > > Although this receiver is implemented as a differential receiver, from the
> > > outside it looks more like a single ended receiver because the system really
> > > only feeds in one data signal.  Vref is held constant at 1.25V.  You can
> > > simply use the parameters Vinl and Vinh to specify the thresholds Vref -
> > > 350mV (0.9V) and Vref + 350mv (1.6V).
> > >
> > > Now, since Vref should follow Vcc, it changes for min and max cases.  For
> > > this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
> > > same but now have typ, min, and max values.
> >
> > Not good enough.  Vref and Vtt are related to Vddq, but there are both
> > tolerances and noise terms involved which don't track the simplistic
> > typ/min/max axis.  In particular, for the devices Mr. Nolan is discussing,
> > the common-mode rejection of the receivers is an issue.  Differential is
> > a must.
> >
> > For instance, right now there is a JC-42.3 task group dealing with the
> > impact of SSI noise on Vref.  Crosstalk analysis where is can make or
> > break standard technology.
> >
> > > The IBIS committee is still working on the AC thresholds vs. DC thresholds
> > > problem.
> >
> > One of the reasons that Mr. Nolan now represents TI on the IBIS committee.
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com

-- 
D. C. Sessions
dc.sessions@vlsi.com
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
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Subject: EUROPEAN IBIS SUMMIT MEETING AGENDA
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To All:

Below is the planned agenda of the European IBIS Summit Meeting
in Paris, France.  The meeting consists of discussions and
presentations.

The meeting is free to people interested in IBIS modeling, digital
circuit design and related EDA tool development.  Refreshments and
a buffet lunch are included.

If you plan to attend, please notify Francoise Lindecker at the
address at the end.

Bob Ross
Mentor Graphics
Chair, EIA IBIS Open Forum

------------------------------------------------------------------

               AGENDA, EUROPEAN IBIS SUMMIT MEETING
                     Friday, March 31, 2000

                  Room: Salon Van Gogh/Pissarro
                     Concorde-Lafayette Hotel                  
                          Paris, France
   
------------------------------------------------------------------

8:30     REFRESHMENTS & SIGN IN

9:00     INTRODUCTIONS
          - Welcome to Summit - Bob Ross, Mentor Graphics
          - Introductions 

9:15     SIEMENS IBIS MODELING REQUIREMENTS
         Gerald Bannert, Siemens

9:45     TIPS AND TRICKS FOR CREATING IBIS MODELS
         Cary Mandel, Viewlogic Systems

10:15    BREAK

10:30    IBIS ACCURACY STUDIES
         Sherif Hammad, Mentor Graphics

11:00    TC93 WG6 EMC/EMI IC MODEL STANDARDIZATION REPORT
         Jean-Claude Perrin, Texas Instruments

11:45    BUFFET LUNCH (Hosted by Cadence Design)

12:30    BEHAVIORAL RECEIVER MODELING
         Patrick Dos Santos, Cadence Design

13:15    IBIS FUTURE ACTIVITIES (and Discussion)
         Bob Ross, Mentor Graphics

13:45    OPEN DISCUSSIONS

14:00    BREAK AND END OF MEETING

         CONTINUATION OF OPEN DISCUSSIONS

------------------------------------------------------------------

Sponsors:      Cadence, INCASES, Mentor Graphics and Viewlogic

DATE2000:      March 27-30, 2000.  The IBIS meeting is scheduled the day
               following the trade show portion of the Conference and the
               PCB Symposium.

               See http://www.date-conference.com for more information.

SIGNUP

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to attend, please supply the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Francoise Lindecker (francoise_lindecker@mentor.com)
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Date: Wed, 22 Mar 2000 15:20:14 -0800
From: Bob Ross <bob_ross@mentorg.com>
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Subject: Re: Differential pins in IBIS
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		 <38D7C659.1769D954@vlsi.com> <38D91014.D99AD67F@fairchildsemi.com> <38D915EE.D47888AA@vlsi.com>
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Stephen, D. C., etc.:

All that I can add to this is that I believe BIRD62.6
additions will provide additional detail for this
technology.  The data input pins should be treated as
single-ended inputs based on the function table of
the SN74SSTL16857.

Bob Ross
Mentor Graphics


"D. C. Sessions" wrote:
> 
> Christian Klein wrote:
> >
> > DC, Stephen,
> >
> > What if you  created additional "virtual" Vref pins, and referenced each
> > differential input to a different pin? I don't think this would be a problem, as
> > long as they share the same POWER and GND busses.
> 
> I talked about this with Bob Ross (Please chime in, Bob) and it seems
> that this is one of those cases where Mr. Nolan's IBIS files are
> within the letter of the specification but violate tool requirements.
> 
> Arguably, we don't need to make any changes in IBIS to accomodate this
> application, except maybe some comments to the effect that this is a
> supported use.  The tool companies just need a nudge to get them to
> support this.
> 
> In the meantime, your proposed workaround might trick them into doing
> what they Should Have In the First Place.
> 
> > "D. C. Sessions" wrote:
> >
> > > Weston Beal wrote:
> > > >
> > > > Stephen,
> > > >
> > > > Although this receiver is implemented as a differential receiver, from the
> > > > outside it looks more like a single ended receiver because the system really
> > > > only feeds in one data signal.  Vref is held constant at 1.25V.  You can
> > > > simply use the parameters Vinl and Vinh to specify the thresholds Vref -
> > > > 350mV (0.9V) and Vref + 350mv (1.6V).
> > > >
> > > > Now, since Vref should follow Vcc, it changes for min and max cases.  For
> > > > this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
> > > > same but now have typ, min, and max values.
> > >
> > > Not good enough.  Vref and Vtt are related to Vddq, but there are both
> > > tolerances and noise terms involved which don't track the simplistic
> > > typ/min/max axis.  In particular, for the devices Mr. Nolan is discussing,
> > > the common-mode rejection of the receivers is an issue.  Differential is
> > > a must.
> > >
> > > For instance, right now there is a JC-42.3 task group dealing with the
> > > impact of SSI noise on Vref.  Crosstalk analysis where is can make or
> > > break standard technology.
> > >
> > > > The IBIS committee is still working on the AC thresholds vs. DC thresholds
> > > > problem.
> > >
> > > One of the reasons that Mr. Nolan now represents TI on the IBIS committee.
> > >
> > > --
> > > D. C. Sessions
> > > dc.sessions@vlsi.com
> 
> --
> D. C. Sessions
> dc.sessions@vlsi.com
From owner-ibis  Thu Mar 23 07:26:50 2000
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Date: Thu, 23 Mar 2000 21:27:06 -0600
From: Stephen Nolan <s-nolan1@ti.com>
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Subject: Re: Differential pins in IBIS
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			 <38D7C659.1769D954@vlsi.com> <38D91014.D99AD67F@fairchildsemi.com> <38D915EE.D47888AA@vlsi.com> <38D9552E.C8B3CF8D@mentor.com>
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Bob, D.C., et. al.,

To me, this seems to be a spec interpretation issue. It's an old story, and one that we are all familiar with: the user interprets the spec one way and the supplier interprets it another. In my case, it appears that the spec supports the way that I intend to use the IBIS file (and it would be nice if IBIS acually supported putting CORRECT data in about the part, and not some workaround). There is nothing in the spec that states that each pin of a diff pair must be unique and seperate from another diff pin pair. The golden parser, and apparently therefore the EDA tools interpret this differently.

These inputs are in fact differential, and to model them as single-ended is wrong. The Vinh and Vinl levels move around WRT Vref. Vref does NOT necessarily follow Vcc. It should follow Vddq of the transmitting device which can move around independantly of the typ/min/max case of the receiving device that I am modeling, especially when you consider the additive transmission line effects, xtalk, etc. 

If I model the inputs as single-ended HOW do I spec correct Vinh and Vinl levels? IBIS is a DATA TRANSMISSION tool. If it does not adequately allow me to transmit the CORRECT factual information about my device then IBIS is BROKEN!

-- 
Regards,
Stephen M. Nolan


Bob Ross wrote:
> 
> Stephen, D. C., etc.:
> 
> All that I can add to this is that I believe BIRD62.6
> additions will provide additional detail for this
> technology.  The data input pins should be treated as
> single-ended inputs based on the function table of
> the SN74SSTL16857.
> 
> Bob Ross
> Mentor Graphics
> 
> "D. C. Sessions" wrote:
> >
> > Christian Klein wrote:
> > >
> > > DC, Stephen,
> > >
> > > What if you  created additional "virtual" Vref pins, and referenced each
> > > differential input to a different pin? I don't think this would be a problem, as
> > > long as they share the same POWER and GND busses.
> >
> > I talked about this with Bob Ross (Please chime in, Bob) and it seems
> > that this is one of those cases where Mr. Nolan's IBIS files are
> > within the letter of the specification but violate tool requirements.
> >
> > Arguably, we don't need to make any changes in IBIS to accomodate this
> > application, except maybe some comments to the effect that this is a
> > supported use.  The tool companies just need a nudge to get them to
> > support this.
> >
> > In the meantime, your proposed workaround might trick them into doing
> > what they Should Have In the First Place.
> >
> > > "D. C. Sessions" wrote:
> > >
> > > > Weston Beal wrote:
> > > > >
> > > > > Stephen,
> > > > >
> > > > > Although this receiver is implemented as a differential receiver, from the
> > > > > outside it looks more like a single ended receiver because the system really
> > > > > only feeds in one data signal.  Vref is held constant at 1.25V.  You can
> > > > > simply use the parameters Vinl and Vinh to specify the thresholds Vref -
> > > > > 350mV (0.9V) and Vref + 350mv (1.6V).
> > > > >
> > > > > Now, since Vref should follow Vcc, it changes for min and max cases.  For
> > > > > this we use Vinl and Vinh under the [Model_Spec] keyword.  They work the
> > > > > same but now have typ, min, and max values.
> > > >
> > > > Not good enough.  Vref and Vtt are related to Vddq, but there are both
> > > > tolerances and noise terms involved which don't track the simplistic
> > > > typ/min/max axis.  In particular, for the devices Mr. Nolan is discussing,
> > > > the common-mode rejection of the receivers is an issue.  Differential is
> > > > a must.
> > > >
> > > > For instance, right now there is a JC-42.3 task group dealing with the
> > > > impact of SSI noise on Vref.  Crosstalk analysis where is can make or
> > > > break standard technology.
> > > >
> > > > > The IBIS committee is still working on the AC thresholds vs. DC thresholds
> > > > > problem.
> > > >
> > > > One of the reasons that Mr. Nolan now represents TI on the IBIS committee.
> > > >
> > > > --
> > > > D. C. Sessions
> > > > dc.sessions@vlsi.com
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com
From owner-ibis  Thu Mar 23 08:47:35 2000
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Date: Thu, 23 Mar 2000 10:46:03 -0600
From: Matt Callicoat <mlcallic@us.ibm.com>
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I'm a little confused about the definitions of min, typ, and max in the
ibis specifications.  In some cases, it seems to simply mean the
smallest, middle, and greatest numerical values, respectively.  But in
other cases it seems to refer to slow, typical, and fast, respectively.
For a CMOS circuit, I believe the convention is as follows:

Organized by process,

-----------  -SLOW- -TYP-- -FAST-
C_comp        max    typ    min
Temperature   min    typ    max
Voltage       min    typ    max
IV Curves     min    typ    max
VT Curves     min    typ    max

Organized by numerical comparison,

-----------  SMALL   TYP   LARGE
C_comp        min    typ    max
Temperature   max    typ    min
Voltage       min    typ    max
IV Curves     min    typ    max
VT Curves     min    typ    max

Neither way of looking at the organization of the data into min, typ and
max seems to be consistent.  What exactly are the rules governing the
assignment of min, typ and max?

From owner-ibis  Thu Mar 23 09:49:25 2000
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To: Matt Callicoat <mlcallic@us.ibm.com>, ibis-users@eda.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: min typ & max, explained (I hope)
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Hi Matt,

At 10:46 AM 3/23/00 -0600, Matt Callicoat wrote:
>I'm a little confused about the definitions of min, typ, and max in the
>ibis specifications.  In some cases, it seems to simply mean the
>smallest, middle, and greatest numerical values, respectively.  But in
>other cases it seems to refer to slow, typical, and fast, respectively.
>For a CMOS circuit, I believe the convention is as follows:

Min typ and max are used consistently in IBIS as refering to the
parameter they describe.  For example: C_comp min,typ,max are the
min,typ,max manufacturing tolerance values that describe C_comp.

For the purposes of choosing a SLOW or FAST process the choice of
which min's and max's to use together is not specified by IBIS.  It is
the responsibility of the user together with the simulator to select
the choice of combinations that would say describe the slowest or fastest
output edge rate.

There have been a few discussions in the past about specifying which
combinations are to be used for some of the corners but we could not
agree about how many corners there should be or what parameters they
should be.  We ultimately decided to leave this to the simulators and
end users.

best wishes..
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli 
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Thu Mar 23 10:58:17 2000
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From: "Weston Beal" <weston_beal@mentorg.com>
To: <ibis-users@eda.org>
Subject: RE: min typ & max, explained (I hope)
Date: Thu, 23 Mar 2000 10:59:34 -0800
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Matt and Kellee,

typ, min, and max refer to the manufacturing tolerance as Kellee stated
except in the case of temperature.  Since temperature has opposite effects
in CMOS and TTL, we can not just specify the min and max temperature.  The
min temperature is the temperature at which the min IV (and VT) curves are
measured.  The same applies to max temperature with max curves. This is
stated in the IBIS specification, I believe.  All the other parameters are
specified by numerical min and max.

Regards,
Weston


-----Original Message-----
From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
Sent: Thursday, March 23, 2000 9:48 AM
To: Matt Callicoat; ibis-users@eda.org
Subject: Re: min typ & max, explained (I hope)


Hi Matt,

At 10:46 AM 3/23/00 -0600, Matt Callicoat wrote:
>I'm a little confused about the definitions of min, typ, and max in the
>ibis specifications.  In some cases, it seems to simply mean the
>smallest, middle, and greatest numerical values, respectively.  But in
>other cases it seems to refer to slow, typical, and fast, respectively.
>For a CMOS circuit, I believe the convention is as follows:

Min typ and max are used consistently in IBIS as refering to the
parameter they describe.  For example: C_comp min,typ,max are the
min,typ,max manufacturing tolerance values that describe C_comp.

For the purposes of choosing a SLOW or FAST process the choice of
which min's and max's to use together is not specified by IBIS.  It is
the responsibility of the user together with the simulator to select
the choice of combinations that would say describe the slowest or fastest
output edge rate.

There have been a few discussions in the past about specifying which
combinations are to be used for some of the corners but we could not
agree about how many corners there should be or what parameters they
should be.  We ultimately decided to leave this to the simulators and
end users.

best wishes..
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Thu Mar 23 12:29:26 2000
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: min typ & max, explained (I hope)
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Hello All:

  Which parameters have their min, typ and max values listed
according to absolute value and and those that have their values
listed by operating corner is detailed in the IBIS cookbook, section
4.  The cookbook can be found at:

 http://www.eia.org/eig/ibis/ibis.htm

click on the 'spec' link.

 Regards,
 Stephen Peters
 Intel Corp.


-----Original Message-----
From: Weston Beal [mailto:weston_beal@mentorg.com]
Sent: Thursday, March 23, 2000 11:00 AM
To: ibis-users@eda.org
Subject: RE: min typ & max, explained (I hope)


Matt and Kellee,

typ, min, and max refer to the manufacturing tolerance as Kellee stated
except in the case of temperature.  Since temperature has opposite effects
in CMOS and TTL, we can not just specify the min and max temperature.  The
min temperature is the temperature at which the min IV (and VT) curves are
measured.  The same applies to max temperature with max curves. This is
stated in the IBIS specification, I believe.  All the other parameters are
specified by numerical min and max.

Regards,
Weston


-----Original Message-----
From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
Sent: Thursday, March 23, 2000 9:48 AM
To: Matt Callicoat; ibis-users@eda.org
Subject: Re: min typ & max, explained (I hope)


Hi Matt,

At 10:46 AM 3/23/00 -0600, Matt Callicoat wrote:
>I'm a little confused about the definitions of min, typ, and max in the
>ibis specifications.  In some cases, it seems to simply mean the
>smallest, middle, and greatest numerical values, respectively.  But in
>other cases it seems to refer to slow, typical, and fast, respectively.
>For a CMOS circuit, I believe the convention is as follows:

Min typ and max are used consistently in IBIS as refering to the
parameter they describe.  For example: C_comp min,typ,max are the
min,typ,max manufacturing tolerance values that describe C_comp.

For the purposes of choosing a SLOW or FAST process the choice of
which min's and max's to use together is not specified by IBIS.  It is
the responsibility of the user together with the simulator to select
the choice of combinations that would say describe the slowest or fastest
output edge rate.

There have been a few discussions in the past about specifying which
combinations are to be used for some of the corners but we could not
agree about how many corners there should be or what parameters they
should be.  We ultimately decided to leave this to the simulators and
end users.

best wishes..
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------


From owner-ibis  Thu Mar 23 13:18:12 2000
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From: "Weston Beal" <weston_beal@mentorg.com>
To: "'Peters, Stephen'" <stephen.peters@intel.com>, <ibis-users@eda.org>
Subject: RE: min typ & max, explained for good.
Date: Thu, 23 Mar 2000 13:19:29 -0800
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All,

Final word. From the IBIS 3.2 specification:

"| The optional [Temperature Range] keyword will contain the temperature
which
| causes or amplifies the slow, weak conditions in the "min" column and the
| temperature which causes or amplifies the fast, strong conditions in the
| "max" column. Therefore, the "min" column for [Temperature Range] will
| contain the lowest value for bipolar models (TTL and ECL) and the highest
| value for CMOS models. Default values described later are assumed if
| temperature is not specified.
|
| The "min" and "max" columns for all remaining keywords and subparameters
| will contain the smallest and largest magnitude values. This applies to
the
| [Model] subparameter C_comp as well even if the correlation to the
voltage,
| temperature, and process variations are known because information about
such
| correlation is not available in all cases."
  - section 9, pg. 76


Regards,
Weston



-----Original Message-----
From: Peters, Stephen [mailto:stephen.peters@intel.com]
Sent: Thursday, March 23, 2000 12:28 PM
To: 'ibis-users@eda.org'
Subject: RE: min typ & max, explained (I hope)



Hello All:

  Which parameters have their min, typ and max values listed
according to absolute value and and those that have their values
listed by operating corner is detailed in the IBIS cookbook, section
4.  The cookbook can be found at:

 http://www.eia.org/eig/ibis/ibis.htm

click on the 'spec' link.

 Regards,
 Stephen Peters
 Intel Corp.


-----Original Message-----
From: Weston Beal [mailto:weston_beal@mentorg.com]
Sent: Thursday, March 23, 2000 11:00 AM
To: ibis-users@eda.org
Subject: RE: min typ & max, explained (I hope)


Matt and Kellee,

typ, min, and max refer to the manufacturing tolerance as Kellee stated
except in the case of temperature.  Since temperature has opposite effects
in CMOS and TTL, we can not just specify the min and max temperature.  The
min temperature is the temperature at which the min IV (and VT) curves are
measured.  The same applies