From owner-ibis  Wed Jan  5 10:32:36 2000
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Message-ID: <38738DE8.5BD9C09@ti.com>
Date: Wed, 05 Jan 2000 12:31:04 -0600
From: Stephen Nolan <s-nolan1@ti.com>
Organization: Texas Instruments Incorporated
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I've been reading the draft version of the "IBIS FORUM I/O BUFFER MODELING
COOKBOOK - Revision 2.0X (under development)"

In the section entitled "Making Pullup and Power Clamp Sweeps Vcc Relative" it
states that you should make your three sweeps Vcc relative. Example: min=-3.6 to
6.3, typ=-3.3 to 6.6, and max=-3.0 to 6.9.

In this case, there would be table data created for the min column from -3.6 to
-3.3 where no typ data exists. Also, there would be data in the max column from
6.6 to 6.9 where no typ data exists. In those ranges, the typ column would have
to include NAs. Is this legal?

The IBIS spec (Version 3.2) says:
"NA" can be used for currents in the typical column, but numeric values MUST be
specified for the first and last voltage points on any I-V table.

As I read this, the typ table would have NA values for both the first and last
voltage points on the I-V table, by following this method.

And the example given in the IBIS spec ranges ONLY from -5 to 10 V and does not
include the additional data suggested by the "Making Pullup and Power Clamp
Sweeps Vcc Relative" section of the Cookbook.

Thanks.
-- 
Regards,
Stephen M. Nolan
From owner-ibis  Wed Jan  5 11:32:03 2000
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Reply-To: <rpryor@nortelnetworks.com>
From: "Ross Pryor" <rpryor@nortelnetworks.com>
To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
Subject: RE: IBIS model creation
Date: Wed, 5 Jan 2000 14:33:28 -0500
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Stephen,

The data are tabulated after the vcc-relative calculation, vtable=vcc-vout. After the calculation, the data have the same range.
For a pullup curve, the following table may help:

			(vout)		(vtable)
			sweep			vcc-relative
corner	vcc	range			range
------	---	-----			-------------
min		3.0	-3.6 > 6.3		6.6 > -3.3
typ		3.3	-3.3 > 6.6		6.6 > -3.3
max		3.6	-3.0 > 6.9		6.6 > -3.3

Regards,
Ross
--------------
Ross Pryor
Nortel Networks
Billerica, MA
(978) 288-3811
ESN 248-3811
rpryor@nortelnetworks.com

-----Original Message-----
From: Stephen Nolan [mailto:s-nolan1@ti.com]
Sent: Wednesday, January 05, 2000 1:31 PM
To: ibis-users@eda.org
Subject: IBIS model creation


I've been reading the draft version of the "IBIS FORUM I/O BUFFER MODELING
COOKBOOK - Revision 2.0X (under development)"

In the section entitled "Making Pullup and Power Clamp Sweeps Vcc Relative" it
states that you should make your three sweeps Vcc relative. Example: min=-3.6 to
6.3, typ=-3.3 to 6.6, and max=-3.0 to 6.9.

In this case, there would be table data created for the min column from -3.6 to
-3.3 where no typ data exists. Also, there would be data in the max column from
6.6 to 6.9 where no typ data exists. In those ranges, the typ column would have
to include NAs. Is this legal?

The IBIS spec (Version 3.2) says:
"NA" can be used for currents in the typical column, but numeric values MUST be
specified for the first and last voltage points on any I-V table.

As I read this, the typ table would have NA values for both the first and last
voltage points on the I-V table, by following this method.

And the example given in the IBIS spec ranges ONLY from -5 to 10 V and does not
include the additional data suggested by the "Making Pullup and Power Clamp
Sweeps Vcc Relative" section of the Cookbook.

Thanks.
--
Regards,
Stephen M. Nolan

From owner-ibis  Wed Jan  5 11:33:20 2000
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Date: Wed, 05 Jan 2000 11:32:26 -0800
To: Stephen Nolan <s-nolan1@ti.com>, ibis-users@eda.org
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: IBIS model creation a few comments...
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At 12:31 PM 1/5/00 -0600, Stephen Nolan wrote:
>In the section entitled "Making Pullup and Power Clamp Sweeps Vcc
Relative" it
>states that you should make your three sweeps Vcc relative. Example:
min=-3.6 to
>6.3, typ=-3.3 to 6.6, and max=-3.0 to 6.9.
>
>In this case, there would be table data created for the min column from
-3.6 to
>-3.3 where no typ data exists. Also, there would be data in the max column
from
>6.6 to 6.9 where no typ data exists. In those ranges, the typ column would
have
>to include NAs. Is this legal?
Yes; I believe it is legal.

However I suggest you make life simple and sweep them all from -3.6 to 6.9.
I don't see any reason not to and it eliminates the whole issue (KIS
principle).

best wishes..
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli 
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Wed Jan  5 12:12:35 2000
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Reply-To: <rpryor@nortelnetworks.com>
From: "Ross Pryor" <rpryor@nortelnetworks.com>
To: "'Kellee Crisafulli'" <kellee@hyperlynx.com>, <ibis-users@eda.org>
Subject: RE: IBIS model creation a few comments...
Date: Wed, 5 Jan 2000 15:13:14 -0500
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Yikes, that's not a good idea for pullup and power clamp curves.  What you suggest will make life much more difficult for the curves
which have to be made vcc-relative.

Sorry to be repetitive.  The data are tabulated after the vcc-relative calculation, vtable=vcc-vout. After the calculation, the data
have the same range.

For a pullup curve, the following table may help:

			(vout)		(vtable)
			sweep			vcc-relative
corner	vcc	range			range
------	---	-----			-------------
min		3.0	-3.6 > 6.3		6.6 > -3.3
typ		3.3	-3.3 > 6.6		6.6 > -3.3
max		3.6	-3.0 > 6.9		6.6 > -3.3

Regards,
Ross
-----Original Message-----
From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
Sent: Wednesday, January 05, 2000 2:32 PM
To: Stephen Nolan; ibis-users@eda.org
Subject: Re: IBIS model creation a few comments...



At 12:31 PM 1/5/00 -0600, Stephen Nolan wrote:
>In the section entitled "Making Pullup and Power Clamp Sweeps Vcc
Relative" it
>states that you should make your three sweeps Vcc relative. Example:
min=-3.6 to
>6.3, typ=-3.3 to 6.6, and max=-3.0 to 6.9.
>
>In this case, there would be table data created for the min column from
-3.6 to
>-3.3 where no typ data exists. Also, there would be data in the max column
from
>6.6 to 6.9 where no typ data exists. In those ranges, the typ column would
have
>to include NAs. Is this legal?
Yes; I believe it is legal.

However I suggest you make life simple and sweep them all from -3.6 to 6.9.
I don't see any reason not to and it eliminates the whole issue (KIS
principle).

best wishes..
Kellee

---------------------------------------------------------
Have a great day....
Kellee Crisafulli
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------


From owner-ibis  Wed Jan  5 12:27:23 2000
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To: <rpryor@nortelnetworks.com>, <ibis-users@eda.org>
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: RE: IBIS model creation a few comments...
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 ks.com>
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Hi Stephen, all

Oops.. Ross is correct.
my appologies...

best wishes..
Kellee


At 03:13 PM 1/5/00 -0500, Ross Pryor wrote:
>Yikes, that's not a good idea for pullup and power clamp curves.  What you
suggest will make life much more difficult for the curves
>which have to be made vcc-relative.
>
>Sorry to be repetitive.  The data are tabulated after the vcc-relative
calculation, vtable=vcc-vout. After the calculation, the data
>have the same range.
>
>For a pullup curve, the following table may help:
>
>			(vout)		(vtable)
>			sweep			vcc-relative
>corner	vcc	range			range
>------	---	-----			-------------
>min		3.0	-3.6 > 6.3		6.6 > -3.3
>typ		3.3	-3.3 > 6.6		6.6 > -3.3
>max		3.6	-3.0 > 6.9		6.6 > -3.3
>
>Regards,
>Ross
>-----Original Message-----
>From: Kellee Crisafulli [mailto:kellee@hyperlynx.com]
>Sent: Wednesday, January 05, 2000 2:32 PM
>To: Stephen Nolan; ibis-users@eda.org
>Subject: Re: IBIS model creation a few comments...
>
>
>
>At 12:31 PM 1/5/00 -0600, Stephen Nolan wrote:
>>In the section entitled "Making Pullup and Power Clamp Sweeps Vcc
>Relative" it
>>states that you should make your three sweeps Vcc relative. Example:
>min=-3.6 to
>>6.3, typ=-3.3 to 6.6, and max=-3.0 to 6.9.
>>
>>In this case, there would be table data created for the min column from
>-3.6 to
>>-3.3 where no typ data exists. Also, there would be data in the max column
>from
>>6.6 to 6.9 where no typ data exists. In those ranges, the typ column would
>have
>>to include NAs. Is this legal?
>Yes; I believe it is legal.
>
>However I suggest you make life simple and sweep them all from -3.6 to 6.9.
>I don't see any reason not to and it eliminates the whole issue (KIS
>principle).
>
>best wishes..
>Kellee
>
>---------------------------------------------------------
>Have a great day....
>Kellee Crisafulli
>HyperLynx, a division of Pads Software Inc.
>SI,EMC,X-talk and IBIS tools for the Windows platform
>E-mail: <mailto:kellee@hyperlynx.com>
>web:    <http://www.hyperlynx.com>
>---------------------------------------------------------
> 
---------------------------------------------------------
Have a great day....
Kellee Crisafulli 
HyperLynx, a division of Pads Software Inc.
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Thu Jan  6 10:52:07 2000
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To: ibis-users@eda.org
Subject: RE: IBIS model creation
X-Sun-Charset: US-ASCII



Happy new year IBISians,

It's kind of silly but I can not reproduce arithmetics
from the attached email. Here is mine:


        Vcc     Vout                  Vtable

min     3.0     from -3.0 to 6.0      from 6.0 to -3.0


typ     3.3     from -3.3 to 6.6      from 6.6 to -3.3


max     3.6     from -3.6 to 7.2      from 7.2 to -3.6


Vcc is derived from range (denoted Vpower below)

Vout changes from ( Vground - Vpower ) to (Vpower + Vpower )
(see spec.)  e.g. from ( 0 - Vcc ) to 2*Vcc
             e.g. from -Vcc to 2*Vcc

Vtable = Vcc - Vout

Conclusion: spec is inconsistent in this part.

Nikolai Bannov
Hspice group
Avant! Corporation

:-) From owner-ibis@server.eda.org Wed Jan  5 12:36 PST 2000
:-) From: "Ross Pryor" <rpryor@nortelnetworks.com>
:-) To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
:-) Subject: RE: IBIS model creation
:-) Date: Wed, 5 Jan 2000 14:33:28 -0500
:-) MIME-Version: 1.0
:-) Content-Transfer-Encoding: 7bit
:-) X-Priority: 3 (Normal)
:-) X-MSMail-Priority: Normal
:-) Importance: Normal
:-) X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2120.0
:-) 
:-) Stephen,
:-) 
:-) The data are tabulated after the vcc-relative calculation, vtable=vcc-vout. After the calculation, the data have the same range.
:-) For a pullup curve, the following table may help:
:-) 
:-) 			(vout)		(vtable)
:-) 			sweep			vcc-relative
:-) corner	vcc	range			range
:-) ------	---	-----			-------------
:-) min		3.0	-3.6 > 6.3		6.6 > -3.3
:-) typ		3.3	-3.3 > 6.6		6.6 > -3.3
:-) max		3.6	-3.0 > 6.9		6.6 > -3.3
:-) 
:-) Regards,
:-) Ross
:-) --------------
:-) Ross Pryor
:-) Nortel Networks
:-) Billerica, MA
:-) (978) 288-3811
:-) ESN 248-3811
:-) rpryor@nortelnetworks.com
:-) 


From owner-ibis  Thu Jan  6 11:44:21 2000
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From: "Ruston, Matt" <mruston@lucent.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: FW: cPCI generic 5V Ibis Models
Date: Thu, 6 Jan 2000 14:42:37 -0500 
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Sent to ibis-users instead of just ibis distribution:

> -----Original Message-----
> From:	Ruston, Matt 
> Sent:	Thursday, January 06, 2000 11:00 AM
> To:	'ibis@eda.org'
> Subject:	cPCI generic 5V Ibis Models
> 
> All:
> 
>  Hi. I'm trying to do 5V Compact PCI sims and am in need of strong and
> weak models. In the cPCI draft spec (PICMG 2.0 D3.0) dated July 21, 1999,
> there is reference in Appendix A (Pg 79) to models and they plot the I-V
> curves referenced to the min-max specs. Does anyone have these models
> (either Ibis or Spice) and can they forward them to me? If not, does
> anyone have anything that is close to covering the full range of the cPCI
> 5V signaling specs?
> 
> Thanks in advance...
> 
> 
> Matt
> 
>                                   Matt Ruston  (mruston@lucent.com)
>                                   Lucent Technologies CNS
>                                   Voice: (508) 486-2188
>                                   Fax:    (508) 486-2126
> 
> 
From owner-ibis  Thu Jan  6 11:44:48 2000
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Reply-To: <rpryor@nortelnetworks.com>
From: "Ross Pryor" <rpryor@nortelnetworks.com>
To: <nikolai@avanticorp.com>, <ibis-users@eda.org>
Subject: RE: IBIS model creation
Date: Thu, 6 Jan 2000 14:44:57 -0500
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Well, the arithmetic in my table is correct.  Note that the Max and Min rows do not use a vout sweep range of exactly -vcc to 2*vcc.
Instead, they use a range that is adjusted to make the vcc-relative data (vtable) line up.  That makes the post-processing of the
data much easier, and I suspect that's why the s2ibis2 author(s) implemented it this way.

In your table, you are using exactly -vcc to 2*vcc for the min and max rows.  As you note, the vcc-relative (vtable) data then do
not cover the same range.

In a quick search, I can't find where the voltage range is explicitly defined in the spec.  Can you provide a pointer?

Regards,
Ross
-----Original Message-----
From: nikolai@avanticorp.com [mailto:nikolai@avanticorp.com]
Sent: Thursday, January 06, 2000 1:51 PM
To: ibis-users@eda.org
Subject: RE: IBIS model creation




Happy new year IBISians,

It's kind of silly but I can not reproduce arithmetics
from the attached email. Here is mine:


        Vcc     Vout                  Vtable

min     3.0     from -3.0 to 6.0      from 6.0 to -3.0


typ     3.3     from -3.3 to 6.6      from 6.6 to -3.3


max     3.6     from -3.6 to 7.2      from 7.2 to -3.6


Vcc is derived from range (denoted Vpower below)

Vout changes from ( Vground - Vpower ) to (Vpower + Vpower )
(see spec.)  e.g. from ( 0 - Vcc ) to 2*Vcc
             e.g. from -Vcc to 2*Vcc

Vtable = Vcc - Vout

Conclusion: spec is inconsistent in this part.

Nikolai Bannov
Hspice group
Avant! Corporation

:-) From owner-ibis@server.eda.org Wed Jan  5 12:36 PST 2000
:-) From: "Ross Pryor" <rpryor@nortelnetworks.com>
:-) To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
:-) Subject: RE: IBIS model creation
:-) Date: Wed, 5 Jan 2000 14:33:28 -0500
:-) MIME-Version: 1.0
:-) Content-Transfer-Encoding: 7bit
:-) X-Priority: 3 (Normal)
:-) X-MSMail-Priority: Normal
:-) Importance: Normal
:-) X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2120.0
:-)
:-) Stephen,
:-)
:-) The data are tabulated after the vcc-relative calculation, vtable=vcc-vout. After the calculation, the data have the same range.
:-) For a pullup curve, the following table may help:
:-)
:-) 			(vout)		(vtable)
:-) 			sweep			vcc-relative
:-) corner	vcc	range			range
:-) ------	---	-----			-------------
:-) min		3.0	-3.6 > 6.3		6.6 > -3.3
:-) typ		3.3	-3.3 > 6.6		6.6 > -3.3
:-) max		3.6	-3.0 > 6.9		6.6 > -3.3
:-)
:-) Regards,
:-) Ross
:-) --------------
:-) Ross Pryor
:-) Nortel Networks
:-) Billerica, MA
:-) (978) 288-3811
:-) ESN 248-3811
:-) rpryor@nortelnetworks.com
:-)



From owner-ibis  Thu Jan  6 12:32:35 2000
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To: nikolai@avanticorp.com
cc: ibis-users@eda.org
Subject: Re: IBIS model creation 
In-reply-to: Your message of "Thu, 06 Jan 2000 10:51:00 PST."
             <200001061851.KAA03486@av20121.svd.avanticorp.com> 
Mime-Version: 1.0
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Date: Thu, 06 Jan 2000 12:10:51 -0800
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello Nick:

  Take a look at your Vout data.  -3.0 to 6.0 is the sweep range 
for the 'max' (Vcc = 3.6v) case but you are applying it to the 'min'
(Vcc = 3.0v) row.   Likewise for the max row.

  Regards,
  Stephen Peters
  Intel Corp.


> 
> 
> Happy new year IBISians,
> 
> It's kind of silly but I can not reproduce arithmetics
> from the attached email. Here is mine:
> 
> 
>         Vcc     Vout                  Vtable
> 
> min     3.0     from -3.0 to 6.0      from 6.0 to -3.0
> 
> 
> typ     3.3     from -3.3 to 6.6      from 6.6 to -3.3
> 
> 
> max     3.6     from -3.6 to 7.2      from 7.2 to -3.6
> 
> 
> Vcc is derived from range (denoted Vpower below)
> 
> Vout changes from ( Vground - Vpower ) to (Vpower + Vpower )
> (see spec.)  e.g. from ( 0 - Vcc ) to 2*Vcc
>              e.g. from -Vcc to 2*Vcc
> 
> Vtable = Vcc - Vout
> 
> Conclusion: spec is inconsistent in this part.
> 
> Nikolai Bannov
> Hspice group
> Avant! Corporation
> 
> :-) From owner-ibis@server.eda.org Wed Jan  5 12:36 PST 2000
> :-) From: "Ross Pryor" <rpryor@nortelnetworks.com>
> :-) To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
> :-) Subject: RE: IBIS model creation
> :-) Date: Wed, 5 Jan 2000 14:33:28 -0500
> :-) MIME-Version: 1.0
> :-) Content-Transfer-Encoding: 7bit
> :-) X-Priority: 3 (Normal)
> :-) X-MSMail-Priority: Normal
> :-) Importance: Normal
> :-) X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2120.0
> :-) 
> :-) Stephen,
> :-) 
> :-) The data are tabulated after the vcc-relative calculation, vtable=vcc-vout. After the calculation, the data have the same range.
> :-) For a pullup curve, the following table may help:
> :-) 
> :-) 			(vout)		(vtable)
> :-) 			sweep			vcc-relative
> :-) corner	vcc	range			range
> :-) ------	---	-----			-------------
> :-) min		3.0	-3.6 > 6.3		6.6 > -3.3
> :-) typ		3.3	-3.3 > 6.6		6.6 > -3.3
> :-) max		3.6	-3.0 > 6.9		6.6 > -3.3
> :-) 
> :-) Regards,
> :-) Ross
> :-) --------------
> :-) Ross Pryor
> :-) Nortel Networks
> :-) Billerica, MA
> :-) (978) 288-3811
> :-) ESN 248-3811
> :-) rpryor@nortelnetworks.com
> :-) 
> 


From owner-ibis  Thu Jan  6 12:36:12 2000
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: IBIS model creation
Date: Thu, 6 Jan 2000 12:35:14 -0800 
MIME-Version: 1.0
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The problem with the IBIS spec is that it does not say that the ranges
should be calculated based on the typical Vcc values.  So keeping that
in mind here is an example (for a 5V device with 5% tolerance) that works.

IV curve range for pullup:
On the high end:

 GND_rel_typ = Vcc_typ - -Vcc_typ
  10.00      =  5.00   - -5.00
 GND_rel_min = Vcc_min - -Vcc_typ
   9.75      =  4.75   - -5.00
 GND_rel_max = Vcc_max - -Vcc_typ
  10.25      =  5.25   - -5.00

On the low end:

 GND_rel_typ = Vcc_typ - 2*Vcc_typ
  -5.00      =  5.00   - 10.00
 GND_rel_min = Vcc_min - 2*Vcc_typ
  -5.25      =  4.75   - 10.00
 GND_rel_max = Vcc_max - 2*Vcc_typ
  -4.75      =  5.25   - 10.00

Notice that the range for the sweep is -Vcc(typ) to 2*Vcc(typ) for each
case with respect to the typ., min., and max. Vcc voltage.  The problem
is when people want to make the range -Vcc(min) to 2*Vcc(min) and
-Vcc(max) to 2*Vcc(max) for the min and max cases, respectively.  Doing
that will result in different lengths for the three columns which is not
allowed in the IBIS spec.

I hope this helps clarifying the issue.

Arpad Muranyi
Intel Corporation
=======================================================================


-----Original Message-----
From: Ross Pryor [mailto:rpryor@nortelnetworks.com]
Sent: Thursday, January 06, 2000 11:45 AM
To: nikolai@avanticorp.com; ibis-users@eda.org
Subject: RE: IBIS model creation


Well, the arithmetic in my table is correct.  Note that the Max and Min rows
do not use a vout sweep range of exactly -vcc to 2*vcc.
Instead, they use a range that is adjusted to make the vcc-relative data
(vtable) line up.  That makes the post-processing of the
data much easier, and I suspect that's why the s2ibis2 author(s) implemented
it this way.

In your table, you are using exactly -vcc to 2*vcc for the min and max rows.
As you note, the vcc-relative (vtable) data then do
not cover the same range.

In a quick search, I can't find where the voltage range is explicitly
defined in the spec.  Can you provide a pointer?

Regards,
Ross
-----Original Message-----
From: nikolai@avanticorp.com [mailto:nikolai@avanticorp.com]
Sent: Thursday, January 06, 2000 1:51 PM
To: ibis-users@eda.org
Subject: RE: IBIS model creation




Happy new year IBISians,

It's kind of silly but I can not reproduce arithmetics
from the attached email. Here is mine:


        Vcc     Vout                  Vtable

min     3.0     from -3.0 to 6.0      from 6.0 to -3.0


typ     3.3     from -3.3 to 6.6      from 6.6 to -3.3


max     3.6     from -3.6 to 7.2      from 7.2 to -3.6


Vcc is derived from range (denoted Vpower below)

Vout changes from ( Vground - Vpower ) to (Vpower + Vpower )
(see spec.)  e.g. from ( 0 - Vcc ) to 2*Vcc
             e.g. from -Vcc to 2*Vcc

Vtable = Vcc - Vout

Conclusion: spec is inconsistent in this part.

Nikolai Bannov
Hspice group
Avant! Corporation

:-) From owner-ibis@server.eda.org Wed Jan  5 12:36 PST 2000
:-) From: "Ross Pryor" <rpryor@nortelnetworks.com>
:-) To: "'Stephen Nolan'" <s-nolan1@ti.com>, <ibis-users@eda.org>
:-) Subject: RE: IBIS model creation
:-) Date: Wed, 5 Jan 2000 14:33:28 -0500
:-) MIME-Version: 1.0
:-) Content-Transfer-Encoding: 7bit
:-) X-Priority: 3 (Normal)
:-) X-MSMail-Priority: Normal
:-) Importance: Normal
:-) X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2120.0
:-)
:-) Stephen,
:-)
:-) The data are tabulated after the vcc-relative calculation,
vtable=vcc-vout. After the calculation, the data have the same range.
:-) For a pullup curve, the following table may help:
:-)
:-) 			(vout)		(vtable)
:-) 			sweep			vcc-relative
:-) corner	vcc	range			range
:-) ------	---	-----			-------------
:-) min		3.0	-3.6 > 6.3		6.6 > -3.3
:-) typ		3.3	-3.3 > 6.6		6.6 > -3.3
:-) max		3.6	-3.0 > 6.9		6.6 > -3.3
:-)
:-) Regards,
:-) Ross
:-) --------------
:-) Ross Pryor
:-) Nortel Networks
:-) Billerica, MA
:-) (978) 288-3811
:-) ESN 248-3811
:-) rpryor@nortelnetworks.com
:-)




From owner-ibis  Thu Jan  6 13:35:03 2000
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X-Mailer: exmh version 2.0delta 6/3/97
To: ibis@eda.org, ibis-users@eda.org
Subject: Bird 62.2 -- Enhanced Specification of Receiver Thresholds
Mime-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Date: Thu, 06 Jan 2000 13:13:20 -0800
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello All:

  Bird 62.2 includes a minor syntax correction.  For details, refer to the
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: section at the bottom.


  Regards,
  Stephen Peters
  Intel Corp.


============

                  Buffer Issue Resolution Document  (BIRD)
 
 BIRD ID#:      62.2
 ISSUE TITLE:   Enhanced Specification of Receiver Thresholds
 REQUESTOR:     DC Sessions (Philips), Stephen Peters, Richard Melitz,
                Arpad Muranyi (Intel Corp).
 DATE SUBMITTED:  Aug 24, 1999, Dec 28, 1999, Jan 6, 2000
 DATE ACCEPTED BY IBIS OPEN FORUM:
 
*******************************************************************************
*******************************************************************************
 
 STATEMENT OF THE ISSUE:  When specifying receiver input thresholds the current
 specification allows only the traditional DC derived Vinh and Vinl parameters.
 These two parameters are no longer adequate for describing receivers used for
 high speed designs.  This BIRD proposes four new input switching threshold
 parameters: Vinh_ac, Vinh_dc, Vinl_ac, Vinl_dc.  These parameters are
 referenced to an reference point Vth, and this reference is allowed to vary
 with variations in a supply.
 
*******************************************************************************
 
 STATEMENT OF THE RESOLVED SPECIFICATIONS:
 
 1) The following new keyword is defined and placed in the specification
 just below the [Model Spec] keyword.
 
|=============================================================================
|      Keyword: [Receiver Thresholds]
|     Required: No
|   Sub-Params: Vth, Vth_min, Vth_max, Vinh_ac, Vinh_dc, Vinl_ac, Vinl_dc,
|               Vth_sensitivity, Input_Ref_Supply
|  Description: The [Receiver Thresholds] keyword defines both a set of
|               receiver input thresholds as well as their sensitivity to
|               variations in a referenced supply.  The subparameters are
|               defined as follows:
|
|               Vth, Vth_min and Vth_max are the ideal input threshold voltage
|               at which the output of a digital logic receiver changes state.
|               Vth is the nominal input threshold voltage under the voltage,
|               temperature and process conditions that define 'typ'.  Vth_min
|               is the minimum input threshold voltage at 'typ' conditions
|               while Vth_max is the maximum input threshold voltage at 'typ'
|               conditions.
|
|               Vinh_ac is the voltage that a low-to-high going input waveform
|               must reach in order to guarantee that the receiver's output
|               has changed state.  In other words, reaching Vinh_ac is
|               sufficient to guarantee a receiver state change.  Vinh_ac is
|               expressed as an offset from Vth.
|
|               Vinh_dc is the voltage that an input waveform must remain
|               above (more positive than) in order to guarantee that a
|               receiver output will NOT change state.  Vinh_dc is expressed
|               as an offset from Vth.
|
|               Vinl_ac is the voltage that a high-to-low going input waveform
|               must reach in order to guarantee that the receiver's output
|               has changed state.  In other words, reaching Vinl_ac is
|               sufficient to guarantee a receiver state change.  Vinl_ac
|               is expressed as an offset from Vth.
|
|               Vinl_dc is the voltage that an input waveform must remain below
|               (more negative than) in order to guarantee that a receiver's
|               output will NOT change state.  Vinh_dc is expressed as a
|               offset from Vth.
|
|               Vth_sensitivity is a unitless number that specifies how Vth
|               varies with respect to the supply voltage defined by the
|               Input_Ref_Supply subparameter. Vth_sensitivity is defined
|               as:
|
|                                   change in input threshold voltage
|               Vth_sensitivity = ------------------------------------
|                                  change in referenced supply voltage
|
|               Vth_sensitivity must be entered as a whole number or
|               decimal, not as a fraction.
|
|               Input_Ref_Supply indicates which supply voltage Vth tracks;
|               i.e. it indicates which supply voltage change causes a change
|               in input threshold.  The legal arguments to this subparameter
|               are VOLTAGE_RANGE (the supply voltage defined by the
|               [Voltage Range] keyword), PULLUP_REF (the supply voltage
|               defined by the [Pullup Reference] keyword), or EXT (an
|               external voltage defined by the [External Reference] keyword).
|
|
| Usage Rules:  The [Receiver Thresholds] keyword is valid if the model type
|               includes any reference to input or I/O.  The Vinh_ac, Vinh_dc,
|               Vinl_ac, Vinh_dc and Vth subparameters are required and
|               override the Vinh, Vinl, Vinh+/- and Vinl+/- subparameters
|               declared under the [Model] or [Model Spec] keywords.  The
|               Vth_min, Vth_max, Vth_sensitivity and Input_Ref_Supply 
|               subparameters are optional.  However, if the Vth_sensitivity
|               subparameter is present then the Input_Ref_Supply 
|               subparameter must also be present.
|
|               Subparameter Usage Rules:
|               Numerical arguments are separated from their associated
|               subparameter by an equals sign (=); white space around the
|               equals sign is optional.  The argument to the
|               Input_Ref_Supply subparameter is separated from the 
|               subparameter by white space.
|
|               Vth at Minimum or Maximum Operating Conditions:
|               As described above, the Vth_min and Vth_max subparameters
|               define the minimum and maximum input threshold values under
|               typical operating conditions.  There is no provision for
|               directly specifying Vth under minimum or maximum operating
|               conditions.  Instead, these values are calculated using
|               the following equation:
|
|      Vth(min/max) = Vth* + [(Vth_sensitivity) X (change in supply voltage)]
|
|               where Vth* is either Vth, Vth_min or Vth_max as appropriate,
|               and the supply voltage is the one indicated by the
|               Input_Ref_Supply subparameter.
|
|
|               Differential Receivers:
|               For a single ended receiver the numerical values of Vth,
|               Vth_min and Vth_max are specified with respect to 0v.
|               However, if the [Receiver Threshold] keyword is describing
|               a differential receiver (i.e. is part of a [Model] statement
|               that describes a pin listed in the [Diff Pin] keyword), then
|               Vth is typically assigned a value of zero volts and the 
|               Vth_min and Vth_max parameters are not used.  The values of 
|               Vinh_* and Vinl_* subparameters are still given as an
|               offset from Vth and become, in effect, the more traditional 
|               Vdiff.
|
| Examples:
|
| A basic 3.3v single ended receiver using only the required
| subparameters
|
Vth = 1.5v
Vinh_ac = +225mV
Vinh_dc = +100mV
Vinl_ac = -225mV
Vinl_dc = -100mV
|
|
| A single ended receiver using an external threshold reference.  In this
| case the input threshold is the external reference voltage so
| Vth_sensitivity equals 1.
|
Vth = 1.0v
Vth_sensitivity = 1
Input_Ref_Supply EXT
Vinh_ac = +200mV
Vinh_dc = +100mV
Vinl_ac = -200mV
Vinl_dc = -100mV
|
|
| A fully specified single ended 3.3v CMOS receiver
|
Vth = 1.5v
Vth_min = 1.45v
Vth_max = 1.53v
Vth_sensitivity = 0.45
Input_Ref_Supply VOLTAGE_RANGE
Vinh_ac = +200mV
Vinh_dc = +100mV
Vinl_ac = -200mV
Vinl_dc = -100mV
|
|
| A differential receiver
|
Vth = 0.0v
Vinh_ac = +50mV
Vinh_dc = +25mV
Vinl_ac = -50mV
Vinl_dc = -25mV

2) The following new keyword is defined and place in the specification
following the [GND Clamp Reference] keyword
|=============================================================================
|      Keyword: [External Reference]
|     Required: Yes, if a receiver's input threshold is determined by an
|               external reference voltage
|  Description: Defines a voltage source that supplies the reference voltage
|               used by a receiver for its input threshold reference.
|  Usage Notes: Provide actual voltages (not percentages in the typ, min max
|               format.  "NA" is allowed for the min and max values only.
|-----------------------------------------------------------------------------
| variable              typ          min           max
[External Reference]    1.0v         0.95v        1.05v

3)  Under section 2 of General Syntax Rules and Guidelines the following
words are added to the list of reserved words.

EXT   -  A reference to a voltage defined by the [External Reference] Keyword
VOLTAGE_RANGE - A reference to a voltage defined by the [Voltage Range] keyword
PULLUP_REFERENCE - A reference to a voltage defined by the [Pullup
Reference] keyword

******************************************************************************
 
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:  This proposal follows the
recommendations of the JC-15 committee for specifying SDRAM inputs.

Update for 62.1:
  Specified exactly which [Model] and [Model Spec] parameters are
overridden by [Receiver Threshold] and changed the wording of the
"Differential Receivers:"  to indicate that the numerical 
value of Vth is *typically* assigned a value of 0v rather than 
*must* be assigned a value of zero.

Update for 62.2
  Under Usage Rules: added the section (Subparameter Usage Rules:)
describing the syntax rules for seperating arguments from subparameters.
Updated examples with this change.
 
******************************************************************************

ANY OTHER BACKGROUND INFORMATION: This BIRD is a direct result of a
request by the JEDEC JC-15 committee to the IBIS Open Forum to provide better
specification of receivers.  The basic form of this bird was discussed at
a meeting in July 1999 between DC Sessions of Phillips Corp. and Stephen
Peters, Richard Melitz and Aprad Muranyi of Intel Corp.

 
*******************************************************************************






From owner-ibis  Thu Jan  6 13:38:45 2000
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Subject: Bird 63.2 -- Documentation of Receiver Setup and Hold Timing 
 Conditions
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From: Stephen Peters <sjpeters@ichips.intel.com>


Hello All:

  Bird 63 is reissued as Bird 63.2 to correct a syntax usage error.  For
details, refer to the ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: section
at the bottom.

  Regards,
  Stephen Peters
  Intel Corp.

=============

                Buffer Issue Resolution Document  (BIRD)

BIRD ID#:     63.3
ISSUE TITLE:  Documentation of Receiver Setup and Hold Timing Conditions
REQUESTOR:    D.C. Sessions (Philips), Stephen Peters, Richard Melitz,
              Arpad Muranyi (Intel Corp.)
DATE SUBMITTED:  Sept 8, 1999, Dec 27, 1999, Jan 6, 2000
DATE ACCEPTED BY IBIS OPEN FORUM:

*******************************************************************************
*******************************************************************************

STATEMENT OF THE ISSUE:  Currently, the edge rate and overdrive conditions
under which a receiver's data book setup and hold timings are specified are
not documented.  This bird provides a way for the model creator to document
those conditions in an IBIS file.

*******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

1) The following new keyword is defined and placed in the specification
just below the [Receiver Threshold] keyword.

|=============================================================================
|      Keyword: [Tester Spec]
|     Required: No
|   Sub-Params: Tester_Vlow, Tester_Vhigh, Tester_Vth, Tester_Slew_Setup,
|               Tester_Slew_Hold
|  Description: The [Tester Spec] keyword documents the input overdrive
|               and tester slew rate conditions under which a device's
|               input setup and hold times are specified.  The subparameters
|               are defined as follows:
|
|               Tester_Vth is the point on the input waveform from 
|               which an receivers setup and hold time is referenced.  It is
|               usually the input voltage at which the output of a digital
|               logic receiver changes state.  Tester_Vth is used as the
|               reference voltage for the Tester_Vlow and Tester_Vhigh
|               parameters.
|
|               Tester_Vlow represents the starting voltage of the low-to-high
|               going waveform a tester uses when characterizing a receiver's
|               setup or hold time. It also represents the ending voltage of a
|               high-to-low going waveform.  Tester_Vlow is expressed as an
|               offset from Tester_Vth.
|
|               Tester_Vhigh represents the ending voltage of the low-to-high
|               going waveform a tester uses when characterizing a receiver's
|               setup or hold time. It also represents the starting voltage of
|               a high-to-low going waveform.  Tester_Vhigh is expressed as an
|               offset from Tester_Vth.
|
|               Tester_Slew_Setup is the tester waveform's slew rate at
|               which a receiver's setup time is specified.  For purposes of
|               this keyword, slew rate is defined as:
|
|                               Tester_Vhigh - (Tester_Vlow)
|         Slew Rate  = -------------------------------------------
|                        Time it takes to swing the above voltage
|
|               Tester_Slew_Setup must be expressed as an explicit ratio 
|               of voltage over time, and not reduced to a decimal number.
|
|               Tester_Slew_Hold is the tester waveform's slew rate at which
|               a receiver's hold time is specified.  Slew rate is defined
|               as above.  Tester_Slew_Hold must be expressed as an explicit
|               ratio of voltage over time, and not reduced to a decimal
|               number.
|
|
| Usage Rules:  The [Tester Spec] keyword is valid if the model type
|               includes any reference to input or I/O.  All subparameters
|               are required to be present.  When entering a numeric value the
|               subparameter argument and the subparameter itself must
|               be separated by an equals sign (=).  The argument to the
|               Tester_Skew_* subparameter must be seperated from the
|               subparameter itself by a white space.
|
|               Differential Receivers:
|               For a single ended receiver the numerical value of
|               Tester_Vth is specified with respect to 0v.  However, if
|               the [Tester Spec] keyword is describing a differential receiver
|               (i.e. is part of a [Model] statement that describes a pin
|               listed in the [Diff Pin] keyword), then the numerical value of
|               Tester_Vth is typically given as 0v.  Tester_Vlow and 
|               Tester_Vhigh are then assumed to represent the difference in
|               voltage between one input and the other.
|
|
| A basic 3.3v single ended receiver
Tester_Vth   = 1.5v
Tester_Vlow  = -1.0v
Tester_Vhigh = 2.5v
Tester_Slew_setup 1v/ns
Tester_Slew_hold  1v/ns
|
| A differential receiver
Tester_Vth = 0V
Tester_Vlow = -200mV
Tester_Vhigh = +200mV
Tester_Slew_setup 1.2v/1ns
Tester_Slew_hold  1.2v/1ns
|
|
*******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:  Like it's companion BIRD #62,
this bird is an attempt to better specify and document a receiver's
functionality.  It follows the convention of the previous BIRDS in that
most of the parameter values are specified as an offset from a reference
voltage.  This technique supports both single ended and differential
receivers.

Note that there are separate slew rate entries for setup and hold time.  When
formulating this bird the authors were not sure if receiver hold time was
specified under different slew rate conditions than setup time.  Thus,
separate slew rate entries.  These two parameters can be collapsed into one
if further information indicates that this is not the case.

Updates for 63.1:
  Corrected "Tester_Skew" to "Tester_Slew" in the examples (typo
correction) and fixed up the Slew_rate equation by removing the
absolute value markers.  Changed Slew_rate so that it is expressed
as an explicit ratio and not as a decimal (following the convention of
[Ramp Rate]).  Clarified the meaning of Tester_Vth.  Finally, under 
"Differential Receivers:" changed the text to indicate that the numerical 
value of Tester_Vth is *typically* given as 0v rather than *must* be given 
as zero. 

Updates for 63.2:
  Syntax correction -- the argument to the Tester_Slew_* parameter should
be seperated from the subparameter by white space, not an equals sign 
(it's a non-numeric argument).  Corrected examples.

*******************************************************************************

ANY OTHER BACKGROUND INFORMATION: This BIRD is a direct result of a
request by the JEDEC JC-15 committee to the IBIS Open Forum to provide better
specification of receivers.  The basic form of this bird was discussed at
a meeting in July 1999 between DC Sessions of Phillips Corp. and Stephen
Peters, Richard Melitz and Aprad Muranyi of Intel Corp.

*******************************************************************************




From owner-ibis  Mon Jan 10 06:33:38 2000
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From: kraahemifar@interactiv.com
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Date: Mon, 10 Jan 2000 09:42:37 -0500
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Subject: A question
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Hello Sir:

I understand why IBIS models are needed. However, I am still trying to
understand how the simulation of IBIS models are performed. One way of doing it
is to convert IBIS models to structural models and use SPICE on them. I am
interested to see documents on the simulation of IBIS components.

Thanks a lot for your care and response.

Best Regards,

Kaamran


From owner-ibis  Mon Jan 10 15:48:00 2000
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Message-ID: <387A6F57.B72F5851@mentor.com>
Date: Mon, 10 Jan 2000 15:46:31 -0800
From: Bob Ross <bob_ross@mentorg.com>
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To: kraahemifar@interactiv.com
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Kaamran:

Here are a few links to uploaded documents that deal with some
simulation algorithms.  Other information may be available
from vendors directly.

Best Regards,
Bob Ross
Mentor Graphics

Papers:
http://www.sigrity.com/papers/ectc96/DOectc96ibis.htm
http://www.ntu.edu.sg/home/ehntan/glsvlsi.zip

Presentations:
http://www.eda.org/pub/ibis/summits/feb99/unger.zip
http://www.eda.org/pub/ibis/summits/feb98/unger.zip




kraahemifar@interactiv.com wrote:
> 
> Hello Sir:
> 
> I understand why IBIS models are needed. However, I am still trying to
> understand how the simulation of IBIS models are performed. One way of doing it
> is to convert IBIS models to structural models and use SPICE on them. I am
> interested to see documents on the simulation of IBIS components.
> 
> Thanks a lot for your care and response.
> 
> Best Regards,
> 
> Kaamran
From owner-ibis  Tue Jan 11 17:12:12 2000
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Date: Tue, 11 Jan 2000 17:10:45 -0800
From: Bob Ross <bob_ross@mentorg.com>
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To All:

This is for people on the IBIS lists who want to just visit
the exhibits for free.  Note the Exhibit dates should be
Tuesday, February 1 and Wednesday, February 2, 2000.

Bob Ross
Mentor Graphics
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Subject: Complimentary Exhibits and Demo Pass for DesignCon 2000
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<P class=MsoNormal>Title: ______________________________________________</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Company: __________________________________________</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Division: ___________________________________________</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
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<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
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<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>City, State, Zip: _____________________________________</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
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<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
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<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Return FAX THIS FORM TO: 312-559-4111</P>
<DIV 
style="BORDER-BOTTOM: windowtext 3pt dotted; BORDER-LEFT: medium none; BORDER-RIGHT: medium none; BORDER-TOP: medium none; PADDING-BOTTOM: 1pt; PADDING-LEFT: 0in; PADDING-RIGHT: 0in; PADDING-TOP: 0in">
<P class=MsoNormal 
style="BORDER-BOTTOM: medium none; BORDER-LEFT: medium none; BORDER-RIGHT: medium none; BORDER-TOP: medium none; PADDING-BOTTOM: 0in; PADDING-LEFT: 0in; PADDING-RIGHT: 0in; PADDING-TOP: 0in; mso-border-bottom-alt: dotted windowtext 3.0pt; mso-padding-alt: 0in 0in 1.0pt 0in"><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P></DIV>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Exhibits</P>
<P class=MsoNormal>The exhibits at DesignCon 2000 provide attendees with a 
firsthand look at the latest technologies and solutions available. More than 100 
companies will present their technologies and provide all of the solutions you 
need.</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Here are just some of the products you will find at the 
DesignCon exhibits and demonstrations:</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Applications Engineering </P>
<P class=MsoNormal>ASICs Components</P>
<P class=MsoNormal>Computer Software and Peripherals</P>
<P class=MsoNormal>Design Automation Tools</P>
<P class=MsoNormal>EDA/CAE Tools</P>
<P class=MsoNormal>FPGAs</P>
<P class=MsoNormal>Interconnection Devices</P>
<P class=MsoNormal>Packaging</P>
<P class=MsoNormal>PLDs</P>
<P class=MsoNormal>Semiconductors </P>
<P class=MsoNormal>Standard, Analog, Mixed-Signal, Digital, and Memory ICs</P>
<P class=MsoNormal>System Boards</P>
<P class=MsoNormal>Test, Measurement, and Debug Tools</P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal><![if !supportEmptyParas]><![endif]>&nbsp;<o:p></o:p></P>
<P class=MsoNormal>Interested in the DesignCon Sessions?<SPAN 
style="mso-spacerun: yes">&nbsp; </SPAN>You can view or download the entire 
conference catalog at <A 
href="http://www.designcon.com/catalog.pdf">www.designcon.com/catalog.pdf</A><SPAN 
style="mso-spacerun: yes">&nbsp;&nbsp; </SPAN>Experience the DesignCon 
difference!<SPAN style="mso-spacerun: yes">&nbsp; 
</SPAN></P></DIV></BODY></HTML>


--------------0ADE42D1FF363E6488ED8949--

From owner-ibis  Wed Jan 12 09:03:51 2000
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Hi,

I downloaded the HP version of ibischk3.  What do I need to do with the file
before running it.

Thanks in advance,
Henrik Keshishian
From owner-ibis  Tue Jan 18 14:02:47 2000
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To IBIS Committee:

I am sending this out on behalf of Milt.

Bob Ross
Mentor Graphics

------------------------------------------

To All:

This is the final call for presentations and participation at the 
IBIS Summit Meeting held with DesignCon 2000.

If you have not done so, PLEASE signup with me below so we have an
estimated attendence count for planning the lunch.

Milt Schwartz
National Semiconductor


    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    ----------------------------------------------------------------------
    DESIGNCON 2000 IBIS SUMMIT FINAL CALL FOR PARTICIPATION, PRESENTATIONS
    ----------------------------------------------------------------------
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

                     I B I S   S U M M I T   M E E T I N G

Time/Date:     8:00 PM - 5:00 PM, Monday, January 31, 2000

Location:      Santa Clara Convention Center
               Santa Clara, CA

               Meeting Location - Weston Hotel, Grand Ballroom C

Content:       IBIS Future Requirements is the main topic of this meeting
               These include an exchange of ideas on IBIS accuracy,
               connectors, and new requirements under discussion.

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      DesignCon 2000 & National Semiconductor Corporation

SIGN UP FOR THE IBIS Summit by sending a note to the address below:

               Milt Schwartz
               schwartz@nsc.com


                   D E S I G N C O N   2 0 0 0   M E E T I N G S

Time/Date:     Monday - Thursday, January 31 - February 3, 2000

Exhibition:    Tuesday - Wednesday, 12:30 PM - 6:30 PM, February 1 - 2, 2000

IBIS Booth:    #1039, Exhibition Hall
               - Connector Specification and Accuracy Committee Demonstration
               - IBIS Information
               - Contact Jon Powell, jpowell@viewlogic.com, for information.

URL DesignCon2000:
               http://www.designcon.com/

Signup Discount:  
               IBIS member companies may receive a 15 percent discount to
               the DesignCon 2000 Conference.  Past Conference attendees
               also will receive a 20% alumni discount.


AGENDA FOR IBIS SUMMIT

The agenda includes presentations, discussions, refreshments, and a free
buffet luncheon for participants.  In addition, we will have an opportunity
for Ad Hoc presentations and extended discussions.

So far we tentatively plan the following presentations and discussions:

Morning:

  Model Design: Tables and Equations - Lynne Green, HyperLynx
  Connector Model Specification - Gus Panella, Molex

Afternoon:

  Using Statistical Methods to Characterize Receivers to Determine the 
    Applicability of Receiver Modeling Standardization
                                                   - Richard Mellitz, Intel
  Input Receiver Modeling - Don Telium, Cadence
  Extendable Macro Structures of IBIS - Al Davis, HyperLynx
  Ideas for Future IBIS Versions - Arpad Muranyi, Intel
  Discussion - Future of IBIS - Stephen Peters, Intel

Adequate time is set aside for Ad Hoc presentations and discussion.

Presentors, plan on 50 copies for handing out.  Or else, National
Semiconductor will make and bring the copies of the presentations are
received by Milt Schwartz by Wednesday, January 26, 2000.
From owner-ibis  Thu Jan 20 07:55:34 2000
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Reply-To: <chrisp@px.uk.com>
From: "Chris Potts" <chrisp@px.uk.com>
To: <ibis-users@eda.org>
Subject: Built-in model Termination.
Date: Thu, 20 Jan 2000 15:54:29 -0000
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I would like to know if it is possible to add a "built-in" termination
resistor between two pins in an IBIS model text file, i.e. say 50 Ohms
between pins 1 and 2 on a differential receiver port?

Can this be done using a resistance Matrix at the end of the model??

Any help would be very much appreciated, thanks in advance.

Regards

Chris Potts.

Mr Chris Potts BEng(Hons).
Design Engineer
PowerX Ltd
Tel: +44 0161 286 2000 ext 201
Fax: +44 0161 286 2202
E-Mail: chrisp@px.uk.com


From owner-ibis  Thu Jan 20 13:56:23 2000
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Chris:

IBIS Version 3.2 supports the [R Series] keyword and series
element constructs that would allow you to put a resistor
across a differential port.  You need to check with the
simulation vendors regarding whether this feature is
supported in their products.

Bob Ross
Mentor Graphics


Chris Potts wrote:
> 
> I would like to know if it is possible to add a "built-in" termination
> resistor between two pins in an IBIS model text file, i.e. say 50 Ohms
> between pins 1 and 2 on a differential receiver port?
> 
> Can this be done using a resistance Matrix at the end of the model??
> 
> Any help would be very much appreciated, thanks in advance.
> 
> Regards
> 
> Chris Potts.
> 
> Mr Chris Potts BEng(Hons).
> Design Engineer
> PowerX Ltd
> Tel: +44 0161 286 2000 ext 201
> Fax: +44 0161 286 2202
> E-Mail: chrisp@px.uk.com
From owner-ibis  Mon Jan 24 13:26:39 2000
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To All:

Below is the planned Agenda.  We have room for discussions,
and we also may end the meeting early.

Please contact Milt Schwartz at schwartz@nsc.com to sign
up, if you have not done so.

Confirm the room location at the hotel.  It may be listed
under some sponsoring organization such as IEC, DesignCon,
National Semiconductor, etc.

Bob Ross
Mentor Graphics

------------------------------------------------------------------

                   AGENDA, IBIS SUMMIT MEETING
                        JANUARY 31, 2000

                    Westin Hotel, Ballroom E
                  Santa Clara Convention Center
                    Santa Clara, California

------------------------------------------------------------------

8:00 AM     Refreshments & Sign In

8:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - IBIS Booth #1039 Placards
            - Opens for Issues, Discussion           

9:00 AM     Model Designs: Tables and Equations
            Lynne Green, HyperLynx

9:30 AM     Simutaneous Switching Noise Modeling
            Bernhard Unger, Siemens

10:00 AM    Break

10:15 AM    IBIS Booth #1039 - Connector Demonstration
            Bob Haller, Compaq

10:20 AM    Connector Model Specification (& Discussion)
            Gus Panella, Molex

11:30 AM    Using Statistical Methods to Characterize Receivers to Determine
            the Applicability of Receiver Modeling Standardization
            Richard Mellitz, Intel

12:00 PM    Lunch Ballroom D (Hosted by National Semiconductor)
            Westin Hotel

1:00 PM     Input Receiver Behavioral Modeling (& Discussion)
            Donald Telian, Intel

2:15 PM     Extendable Macro Structures of IBIS
            Al Davis, HyperLynx

2:45 PM     Break

3:00 PM     Ideas for Future IBIS Versions
            Arpad Muranyi, Intel

3:30 PM     Discussion - Future of IBIS
            Stephen Peters, Intel

4:00 PM     Other Topics

4:45 PM     Concluding Items
            - Date2000 IBIS Summit
            - Next Meeting February 25, 2000
            - ??

5:00 PM     End of IBIS Summit Meeting

5:00 PM     JEDEC/IBIS Working Group Meeting Plans

------------------------------------------------------------------
From owner-ibis  Mon Jan 24 13:48:03 2000
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From: Bob Ross <bob_ross@mentorg.com>
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To All:

Correction - (Company affiliation correction for Don Telian)

Bob Ross
Mentor Graphics

------------------------------------------------------------------

                   AGENDA, IBIS SUMMIT MEETING
                        JANUARY 31, 2000

                    Westin Hotel, Ballroom E
                  Santa Clara Convention Center
                    Santa Clara, California

------------------------------------------------------------------

8:00 AM     Refreshments & Sign In

8:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - IBIS Booth #1039 Placards
            - Opens for Issues, Discussion           

9:00 AM     Model Designs: Tables and Equations
            Lynne Green, HyperLynx

9:30 AM     Simutaneous Switching Noise Modeling
            Bernhard Unger, Siemens

10:00 AM    Break

10:15 AM    IBIS Booth #1039 - Connector Demonstration
            Bob Haller, Compaq

10:20 AM    Connector Model Specification (& Discussion)
            Gus Panella, Molex

11:30 AM    Using Statistical Methods to Characterize Receivers to Determine
            the Applicability of Receiver Modeling Standardization
            Richard Mellitz, Intel

12:00 PM    Lunch Ballroom D (Hosted by National Semiconductor)
            Westin Hotel

1:00 PM     Input Receiver Behavioral Modeling (& Discussion)
            Donald Telian, Cadence Design

2:15 PM     Extendable Macro Structures of IBIS
            Al Davis, HyperLynx

2:45 PM     Break

3:00 PM     Ideas for Future IBIS Versions
            Arpad Muranyi, Intel

3:30 PM     Discussion - Future of IBIS
            Stephen Peters, Intel

4:00 PM     Other Topics

4:45 PM     Concluding Items
            - Date2000 IBIS Summit
            - Next Meeting February 25, 2000
            - ??

5:00 PM     End of IBIS Summit Meeting

5:00 PM     JEDEC/IBIS Working Group Meeting Plans

------------------------------------------------------------------
From owner-ibis  Tue Jan 25 17:32:11 2000
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From: Bob Ross <bob_ross@mentorg.com>
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To IBIS Summit Attendees:

This is a revised Agenda to resolve a scheduling conflict.
Lynne Green's presentation is moved to the end.  Note,
some Ad Hoc presentations and discussions may be done
in the morning if we have time.

If you have not done so already, let Milt Schwartz know
if you are attending.  People who are presenting: please
send the presentations to Milt for copying at schwartz@nsc.com.
Otherwise, plan to bring 50 copies for distribution at the 
meeting.

We will have an overhead projector and also a projector
for laptop presentations.  I prefer using the overhead
projector, if practical, to maximize interaction and
allow Ad Hoc presentations and discussions (and so my
hand drawn slides won't look so bad :-)).

Bob Ross
Mentor Graphics

------------------------------------------------------------------

                   AGENDA, IBIS SUMMIT MEETING
                        JANUARY 31, 2000

                    Westin Hotel, Ballroom E
                  Santa Clara Convention Center
                    Santa Clara, California

------------------------------------------------------------------

8:00 AM     Refreshments & Sign In

8:30 AM     Introductions
            - Welcome to Summit
            - Introductions
            - IBIS Booth #1039 Placards
            - Opens for Issues, Discussion           

9:00 AM     Simutaneous Switching Noise Modeling
            Bernhard Unger, Siemens

9:30 AM     Ad Hoc Presentations and Discussions

9:50 AM     IBIS Booth #1039 - Connector Demonstration
            Bob Haller, Compaq

10:00 AM    Break

10:15 AM    Connector Model Specification (& Discussion)
            Gus Panella, Molex

11:30 AM    Using Statistical Methods to Characterize Receivers to Determine
            the Applicability of Receiver Modeling Standardization
            Richard Mellitz, Intel

12:00 PM    Lunch Ballroom D (Hosted by National Semiconductor)
            Westin Hotel

1:00 PM     Input Receiver Behavioral Modeling (& Discussion)
            Donald Telian, Cadence Design

2:15 PM     Extendable Macro Structures of IBIS
            Al Davis, HyperLynx

2:45 PM     Break

3:00 PM     Ideas for Future IBIS Versions
            Arpad Muranyi, Intel

3:30 PM     Discussion - Future of IBIS
            Stephen Peters, Intel

4:00 AM     Model Designs: Tables and Equations
            Lynne Green, HyperLynx

4:30 PM     Other Topics

4:45 PM     Concluding Items
            - Date2000 IBIS Summit
            - Next Meeting February 25, 2000
            - ??

5:00 PM     End of IBIS Summit Meeting

5:00 PM     JEDEC/IBIS Working Group Meeting Plans

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From owner-ibis  Wed Jan 26 09:21:11 2000
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From: marc pegolotti <pego@serverworks.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: VT curves 
Date: Wed, 26 Jan 2000 18:34:53 +-100
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Hi ,

I would like to know what is the typical loading modele that should be used to determine the VT curve
for a IBIS CMOS modele ?

If the output of the driver loaded  is ringing or oscillating .  Is is allow ? If yes , when the VT curves 
sampling should stop (before or after oscillation) ?

What are the recomanded guidelines for VT curves in IBIS ?

Best regards  

From owner-ibis  Wed Jan 26 11:09:18 2000
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	Wed, 26 Jan 2000 10:31:51 -0800
From: Al Davis <albertd@hyperlynx.com>
To: marc pegolotti <pego@serverworks.com>,
        "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: Re: VT curves
Date: Wed, 26 Jan 2000 10:12:07 -0800
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On Wed, 31 Dec 1969, marc pegolotti wrote:
> I would like to know what is the typical loading modele that should be used to determine the VT curve
> for a IBIS CMOS modele ?

You should provide at least two waveforms of each type. 
That is, two rising, two falling.

The load should be as close as possible to the real load. 
A heavier load is preferable to a lighter load.  For two
waveforms, one should have a pulldown load, the other
should have a pullup load.  They can be the same
resistance otherwise.

If you can provide more waveforms, one choice is to do two
more, with light loads, almost open.  Another choice is a
load to a middle voltage, like Vcc/2.

When providing multiple waveforms, be sure that the loads
are sufficiently different that the difference in the data
makes sense.  If the difference is only noise or random
variations (such as by two very light loads) this will
cause problems.


> If the output of the driver loaded  is ringing or oscillating .  Is is allow ? If yes , when the VT curves 
> sampling should stop (before or after oscillation) ?

If the info is real, include it.

Too often, models run too long and have a long tail of
noise.  Include only the part of the waveform that is
important.

Also, too often there are too many points, that are only
noise.  Try taking the derivative from the points.  It
should match the true derivative.  This is as important as
the points themselves.  For the pullup and pulldown, the
derivative is MORE important than the values themselves.

From owner-ibis  Fri Jan 28 13:10:39 2000
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
Subject: EUROPEAN IBIS SUMMIT MEETING ANNOUNCEMENT
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            E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                      F I R S T   A N N O U N C E M E N T

Time/Date:     8:30 AM - 2 PM, Friday, March 31, 2000

Location:      Concorde-Lafayette Hotel (adjacent to Le Palais des 
               Congress de Paris Prote Mailot - site of the DATE2000
               Conference in Paris, France

Rooms:         Salon, Van Gogh, Pissarro

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:      INCASES, Mentor Graphics and Viewlogic

DATE2000:      March 27-30, 2000.  The IBIS meeting is scheduled the day
               following the trade show portion of the Conference and the
               PCB Symposium.

               See http://www.date-conference.com for more information.


BACKGROUND

For the last several years we have been holding very successful European IBIS
Summit Meetings.  We plan a combination of the following:

  Submitted Presentations on IBIS Topics (See below)
  Less formal Ad Hoc Presentations and Discussions
  IBIS Questions and Answers
  
Below is an invitation to register and also to submit presentations.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please supply the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Karine Loudet (karine_loudet@mentor.com)  +33 1 40 94 74 54 


CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.  Some suggested subjects of interest are:

  IBIS Model Development Experiences
  Company IBIS Standards and Requirements
  Generating and Validating IBIS Models
  Future IBIS Requirements
  EMC/EMI IBIS Issues


Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Bob Ross (bob_ross@mentor.com)


AGENDA

The agenda includes presentations, discussions, and a free lunch.


FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com
