
From owner-ibis  Tue Sep  1 05:25:39 1998
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From: "fabrizio zanella" <fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com>
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Hello to IBIS users everywhere.  There are a few gate arrays and bus 
transceivers for which I can only get IBIS models, HSPICE is not possible.  
In order to perform a system backplane analysis, though, I need to run the 
simulations in HSPICE, and need to do this very soon.  Does anyone know of 
a consulting service which provides IBIS to HSPICE conversion, and could do 
so quickly?

Thanks very much,
Fabrizio Zanella
EMC Corporation
fzanella@emc.com
508-435-2075, x4645

From owner-ibis  Tue Sep  1 11:40:29 1998
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Date: Tue, 01 Sep 1998 11:36:53 +0000
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From: Matthew Flora <mbflora@hyperlynx.com>
Subject: IBIS Open Forum Minutes   28 Aug 1998
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DATE: 9/1/98

SUBJECT: 8/28/98 EIA IBIS Open Forum Minutes
   
VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Norio Matsui, Raj Raghuram
Cadence Design (& UniCAD)      C. Kumar, Don Telian, Patrick Riffault, 
                               Craig Lewis, Greg Fitzgerald, Paul Galloway,
                               Patrick Dos Santos, Catherine Weiss, 
                               Alain Tribaudot, Geoffrey Ellis*,
                               Todd Westerhoff
Compaq                         Shariq Rahma, Jeff Chu, Greg Edlund*,
  (Digital Equipment Corp.)    Bob Haller
Cypress                        Bruce Wenniger
Hewlett Packard (EEsof, etc.)  Karl Kachigan, Henry Wu, Paul Gregory
High Design Technology         Razvan Ene
HyperLynx                      Kellee Crisafulli, Matthew Flora*
Incases                        Olaf Rethmeier*, Scott Jacobson,
                               Werner Rissiek
Intel Corporation              Stephen Peters, Arpad Muranyi*, Frank Kern,
  (& formerly NCR)             Will Hobbs, Prakash Radhakrishnan,
                               Mohammed Hawana, Martin Chang, Dave Moxley
Mentor Graphics (Zeelan,       Bob Ross*, George Opsahl, Mark Noneman,
  Interconnectix, etc.)        Tom Dagostino, Karine Loudet, Jean Oudinot,
                               Manuel De Almeida, Stephane Rousseau, 
                               Neven Orhanovic, Mohamed Mahmoud
Mitsubishi                     Hoang Nguyen, Tam Cao
Motorola                       (Ron Werner)
National Semiconductor         [Syed Huq], Cheng-Yang Kao, John Goldie,
                               Ikchang Song, Milt Schwartz
North East Systems Associates  Edward Sayre, Kathy Breda
  (NESA)
NEC                            (Hiroshi Matsumoto)
Quantic EMC                    (Mike Ventham)
Symbios Logic                  Larry Barnes
Texas Instruments              Thomas Fisher, Harvey Stiegler,
                               Vincent Chang, Jean-Claude Perrin,
                               Peter Forstner
Thomson-CSF                    Jean-Marc Claveau, Laurent Duzaic,
                               Saverio Lerose, Benoit Meyniel,
                               Jean Lefebvre  
Viewlogic                      Jon Powell, Chris Rokusek*, Guy de Burgh, 
                               Gary Mandel
VeriBest                       Ian Dodd, David Weins, Ian Gabbitas
VLSI Technology                D.C. Sessions
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1998:
Actel                          Eric Tardif, Emmonvelle Gaudin 
Aerospatiale                   Lionel Dreux, Claude Huet
Alcatel (Bell, Espace, etc.)   John Fitzpatrick, W. Temmerman, 
                               Laure Bessettes, Jean-Claude Pourtau,
                               Daniel Peron
ALS Design                     Yves Mouquet
Ansoft                         Eric Bogatin
Apple                          Fred Floresca, Danny Itani
Apteq Design Systems           Dan FitzPatrick 
Atmel                          Ali Baktashian
Avanti                         Nik Bannov
CERN                           Olivier Clere, Jean-Michel Sainson, 
                               Rudi Zurbroken
Cisco Systems                  Syed Huq*, Sergio Camerlo*, Irfan Elahi*
Crucial Technology             Rathna Reddy
EIA                            Patti Rusher
EMC                            Fawn Engelmann, Fabrizio Zanella*
ENST, Paris                    Jean-Jacques Charlot
European CAD Standardization   Adam Morawiec
  Intitiative (ECSI)
Fairchild Semiconductor        Peter LaFlamme
H.A.S Electronics              Haruny Said
IBM                            Richard Steinle, Kevin Jackson
Intracon Design Ltd.           Derek Laidlaw
Philips Semiconductor          Todd Andersen
Scottish Electronics           Robert Easson
  Manufacturing Center (SEMC)
Seagate                        Vanessa Howard
SGS-Thomson                    Philippe Lefevre
Siemens                        Gerald Bannert, Bernhard Unger, 
                               Christian Marot, Miguel Hernandez,
                               Gil Russell
Sun Microsystems               Lam Dong, Kevin Ko
Symmetry                       Andy Hughes
Tektronix                      Nassrin Ghahyasi
Ultratest International        Chris O'Connor
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:
  
  Date               Bridge Number     Reservation #    Passcode
  September 18, 1998 (916) 356-9200    1-249623         2581644

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
7 days before each Open Forum and meeting minutes out within 7 days after.  
When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Syed Huq (past Vice-Chair and formerly of National Semiconductor) called in
from Cisco Systems.  He is now a signal integrity engineer involved with
ASIC design and working for Sergio Camerlo.

Sergio Camerlo is manager of the Signal Integrity and Packaging Group at
Cisco Systems.  He had followed IBIS while at Olivetti.  His group is now
very interested in using IBIS for their signal integrity work.

Irfan Elahi has been with Cisco Systems for nine months.  Irfan has years
of experience doing signal integrity analysis and getting and using IBIS 
models.  He is particularly interested in how IBIS will support connectors in
the future.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross reported that Patti Rusher states no membership or financial
change.

Syed Huq stated that Cisco Systems plans to become a full IBIS Open Forum
member.  Syed plans to contact Patti to get an invoice.


REVIEW OF MINUTES AND AR'S
No corrections were noted.  The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Syed Huq reports that the Roster has been updated.  He also solicited an
update to the roster information for Motorola from an additional contact at
Motorola.

Bob Ross stated that the August 17, 1998 issue of EE Times had a series of
articles on high-speed interconnects with an incidental mention of IBIS.  Ed
Sayre of the IBIS (East) Users Group was on the front page displaying his
"fiendish delight at uncovering knotty engineering problems".


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that Jon Powell plans to clean up the models directory
under eda.org/pub/ibis and remove old subdirectories.  Some older Intel 
models may be retained unless they are publicly available elsewhere on the 
Intel site.  Other models are obsolete or are superceded on company sites.

Also, the models link on the official EIA IBIS Web site has been down for
a while.  Bob is working with Jon on a possible alternative.


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 2.1) - Patti Rusher reported to Bob Ross that the
  document has been moved to the ADVC (Draft Approved for Committee Draft
  With Vote).  This is another step leading to a ratification vote.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuit 
  (IMIC) - Bob Ross mentioned that he might meet again with the committee
  chairman Dr. Hideki Fukuda in September, 1998 to discuss plans.

- IEC 93/67/NP IBIS and EMC Simulation - Bob Ross gave a brief report on a
  recent document he received titled "Electromagnetic Compatibility, Models
  of Integrated Circuits for EMI Simulation".  This document is to be   
  circulated to the IEC National Committees as a new NWIP (new work item
  proposal) replacing the IEC 93/67/NP.  Its scope is to propose a concept
  study and behavioral models for simulation of electromagnetic compatibility
  in emission and susceptibility.

  The objective is to account for the total electrical activity of an 
  integrated circuit including internal core activity, input/output signal
  transitions, power supply dynamic currents, and package parasitic elements.

  Its philosophy is to produce a separate file compatible with IBIS, with the 
  same syntax in an ASCII format.  It must be open to evolution and have
  elements accessible through measurement.

  The document introduces some concepts and proposes some architectures for
  emission and susceptibility models.  However, it needs to be verified and
  optimized.


- JC-16.2 Subcommittee: Modeling and Test - Bob Ross stated that the joint
  meeting is still planned for Wednesday, December 9, 1998 in San Diego with
  the JEDEC JC-42 and JC-16 meetings.  Bob expects the initial details will
  be sent out after the next IBIS telephone meeting.


- IEEE Standard Component Data Sheet - No report.  Matthew Flora reminded Bob 
  Ross of this agenda item.  Bob stated that he is keeping this as an agenda
  item since Stephen Peters may contact Bob Davis, Chair of the committee to 
  call in to one of our meetings.


IBIS (EAST) USERS GROUP MEETINGS
Greg Edlund reported on the Accuracy subcommittee meeting held on Thursday,
August 27, 1998 at Stratus Computer.  The first draft is about one-half  
complete.  The test board is in the PC shop and is expected to be completed
shortly.  The plan is to prepare a DesignCon paper and also an IBIS Summit
presentation in February, 1999.

Fabrizio Zanella reported on the Connector group activities.  The group has
been meeting regularly with representation from connector companies AMP,
Teradyne, Berg, and Molex.  Also Ansoft and Hyperlynx are contributing.
Kellee Chrisafulli is drafting a BIRD for both single and coupled lines.
The intent is that connector models have a separate .con file.  The BIRD
may propose a self-contained document.  The subgroup hopes to complete the
activity by the end of the year.  They are concerned about funding for parser
extensions.

Fabrizio gave a few details of the thinking for the BIRD.  It would cover
three-dimensional extensions and handle 1000 pins.  However, it is based
on using smaller sections and only the significant next pin coupling.

Bob Ross mentioned that if the subgroup wishes, they could send out minutes 
on the IBIS reflectors.  Arpad Muranyi asked if coupled matrices were already
supported and Bob responded that a single stage of coupled LCR is supported
for package models in IBIS Version 2.1

Bob Ross stated that the next IBIS Users group meeting has been rescheduled
from Thursday, August 20, 1998 to Thursday, September 3, 1998 at Stratus
Computer.


OCTOBER 15, 1998 IBIS SUMMIT MEETING PLANS
Bob Ross reported that Kathy Breda is coordinating the arrangements.  The
first meeting notice has been sent out calling for presentations, signups,
sponsors, and providing meeting details.  The meeting will be held at the 
Boxboro Holiday Inn (where the first IBIS Users Group meeting was held).
It is scheduled all day, and lunch and refreshments will be provided.

A two hour IBIS tutorial developed by NESA and TriLogic will be given for
review and feedback.

Greg Edlund will give a report on the IBIS Accuracy progress for discussion.
Fabrizio Zanella will report on the Connector specification status.  Bob
Ross mentioned that he might give a presentation on using Spice to validate
IBIS extensions.  Arpad Muranyi expressed interest in the Accuracy issue.

Bob noted that this meeting will be held at the same time as the PCB
Conference East nearby in Marborough, Massachusetts.  All of the face-to-face 
meetings are held with other meetings of interest to IBIS members since many 
IBIS participants will be in attendance anyway.  Syed Huq asked about an IBIS 
tutorial at the PCB Conference.  Bob noted that it will be conducted the same 
day as the IBIS meeting.

Bob mentioned that Kathy may have a magazine to co-sponsor the meeting.  She
sent out letters to three other companies to co-sponsor (share the expenses
for meeting rental, lunch and refreshments, etc.).

Another notice will go out to get participation commitments.


EDITING COMMITTEE 
No Report.  The editing committee BNF AR remains.

AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (an IBIS Version
3.0 ratification AR).


IBISCHK2+ (VER 2.1.17) PROGRESS
Bob Ross reported that the source code was delivered.  Chris Rokusek compiled
(during the meeting) the executables.

All bugs except BUG25 and new BUGS29-31 are included in this version.  This
release supports the official ANSI/EIA-656 standard or IBIS Version 2.1.

[Bob uploaded the executables after the meeting, per AR, on eda.org under
/pub/ibis/ibschk2+.]

Since Syed is now with a company that has not purchased the parser, Bob
mentioned that he might consider loaning him the source code to get Linux 
executables.


VERSION 3.1/3.2 PARSER DEVELOPMENT
Bob Ross reported that Version 3.1 source code was distributed to those who
funded the parser.

Chris Rokusek compiled the executables during the meeting.  Similar to the
ibischk2+ version, BUG25 and new BUGS29-31 were not included.  Bob explained
that he did not want to hold up the release of executables for BUG25, but
that it would be worked on for the ibischk3, Version 3.2

Bob reported that Atul Agarwal plans to deliver the parser during the third
or fourth week of September, 1998.  He listed several minor errors to the
BIRDS being incorporated.  Bob corrected the errors in a work in progress
ver3_2b.ibs specification which will be uploaded later.

[The new ibischk3 executables have been uploaded to eda.org under /pub/ibis/
ibischk3.


COOKBOOK
No report. 


IBIS MODEL REVIEW COMMITTEE DISCUSSION
Matthew Flora reported that he thinks Motorola will submit a model for 
review.  The list of companies still includes Cadence, HyperLynx, Incases, 
Mentor Graphics, Viewlogic, and Veribest.  Matthew said that he needs to
send a note to the reflector.  His contact address is repeated below:

  Matthew Flora, HyperLynx                   mbflora@hyperlynx.com

AR - Matthew Flora issue to the IBIS reflector a short writeup on the IBIS
IBIS Model Review committee.


BIRD53 - 
Geoffrey Ellis summarized BIRD53 by stating that it basically limited the
line terminators to those supported by UNIX (linefeed) and DOS (carriage
return, line feed).  Geoffrey noted that the 8-bit international character
sets supported other terminators.  Geoffrey listed a number of problems that
could occur if the terminator set were extended.  These included inability
to print the file, and the inability in some systems to recognize certain
terminators.  Sun Unix systems can process the international character
sets, but the involves setting a new environment variable.

Geoffrey supported the limitation as a practical restriction for EDA 
vendors.  Bob Ross asked for the opinions of other EDA vendor participants.
Chris Rokusek agreed with the limitation.  Bob also supported this
limitation because a subset of capability provides a file that is most
easily used by everyone.  Matthew Flora also supported this position.  Olaf
Rethmeier presented a European perspective that EDA vendors must consider
the US market.  So he also supported BIRD53.

Matthew raised some concerns on the wording of the BIRD53 changes.  The
reference to C language \n and \n\r characters was unnecessary.  Also, it was
not clear whether the character set limitation applied to just terminators or
to all characters.  Arpad Muranyi noted that other developers might want to
include comments in their native languages.  However, the information
might be garbled when processed using another character set.  Bob noted that
he wanted BIRD53 to focus only on the termination issue.  In practice the
comment and text characters are not a real issue.  Matthew noted that the
text of BIRD53 could be interpreted narrowly to include limiting comments
in native languages.

Bob indicated that the general consensus was to approve BIRD53.  However,
the wording details needed to be resolved.  Matthew and Geoffry should work
out the acceptable language and issue BIRD53.1 for a vote at the next
meeting.

AR - Geoffrey Ellis and Matthew Flora to work out the technical wording
changes for accuracy and clarity and submit BIRD 53.1 by Friday,
September 4, 1998 so that it can be voted on at the next meeting.


BUG29 - \n, \r. \r\n Line Terminators Need to be Handled
Bob Ross indicated that based on the sense of the committee, BUG29 will be
closed with Will Not Fix.  (This will be finalized if BIRD53.1 is approved.)


BUG30 - [Pin Mapping] Checks are too Simplistic
Bob Ross noted that Atul Agarwal plans to include a fix to BUG30 in the
next ibischk3 parser release.  The current set of tests do not look at
the bus connection restrictions that are documented in the specification.


BUG31 - Error for [Pulldown] Decreasing Current Should be Warning
Bob Ross had some concerns about some of the data in BUG31.  However, he
deferred discussion since he had not looked at the details.  So the action
remains to research BUG31 further before proposing any change to the ibischk3
parser.


INPUT ENHANCEMENTS
Bob Ross briefly noted that input specification enhancements are possible
by adding subparameters to the [Model Spec] keyword.  He noted that comments
have appeared occasionally over the past year on subparameters.  Also some
new Input parameters for duration during input transition are needed.

There have been several reflector comments on the need for more additional
specification parameters in the last year.  Bob noted that all [Model]
subparameters could be expressed in a typ-min-max format under [Model Spec],
similar to Vinh and Vinl.

Bob also noted that some more advanced input considerations relate to SSO
(as suggested by D.C. Sessions) might be included later as a Version 4.X 
enhancement.

Bob noted that he might propose a BIRD on this.  However, such a BIRD could
be disruptive for those vendors implementing IBIS Version 3.1 functionality.


NEXT MEETING:
The next meeting will be on Friday, September 18, 1998 from 8:00 AM to 
10:00 AM.  BIRD53.1 is scheduled for a vote.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentorg.com
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jonp@qdt.com
            Senior Scientist, Viewlogic (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================

From owner-ibis  Tue Sep  1 17:02:27 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Tue, 1 Sep 98 16:57:50 PDT
Message-Id: <9809012357.AA20334@bob>
To: ibis@eda.org
Subject: IBIS BIRD53.1 - IBIS FIle Character Set

To All:

Below is BIRD53.1 from Geoffrey Ellis (with assistance from Matthew
Flora).  This will be scheduled for a vote at the September 18, 1998
meeting.

Bob Ross
Mentor Graphics


                       Buffer Issue Resolution Document  (BIRD)


BIRD ID#:      53.1
ISSUE TITLE:   IBIS File Character Set
REQUESTER:     Geoffrey Ellis at Cadence Design Systems
DATE SUBMITTED: August 7, 1998, September 1, 1998
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

*******************************************************************************
*******************************************************************************

STATEMENT OF THE ISSUE:

While the general syntax rules and guidelines say, "The file must have no more
than 80 characters per line," the rules do not say which character sequences
are legal to terminate a line, e.g. carriage return followed by a linefeed
character, etc.  Also, the Specification does not say whether or not the line
termination character(s) count against the 80 character limit.

The Specification also does not state which characters are legal in an IBIS
file, other than that it is an ASCII file.  Although ASCII is a 7-bit code
("US-ASCII. Coded Character Set - 7-Bit American Standard Code for Information
Interchange. Standard ANSI X3.4-1986, ANSI, 1986"), some published standards
make reference to "8-bit ASCII characters", for example "File Transfer Protocol
RFC 542 NIC 17759".  The International Standards Organization has published
ISO-8859, a group of 8-bit character sets, for use in different regions of the
world.  Each of these character sets is a super set of ASCII, using codes
greater than hexadecimal 07F to represent accented or local characters.

The IBIS Specification should make clear that neither extended character sets,
such as those defined in ISO-8859, nor ASCII controls (other than tabs and
line terminators) are allowed in an IBIS file.

*******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

    The "General Syntax Rules and Guidelines" section contains 13 numbered
    items, including item 4 which states:

        4) The file must have no more than 80 characters per line.

    We propose to modify item 4, and to add item 14, as follows:

        4) A line of the file may have at most 80 characters, followed
           by a line termination sequence.  The line termination sequence must
           be one of the following two sequences: a linefeed character, or a
           carriage return followed by linefeed character.

       14) Only ASCII characters, as defined in ANSI Standard X3.4-1986, may be
           used in an IBIS file.  The use of characters with codes greater than
           hexadecimal 07F is not allowed.  Also, ASCII control characters
           (those numerically less than hexadecimal 20) are not allowed, except
           for tabs or in a line termination sequence. As mentioned in item 10
           above, the use of tab characters is discouraged.

*******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

    At the lowest level of detail, the IBIS Specification needs to say which
    characters are legal, and what constitutes a "line".

    ASCII files produced in a Microsoft/PC environment have lines which end
    with a carriage return followed by a linefeed character, while ASCII files
    produced on UNIX have lines which end with a linefeed character.  An IBIS
    parser should accept either line termination sequence, regardless of the
    environment in which the parser runs.  Any other line termination sequence
    should be ruled out.

    Use of an ISO-8859 extended character set might improve model readability
    in the region of the world where the model was produced, but would make the
    IBIS file less readable in other regions.  The ASCII code, which is a
    subset of each of the ISO-8859 character sets, is the subset which is
    readable across all of the regions.

*******************************************************************************

ANY OTHER BACKGROUND INFORMATION:


*******************************************************************************




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Date: Wed, 09 Sep 1998 12:45:26 +0200
To: ibis@vhdl.org
From: Norbert Wellnitz <norbert_wellnitz@mentorg.com>
Subject: Serial Diodes
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Hi all,

is there any idea how to model seriel diodes ( no terminator ) and to get
them in with the
correct polarity ?
Any idea is welcome.

Mit freundlichem Gruss

Norbert Wellnitz	



Mit freundlichem Gruss

Norbert Wellnitz	

=========================================
Mentor Graphics (Deutschland) GmbH
Education & Training Department	
Tel. +49 (0) 89 57096-0		
Fax +49 (0) 89 57096-455
e-mail: norbert_wellnitz@mentorg.com		
=========================================

+++++++++++++++++++++++++++++++++++++++++
Have a look on http://www.mentorg.com/germany/training 
+++++++++++++++++++++++++++++++++++++++++



From owner-ibis  Wed Sep  9 08:28:44 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Wed, 9 Sep 98 08:24:02 PDT
Message-Id: <9809091524.AA29710@bob>
To: ibis@eda.org, norbert_wellnitz@mentorg.com
Subject: Re:  Serial Diodes

Norbert:

IBIS Version 3.1 contains the [Series Current] keyword
which is designed for modeling non-linear series elements
such as series diodes.  Since [Series Current] is a series
element, the [Series Pin Mapping] keyword can be used to
assign pins to it with the correct polarity.

Best Regards,
Bob Ross
Interconnectix/Mentor Graphics


> Date: Wed, 09 Sep 1998 12:45:26 +0200
> To: ibis@vhdl.org
> From: Norbert Wellnitz <norbert_wellnitz>
> Subject: Serial Diodes


> Hi all,

> is there any idea how to model seriel diodes ( no terminator ) and to get
> them in with the
> correct polarity ?
> Any idea is welcome.

> Mit freundlichem Gruss

> Norbert Wellnitz	



> Mit freundlichem Gruss

> Norbert Wellnitz	

> =========================================
> Mentor Graphics (Deutschland) GmbH
> Education & Training Department	
> Tel. +49 (0) 89 57096-0		
> Fax +49 (0) 89 57096-455
> e-mail: norbert_wellnitz@mentorg.com		
> =========================================

> +++++++++++++++++++++++++++++++++++++++++
> Have a look on http://www.mentorg.com/germany/training 
> +++++++++++++++++++++++++++++++++++++++++





From owner-ibis  Wed Sep  9 14:34:42 1998
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Date: Wed, 9 Sep 98 14:28 CDT
From: beal@lisbon.eng.hou.compaq.com (Weston Beal)
To: ariazi@anigma.com
Subject: Re: [SI-LIST] : IBIS Model Verification
Cc: ibis@eda.org


> From silab.Eng.Sun.COM!owner-si-list Wed Sep  9 14:01:02 1998
> From: Abe Riazi <ariazi@anigma.com>
> To: "'si-list@silab.eng.sun.com'" <si-list@silab.Eng.Sun.COM>
> Subject: [SI-LIST] : IBIS Model Verification
> Date: Wed, 9 Sep 1998 11:21:48 -0700


> Hi Everyone,
> 
...
CHOP
...
> Before using an IBIS model in a simulation, first I check the model for
> possible syntax /format errors using 
> the ibis_chk program, followed by an examination of the I-V data and
> rise/fall times for monotonic behavior (with
> the aid of the Visual IBIS Editor software).  However, this level of
> evaluation can prove insufficient in some cases. 
> 
>    Therefore, I am interested to learn about procedures and tools which
> allow a comprehensive verification of an
> IBIS model, thereby minimizing the possibility of unreliable simulation
> results.
> 

Abe,

Valid point!  I am an IBIS consumer too.  And I'm getting tired of
messy, incomplete, and blatantly wrong IBIS files.  I do the same as
you.  I run ibis_chk and then look at each VI and VT curve with
ibisplot.  About 90% of the files I receive require some fixing on my
side.  It appears that many people are creating IBIS files with very
little understanding of the specification.  Just because s2ibis ran
without errors does not guarantee a good IBIS file!  I think the best
we can do right now is to tell the suppliers about the errors that we
find in their files.  Most of them want to learn how to do it right,
and will gladly accept suggestions when presented tactfully.

Here are some of the flags I look for:
s2ibis 0.91BETA (!!! WARNING !!!)
no Vmeas, Cref, Rref, or Vref
clamp curves left in pullup and pulldown (s2ibis)
pullup and pulldown curves not crossing 0,0
2 significant digits (s2ibis) causing stairstep curves

I don't want to take away from the massive amount of work done in
developing s2ibis.  It can be a great tool if you know how to use it.
Don't just run it without understanding what it does.  I changed some
things I didn't like in the code and use it internally when I have
spice models.

I was saying just yesterday that we need an ibis_fix program to look
for the common errors and try to fix them.  EDUCATION is the only real
answer.

Regards,
Weston Beal

>   Thank you in advance for your response.
> 
>   Best Regards,
> 
>   Abe Riazi
>   SI Engineer
>   Anigma, Inc.
From owner-ibis  Wed Sep  9 18:52:41 1998
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To: beal@lisbon.eng.hou.compaq.com (Weston Beal)
cc: ariazi@anigma.com, ibis@eda.org, si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : IBIS Model Verification 
In-reply-to: Your message of "Wed, 09 Sep 1998 14:28:00 CDT."
             <m0zGpv1-000KyfC@lisbon.eng.hou.compaq.com> 
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Date: Wed, 09 Sep 1998 18:48:29 -0700
From: Stephen Peters <sjpeters@ichips.intel.com>


Hello Weston, others:
  
   I might mention that the IBIS open forum has recognized this problem
of incomplete/messy models and has established an informal model review
program.  It's basic purpose is to provide feedback to
the model creators on what they did or didn't do correctly.  If you receive
an IBIS model that you think is in error and want to have it checked out
send it to Matthew Flora at mbflora@hyperlynx.com.  Several EDA vendors that
support IBIS have volunteered to give submitted models the once over --
including running them with their simulators.  (Obviously, if your model is
unreleased or otherwise confidential you will need to obtain the proper
NDAs...see Matthew for details).

I hope this helps.

          Regards,
          Stephen Peters
          Intel Corp.
          Vice Chair EIA-IBIS Open Forum



> Abe,
> 
> Valid point!  I am an IBIS consumer too.  And I'm getting tired of
> messy, incomplete, and blatantly wrong IBIS files.  I do the same as
> you.  I run ibis_chk and then look at each VI and VT curve with
> ibisplot.  About 90% of the files I receive require some fixing on my
> side.  It appears that many people are creating IBIS files with very
> little understanding of the specification.  Just because s2ibis ran
> without errors does not guarantee a good IBIS file!  I think the best
> we can do right now is to tell the suppliers about the errors that we
> find in their files.  Most of them want to learn how to do it right,
> and will gladly accept suggestions when presented tactfully.
> 
> Here are some of the flags I look for:
> s2ibis 0.91BETA (!!! WARNING !!!)
> no Vmeas, Cref, Rref, or Vref
> clamp curves left in pullup and pulldown (s2ibis)
> pullup and pulldown curves not crossing 0,0
> 2 significant digits (s2ibis) causing stairstep curves
> 
> I don't want to take away from the massive amount of work done in
> developing s2ibis.  It can be a great tool if you know how to use it.
> Don't just run it without understanding what it does.  I changed some
> things I didn't like in the code and use it internally when I have
> spice models.
> 
> I was saying just yesterday that we need an ibis_fix program to look
> for the common errors and try to fix them.  EDUCATION is the only real
> answer.
> 
> Regards,
> Weston Beal
> 
> >   Thank you in advance for your response.
> > 
> >   Best Regards,
> > 
> >   Abe Riazi
> >   SI Engineer
> >   Anigma, Inc.


From owner-ibis  Thu Sep 10 10:14:30 1998
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To: Stephen Peters <sjpeters@ichips.intel.com>,
        beal@lisbon.eng.hou.compaq.com (Weston Beal)
From: Kellee Crisafulli <kellee@hyperlynx.com>
Subject: Re: [SI-LIST] : IBIS Model Verification (correction)
Cc: ariazi@anigma.com, ibis@eda.org, si-list@silab.eng.sun.com
In-Reply-To: <199809100148.SAA28739@xtg801.pdx.intel.com>
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Hi Weston, Stephen,

  I need to modify a statement made by Stephen.
The "Free" IBIS model review is NOT for CAE users.  It was
setup to assist model developers at the IC house with their
models.  We DO NOT have the bandwidth to check models submitted
by users of all the CAE tools in the world.
We DO have the bandwidth to check models submitted by the IC houses.

If we had more volunteers we could expand this program into users.
I suggest a user network be created powered by other users that 
volunteer.  The "IBIS open user forum"


At 06:48 PM 9/9/98 -0700, Stephen Peters wrote:
>
>Hello Weston, others:
>  
>   I might mention that the IBIS open forum has recognized this problem
>of incomplete/messy models and has established an informal model review
>program.  It's basic purpose is to provide feedback to
>the model creators on what they did or didn't do correctly.  If you receive
>an IBIS model that you think is in error and want to have it checked out
>send it to Matthew Flora at mbflora@hyperlynx.com.  Several EDA vendors that
>support IBIS have volunteered to give submitted models the once over --
>including running them with their simulators.  (Obviously, if your model is
>unreleased or otherwise confidential you will need to obtain the proper
>NDAs...see Matthew for details).
>
>I hope this helps.
>
>          Regards,
>          Stephen Peters
>          Intel Corp.
>          Vice Chair EIA-IBIS Open Forum
>
>
>
>> Abe,
>> 
>> Valid point!  I am an IBIS consumer too.  And I'm getting tired of
>> messy, incomplete, and blatantly wrong IBIS files.  I do the same as
>> you.  I run ibis_chk and then look at each VI and VT curve with
>> ibisplot.  About 90% of the files I receive require some fixing on my
>> side.  It appears that many people are creating IBIS files with very
>> little understanding of the specification.  Just because s2ibis ran
>> without errors does not guarantee a good IBIS file!  I think the best
>> we can do right now is to tell the suppliers about the errors that we
>> find in their files.  Most of them want to learn how to do it right,
>> and will gladly accept suggestions when presented tactfully.
>> 
>> Here are some of the flags I look for:
>> s2ibis 0.91BETA (!!! WARNING !!!)
>> no Vmeas, Cref, Rref, or Vref
>> clamp curves left in pullup and pulldown (s2ibis)
>> pullup and pulldown curves not crossing 0,0
>> 2 significant digits (s2ibis) causing stairstep curves
>> 
>> I don't want to take away from the massive amount of work done in
>> developing s2ibis.  It can be a great tool if you know how to use it.
>> Don't just run it without understanding what it does.  I changed some
>> things I didn't like in the code and use it internally when I have
>> spice models.
>> 
>> I was saying just yesterday that we need an ibis_fix program to look
>> for the common errors and try to fix them.  EDUCATION is the only real
>> answer.
>> 
>> Regards,
>> Weston Beal
>> 
>> >   Thank you in advance for your response.
>> > 
>> >   Best Regards,
>> > 
>> >   Abe Riazi
>> >   SI Engineer
>> >   Anigma, Inc.
> 
---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:kellee@hyperlynx.com>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

From owner-ibis  Fri Sep 11 11:39:17 1998
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Date: Fri, 11 Sep 98 11:34:39 PDT
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To: ibis@eda.org
Subject: IBIS Meeting AGENDA 9/18/98

                       IBIS Open Forum Meeting Agenda 
                                for 9/18/98

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   1-249623        2581644

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.

 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Ross
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      International/External Progress
      - IEC 62014-1 (IBIS Version 2.1)                        Rusher
      - pr EIAJ ED-5302 Standard for I/O Interface Model      
           for Integrated Circuits (IMIC)                     Raghuram
      - 93/67/NP IBIS and EMC Simulation                      Perrin
      - JEDEC JC-16.2 Modeling and Testing                    Sessions
      - IEEE Standard Component Data Sheet                    Davis/Peters/Ross

      IBIS (East) Users Group Meetings                        Edlund

      IBISEAST SUMMIT                                         Ross/Breda

      IBISCHK Parsers                                         Ross/Rokusek

      Version 3.1/3.2 Parser Development                      Ross
      - Executables
      - Version 3.2 Document
      - Version 3.2 Parser Development

      Cookbook Status                                         Peters

      IBIS Model Review Committee                             Flora

      New Administrative Issues                               All

 9:00 Technical Discussion

      BIRD53 -  IBIS File Character Set (Vote)                Ellis
      BUG29 - n\, \r, \r\n Line Terminators Need to be        Ellis
              Handled

      BUG31 - Error for [Pulldown Decreasing Current Should   Ross
              be Warning (more discussion)
              
      IBIS Reflector Issues                                   All

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Peters

 9:55 Sign Off
 






From owner-ibis  Fri Sep 11 12:54:32 1998
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From owner-ibis  Thu Sep 17 14:36:30 1998
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To: ibis-users@eda.org, ibis@eda.org, si-list@silab.Eng.Sun.COM
From: Kathy Breda <breda@nesa.com>
Subject: IBIS Summit Agenda - Thurs. 10/15/98 - Can You Attend?
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Greetings:

The October 15th IBIS Summit is rapidly approaching.
The themes of this meeting are IBIS education and 
"real-life" usage of IBIS models.  

Below is a proposed agenda for the upcoming meeting.
We will not be turning away any presentations or
case studies - so don't hesitate to contact me
with an idea! (breda@nesa.com)
					
We're looking for your assistance---+
						|						
						v
					ACTIONS (respond to breda@nesa.com)

*  	Please let me know if you are attending the summit
	so that arrangements can be finalized at the meeting site.

*  	Would you be interested in setting up a software demonstration?
	Purpose is to provide attendees the opportunity to look at
	the different IBIS tools available.

*  	We're looking for more IBIS case studies to be presented.

*	We're looking for more presentations to be presented.

*  	Are you interested in attending the golf outing after the
	meeting?  Should be fun, but let us know if you can join us.

Proposed IBIS Summit Agenda - subject to change
Thursday, October 15, 1998, 8:30 - 4:00
Boxboro Holiday Inn, Boxboro, Massachusetts


During breaks and lunch we would like to have IBIS software
tools demonstrated in the back of the meeting room for the attendees
to view.

8:30 A.M.	Refreshments and informal gathering
9:00		Welcome, Introductions of participants	Ed Sayre
									NESA 
9:15		General IBIS business				Bob Ross
									Mentor/Interconnectix
9:30		IBIS tutorial					Ed Sayre/Joe Socha/TBD
10:30		15 minute break
10:45		Continue with IBIS tutorial
11:30		IBIS Connector Model Definition BIRD	Fabrizio Zanella 
									EMC Corporation
12:00	P.M.	Lunch
1:00		Case Study Panel - Using IBIS Models
		
		Behavioral/IBIS modeling of a FET bus 	Tay Ansari
		switch	using Cadence tools		Sun Microsystems
		
		Measurement and simulations using various	Fabrizio Zanella
		Tools demonstrating and comparing 	
		1) Measurements 2) Spice using spice model
		2) vendors "A" and "B" using IBIS models

		IBIS Accuracy Specification			Robert Haller
									Compaq Computer Corp.

		IBIS Accuracy Test Board			Peter Laflamme
									Fairchild Semiconductor

		Comparison between SPICE and IBIS		Jinhua Chen
		I/O device simulations				NESA				

		MORE CASE STUDIES APPRECIATED!
		
2:00		Break	
2:15		Using SPICE to Validate IBIS keywords			Bob Ross
3:15		PRESENTATION NEEDED!
3:45		Business Wrap-up
4:00		IBIS Summit Golf Outing - Cyprian Keys Golf Club (20 minutes from
		meeting location)
		Greens Fee ($12) to be paid by golfer. This is a Par 3, nine hole course, 
		located twenty minutes from the meeting location. 
		
		284 East Temple St
		Bolyston MA 01505
		508-869-9900
	
		http://features.yahoo.com/golfcourses/ma/boylston/20864.html

+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
|       NORTH EAST SYSTEMS ASSOCIATES, INC.       |
|      -------------------------------------      |
|     "High Performance Engineering & Design"     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
| Kathy Breda             e-mail: breda@nesa.com |
| NESA, Inc.              http://www.nesa.com/    |
| 636 Great Road          Tel +1.978.897-8787     |
| Stow, MA 01775 USA      Fax +1.978.897-5359     |
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+

From owner-ibis  Thu Sep 17 17:06:05 1998
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Date: Thu, 17 Sep 1998 17:01:16 -0700
From: "D. C. Sessions" <dc.sessions@vlsi.com>
Organization: VLSI Technology Inc.
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At this week's meeting of JC-16 and JC-42 (memory standards)
IBM presented the results of a survey of V/I curves (from IBIS!)
from several DDR SDRAM vendors.  Not a lot of agreement.
After some discussion there was a vote and it was decided to
go to ballot with an amendment to the SSTL specification to
include envelope specs -- in IBIS format.  Milestone.

The next day, the JC-42 committee agreed to go forward with
a detailed data-sheet format composition of the DDR SDRAM
standard, to incorporate several detailed electrical specs
including maximum and minimum pin capacitance.  The working
group has provisionally decided to publish the electrical
specs as a full IBIS model of a compliant memory part.

There was a GREAT deal of ignorance as to what IBIS is, what
it can and can't do, etc.  Many of the vendors doubted that
their engineering groups could produce a robust IBIS model
or verify a sample part against a specification model (sounds
like a business opportunity.)  I mentioned to several of the
vendors the posibility of acquiring the model generation tools
that Hyperlynx has so graciously made available.

One of the key functions of the DDR SDRAM spec depends on FET
switches for load isolation in large systems.  I pointed out
that IBIS can now model these devices, which was news to the
TI member there, one Mr. Stephen M. Nolan mailto:s-nolan1@ti.com
who would like to hear from EDA vendors about support for
FET switch models; he'll pass on the contact to the interested
parties within TI.

Several of these issues will be coming up for vote at the joint
December meeting; I want to *strongly* encourage our members to
appear in force as it looks like a priceless opportunity to
educate some very influential people about IBIS at a time when
they are setting standards.  Not a bad marketing opportunity,
either, if it comes to that.

-- 
D. C. Sessions
dc.sessions@vlsi.com
From owner-ibis  Fri Sep 18 14:28:04 1998
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Date: Fri, 18 Sep 1998 14:19:49 -0700
From: Jon Powell <jonp@pacbell.net>
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From the OFFICE of the LIBRARIAN,

The IBIS model page has been put back on-line and updated with all of
the requests that have been sent in over the last few months. You may
note that a large number of previously mentioned pages are either
no-longer working or have had the ibis models removed (or just moved).

If anyone knows where they went, please drop me a line. I have much
better access to this new web page and it is easier for me to do updates
so let me know.


Comments and Suggestions to:
jon@pacbell.net

Complaints to:
BitBucket@have_a_nice_day.org

regards,
jon


From owner-ibis  Mon Sep 21 14:06:26 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Mon, 21 Sep 98 14:01:31 PDT
Message-Id: <9809212101.AA18478@bob>
To: atulapt@giascl01.vsnl.net.in
Subject: Re:  Add Submodel
Cc: ibis@eda.org, ibischk-bug@eda.org

Atul:

I had to think about your question.  My initial intent
was that each submodel be called once.

However, multiple calls of the same model are not prohibited
in the draft specification, and multilple calls are consistent
with how subcircuits or subroutines operate.  So calls to the same
submodel should be allowed for all the cases you show below.

I have comments for each case in your text below.

I have copied this to the IBIS reflector in case there
any concerns or comments on this interpretation.

Best Regards,
Bob Ross




> Date: Sun, 20 Sep 1998 22:23:06 +0000 (GMT)
> From: "APT SOFTWARE AVENUES PVT.LTD" <atulapt@giascl01.vsnl.net.in>
> To: Bob Ross <bobr>
> Subject: Add Submodel


> Hello Bob
> Within an [Add Submodel] there can be repetitions of the same sub model,
> right ?

> [Add Submodel]
> sub1           Driving
> sub1           Non-driving

Could be done more efficiently with one sub1 and the All mode.


> How about
> [Add Submodel]
> sub1           Driving
> sub1           Driving  |  a repetition

This could be used as a simple way of testing a
double strength model sub1 (such as a dynamic clamp
at double strength without creating double strength
IV tables).

> How about
> [Add Submodel]
> sub1           Driving
> sub1           All

Here sub1 is single strength in Non-driving
mode and double strength in the Driving mode.

> (Assume that the model type is appropriate)

> --- atul



From owner-ibis  Thu Sep 24 10:01:28 1998
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From: Matthew Flora <mbflora@hyperlynx.com>
Subject: IBIS Open Forum Minutes   18 Sep 1998
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DATE: 9/24/98

SUBJECT: 9/18/98 EIA IBIS Open Forum Minutes
   
VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Norio Matsui, Raj Raghuram*
Cadence Design (& UniCAD)      C. Kumar, Don Telian, Patrick Riffault, 
                               Craig Lewis, Greg Fitzgerald, Paul Galloway,
                               Patrick Dos Santos, Catherine Weiss, 
                               Alain Tribaudot, Geoffrey Ellis*,
                               Todd Westerhoff
Compaq                         Shariq Rahma, Jeff Chu, [Greg Edlund],
  (Digital Equipment Corp.)    Bob Haller*
Cypress                        Bruce Wenniger
Hewlett Packard (EEsof, etc.)  Karl Kachigan, Henry Wu, Paul Gregory
High Design Technology         Razvan Ene
HyperLynx                      Kellee Crisafulli, Matthew Flora*
Incases                        Olaf Rethmeier, Scott Jacobson,
                               Werner Rissiek
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern*,
  (& formerly NCR)             Will Hobbs, Prakash Radhakrishnan,
                               Mohammed Hawana, Martin Chang, Dave Moxley
LSI Logic (Symbios Logic)      Larry Barnes*
Mentor Graphics (Zeelan,       Bob Ross*, George Opsahl, Mark Noneman,
  Interconnectix, etc.)        Tom Dagostino, Karine Loudet, Jean Oudinot,
                               Manuel De Almeida, Stephane Rousseau, 
                               Neven Orhanovic, Mohamed Mahmoud
Mitsubishi                     Hoang Nguyen, Tam Cao
Motorola                       (Ron Werner)
National Semiconductor         Cheng-Yang Kao, John Goldie, Ikchang Song,
                               Milt Schwartz*
North East Systems Associates  Edward Sayre, Kathy Breda
  (NESA)
NEC                            (Hiroshi Matsumoto)
Quantic EMC                    (Mike Ventham)
Texas Instruments              Thomas Fisher, Harvey Stiegler,
                               Vincent Chang, Jean-Claude Perrin,
                               Peter Forstner
Thomson-CSF                    Jean-Marc Claveau, Laurent Duzaic,
                               Saverio Lerose, Benoit Meyniel,
                               Jean Lefebvre  
Viewlogic                      Jon Powell, Chris Rokusek*, Guy de Burgh, 
                               Gary Mandel
VeriBest                       Ian Dodd, David Weins, Ian Gabbitas
VLSI Technology                D.C. Sessions*
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1998:
Actel                          Eric Tardif, Emmonvelle Gaudin 
Aerospatiale                   Lionel Dreux, Claude Huet
Alcatel (Bell, Espace, etc.)   John Fitzpatrick, W. Temmerman, 
                               Laure Bessettes, Jean-Claude Pourtau,
                               Daniel Peron
ALS Design                     Yves Mouquet
Ansoft                         Eric Bogatin
Apple                          Fred Floresca, Danny Itani
Apteq Design Systems           Dan FitzPatrick 
Atmel                          Ali Baktashian
Avanti                         Nik Bannov
CERN                           Olivier Clere, Jean-Michel Sainson, 
                               Rudi Zurbroken
Cisco Systems                  Syed Huq*, Sergio Camerlo, Irfan Elahi
Crucial Technology             Rathna Reddy
EIA                            Patti Rusher
EMC                            Fawn Engelmann, Fabrizio Zanella
ENST, Paris                    Jean-Jacques Charlot
European CAD Standardization   Adam Morawiec
  Intitiative (ECSI)
Fairchild Semiconductor        Peter LaFlamme
H.A.S Electronics              Haruny Said
IBM                            Richard Steinle, Kevin Jackson
Intracon Design Ltd.           Derek Laidlaw
Philips Semiconductor          Todd Andersen
Scottish Electronics           Robert Easson
  Manufacturing Center (SEMC)
Seagate                        Vanessa Howard
SGS-Thomson                    Philippe Lefevre
Siemens                        Gerald Bannert, Bernhard Unger, 
                               Christian Marot, Miguel Hernandez,
                               Gil Russell
Summit Computer Systems        Bob Davis*
Sun Microsystems               Lam Dong, Kevin Ko
Symmetry                       Andy Hughes
Tektronix                      Nassrin Ghahyasi
Ultratest International        Chris O'Connor
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:
  
  Date               Bridge Number     Reservation #    Passcode
  October 15, 1998   IBIS Summit Meeting - No Phone
  November 6, 1998   TBD               TBD              TBD



All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
7 days before each Open Forum and meeting minutes out within 7 days after.  
When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

INTRODUCTIONS AND MEETING QUORUM
Bob Haller confirms that Digital Equipment is officially Compaq.  Also, Larry
Barnes stated that Symbios Logic is now part of LSI Logic.  Bob Ross mentioned
that the attendees list has been changed and that the EIA IBIS Open Forum
membership now is transferred to these new companies and all their divisions
world-wide.

Bob Davis of Summit Computer Systems joined the meeting to discuss the IEEE
Standard Component Data Sheet activity.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Bob Ross reported no membership or financial change.

Syed Huq stated that Cisco Systems plans to become a full IBIS Open Forum
member and is still working to get the paperwork from Patti Rusher.


REVIEW OF MINUTES AND AR'S
No corrections were noted.  The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
None.


PRESS AND WEB PAGE UPDATES
Syed Huq stated that there is a Mitsubishi Roster update.  Bob Haller and
Larry Barnes will work with Syed to update their sites.

Syed reports that the Models link has been restored, and a new Tools link was
created to the ibischk3 executables.  Syed uploaded linux ibischk2+ and
ibischk3 executables.  Syed also reports the turn around time for web updates
should be 24 hours.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported some new links:

Altera buffers:

  http://www.altera.com/html/atlas/ibis.html

Pericom Semiconductor models:

  http://www.pericom.com/ibis

Bob Ross mentioned that we still need to clean up the models directory
under eda.org/pub/ibis and remove old subdirectories such as the National
subdirectory.


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 2.1) - Bob Ross stated that the IEC plenary
  session is scheduled in London on September 23-25, 1998.  There might be
  some progress on moving IBIS Version 2.1 through some more steps.  Bob
  does not think IBIS will be ratified at that meeting.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - Bob Ross mentioned that he might meet again with the committee
  chairman Dr. Hideki Fukuda in Monday, October 5, 1998 to discuss I/O
  model plans.  Although this was set up as a private meeting, Bob Ross said
  others would be allowed to attend.

- IEC 93/67/NP IBIS and EMC Simulation - Bob Ross reported that a Task Group
  meeting is planned on September 22, 1998 in Paris, prior to the IEC plenary
  meeting in London to prepare a New Work Item to be distributed at the IEC
  meeting in London.

- JC-16.2 Subcommittee: Modeling and Test - Bob Ross initially reported that
  the joint IBIS and JEDEC meeting is planned for Wednesday, December 9, 1998
  in San Diego.  Bob noted that D.C. Sessions sent a note to the IBIS
  reflector on some recent JEDEC JC-16 and JC-42 activities.  He indicates
  that the IBIS format is being considered for Specifying memory products.
  There is growing interested in the IBIS format, but may participants are not
  familiar with its details or how well it works with simulators.  This is an
  opportunity for education.  The note also stated that there is interest in
  the IBIS format for FET switches since they are now being used in DDR SDRAM
  models.

  D.C. gave further details.  The memory manufacturers are not fully aware of
  what IBIS is or does.  D.C. is helping to educate them that it is a format
  for a specification.  If one manufacturer's IBIS specification is used as
  a basis for a memory specification, other manufacturers feel that their
  products may be cut out.  D.C. also provided the JEDEC group information
  about VT and [Ramp] data.  He also has recommended that they join the
  ibis-users reflector to become more familiar with IBIS.

  D.C. also stated that the memory manufacturers need to become familiar with
  IBIS related EDA tools.  He referred to an offer by HyperLynx to provide a
  free tool to semiconductor vendors to assist in doing IBIS model
  development.  Bob Haller stated that in response to a questionnaire sent out
  by Bruce Heilbrunn, several other EDA vendors indicated that they are
  offering free or low cost tools for IBIS model development.  D.C. proposed
  that such tools and offers be put on the EIA IBIS Web Page.  Then
  semiconductor vendors could use this for contact information.  Bob Ross was
  concerned that this was not an appropriate use of the EIA IBIS Web page.  It
  deals with vendor-specific relationships, and Bob suspects that in most
  cases such arrangements are not open-ended - the details and who gets the
  tools need to be worked out on a case-by-case basis directly.  Arpad Muranyi
  supported making the information available.  One possibility might be for EDA
  vendors to use the Roster page itself.  Here the EDA vendors can provide
  information as part of their IBIS Support statement.  Bob Ross noted that
  EDA vendors can notify D.C. directly (602-752-6545) and he can relay the
  information.

  The DDR SDRAM data sheet proposal was discussed.  This is a double data
  rate SDRAM with data transfers rates up to 2 million transfers per second.
  Thus signal integrity concerns are an issue.  The SSTL2 specification is
  designed for this.  The data sheet proposal is to consider IBIS formatted
  envelop tables and data for the I/O characteristics and pin capacitance.
  The IBIS format provides the template for the specification.  This will be
  voted on at the December JEDEC meeting - co-located with the IBIS Summit
  meeting.

  D.C. further elaborated that a compelling reason for the IBIS Version 3.1
  extensions was to support FET switches in memories that are used for 
  memory isolation.

  Bob Ross mentioned that he and D.C. need to work together on the logistics
  of the IBIS Summit meeting.  D.C. strongly urges the IBIS participants to
  also participate in the JEDEC meetings as invited guests.  So Bob and D.C.
  need to provide information on such meetings and how to become an "invited
  guest".   Bob plans for such details to be sent out in the next few weeks
  for early planning.

  AR - Bob Ross and D.C. Sessions work on the logistics of the IBIS Summit
  Meeting / JEDEC JC-42 and JC-16.2 meetings and communicate the information
  using the IBIS reflectors.

 
- IEEE Standard Component Data Sheet - Stephen Peters met on September 17, 1998
  in San Jose with a small group of people concerning initial discussions to
  prepare a Project Authorization Request (PAR).  Stephen summarized the
  Data Sheet contents.  It is intended to be an electronic data sheet covering
  mechanical, thermal, electrical, timing, topological, VHDL descriptions, and
  architectural specification aspects.  The Pinacles document is very large
  and is not the basis for this activity.  The IBIS format could be expanded
  to include power consumption, EMI susceptibility, pin definition, short
  circuit currents, etc.  Arpad Muranyi stated that the short circuit current
  information is already in the I/V tables.  Stephen noted to the group that
  the BIRD (Buffer Issue Resolution Document) process is available to make
  IBIS changes.  Stephen provided the email address for Bob Davis, Chair. of
  the committee as bob@scsi.com if people want more information directly.

  Bob Davis called in later and emphasized that the committee intends to look
  at and rely on existing standards where possible.  It does not intent to
  invent new formats.  A goal is transferrable information from an identifiable
  source.  He wants a succinct and tight format.  Bob provided his website at
  www.scsi.com under projects where more information and documents will be
  stored. 


IBIS (EAST) USERS GROUP MEETINGS
Bob Haller reported on the September 3, 1998 meeting.  It had good attendance
with about 20 participants.  IBIS Summit details were discussed.  The Accuracy
Specification is about one-half done as a rough draft.  The test board is
being built at Fairchild Semiconductor and should be available for display at
the October IBIS Summit.  The connector model BIRD is shaping up.  Ed Sayre
(NESA) and Joe Socha (Trilogic) are developing the IBIS training class and
intend to present the outline and highlights at the IBIS Summit Meeting.  Work
is continuing on a DesignCon paper.


OCTOBER 15, 1998 IBIS SUMMIT MEETING PLANS
Bob Ross noted that a tentative schedule and further details were sent to the
IBIS reflectors by Kathy Breda (NESA) who is coordinating the meeting.  Bob
Ross asked Bob Haller to report on the details.

Bob Haller noted that there is interest in actual case studies.  An
opportunity exists for demonstrations in the back (including the test board
demonstration).

Bob Ross stated that he will include the tentative schedule in the minutes
and reviewed it.  He noted that it will probably change as more presentations
are received and perhaps some time.  Bob summarized the schedule so far as
containing the following:

  A free two hour tutorial
  About six presentations
  A case study panel
  An optional Golf party from 4-6 PM for casual interaction (extra cost)

Arpad Muranyi indicated interest in comparing a computer simulation model with
silicon.

The tentative schedule is below (adapted from the mailing):


8:30 A.M.   Refreshments and informal gathering
9:00        Welcome, Introductions of participants - Ed Sayre (NESA)
9:15        General IBIS business - Bob Ross (Interconnectix/Mentor Graphics)
9:30        IBIS tutorial - Ed Sayre (NESA) /Joe Socha (Trilogic)/TBD
10:30       15 minute break
10:45       Continue with IBIS tutorial
11:30       IBIS Connector Model Definition BIRD - Fabrizio Zanella (EMC)
12:00 P.M.  Lunch
1:00        Case Study Panel - Using IBIS Models
		
	    Behavioral/IBIS modeling of a FET - Tay Ansari (Sun Microsystems)
            Bus using Cadence tools
		
            Measurement and simulations using various - Fabrizio Zanella
            Tools demonstrating and comparing 	
            1) Measurements 2) Spice using spice model
            2) vendors "A" and "B" using IBIS models

            IBIS Accuracy Specification	- Robert Haller (Compaq Computer)

            IBIS Accuracy Test Board - Peter Laflamme (Fairchild Semi.)

            Comparison between SPICE and IBIS - Jinhua Chen (NESA)
            I/O device simulations				

            MORE CASE STUDIES APPRECIATED!
		
2:00        Break	
2:15        Using SPICE to Validate IBIS keywords - Bob Ross (Mentor Graphics)
3:15        PRESENTATION NEEDED!
3:45        Business Wrap-up
4:00        IBIS Summit Golf Outing - Cyprian Keys Golf Club (20 minutes
            from meeting location)
	    Greens Fee ($12) to be paid by golfer. This is a Par 3, nine
            hole course, located twenty minutes from the meeting location. 
		
            284 East Temple St
            Bolyston MA 01505
            508-869-9900

Bob Ross noted that the PCB Conference East is being held nearby Monday
through Friday, October 12-16, 1998 in Marlborough, MA.  So several PCB
Conference attendees can also attend the IBIS Summit.  Bob also noted that
this was an excellent opportunity for some free IBIS training for local 
people and conference attendees.

Kathy is still seeking closure on joint sponsorship issues.  People should
contact Kathy for documentation.

As the emailing indicates, presenters and participants need to notify Kathy
at breda@nesa.com


EDITING COMMITTEE 
Bob Ross may upload a data model.  The editing committee BNF AR remains.

AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (an IBIS Version
3.0 ratification AR).


IBISCHK EXECUTABLES
Bob Ross reported that the ibischk2+, Version 2.1.17 executables and the 
ibischk3 Version 3.1 executables have been uploaded on eda.org.  Thanks to
Chris Rokusek for creating these during the last meeting.  Also, Linux
executables created by Syed Huq have been uploaded as previously reported.
So the AR is completed.


VERSION 3.1/3.2 PARSER DEVELOPMENT
Bob Ross plans to upload ver3_2b.ibs document in the work in progress
directory with the resolution of BIRD53.1 below and some minor editorial
corrections.

As previously reported, Bob is still expecting the first version of ibischk3
for IBIS Version 3.2 by the end of September, 1998.  Atul asked some questions
about data value tests under the new [Submodel keyword.  Bob responded with a
set of tests that are similar to those of existing keywords.


COOKBOOK
No report from Stephen Peters.


IBIS MODEL REVIEW COMMITTEE DISCUSSION
Matthew Flora stated that Motorola has submitted several PECL Models for
review by the Model Review Committee.  Bob Ross believes several people have
already responded.  The committee is composed of EDA tool representatives,
and each should respond privately to the model provider.  The model provider
is expected to consider the comments and make changes, if necessary.

D.C. Sessions reported that VLSI Logic has revised its IBIS models.  Potential
reviewers need to notify D.C. directly by letter to get a copy of the new
library for review.  The letter should state that the reason is for review.
Reviewed models are not to be given to anyone else.

Matthew listed the companies doing the review: HyperLynx, Incases, Mentor
Graphics, Viewlogic, and Veribest.  He expects a new Cadence representative
soon.  Matthew still plans to send a note to the reflector.  His contact
address is listed at the end of these minutes.

AR - Matthew Flora issue to the IBIS reflector a short writeup on the IBIS
Model Review Committee.


BIRD53.1 - IBIS File Character Set
Geoffrey Ellis briefly summarized BIRD53.1 by stating that it limited the
line terminators to those supported by UNIX (linefeed) and DOS (carriage
return, line feed).  Geoffrey and Matthew Flora worked together to produce
BIRD53.1 in response to the editorial comments at the August 28, 1998 IBIS
meeting.  At that time we achieve a general consensus regarding approving
BIRD53.

Raj Raghuram requested that BIRD53.1 new text be read.  Bob Ross read the text
and called for a vote.

BIRD53.1 was approved by unanimous vote.


BUG29 - \n, \r. \r\n Line Terminators Need to be Handled
As a result of the BIRD53.1 approval, BUG29 then is closed with the status
"Will Not Fix".  BUG29 had requested additional terminators besides the UNIX
and DOS terminators above.


BUG31 - Error for [Pulldown] Decreasing Current Should be Warning
Bob Ross continued the discussion on BUG31 by stating that it remained open,
but we did not decide what action to take.  BUG31 requests that the [Pullup],
[Pulldown], [GND Clamp], and [POWER Clamp] table endpoint test be changed
so that it reports a Warning rather than an Error.  The example in BUG29
is confusing and does not appear to have realistic data.  Bob illustrated the
intent with the case that a ground clamp might exist only in the receiver
mode of an I/O buffer, but not appear in the driver mode.  The only way to
model this using IBIS Version 2.1 is to put a compensating current in the
[Pulldown] table (and technically the [Pullup] table).  Because of the 
dominance of the clamp currents, this work-around can create in an ibischk3
Error violation.

Arpad Muranyi and others pointed out that maybe ibischk3 should test the 
summated tables.  Then the endpoint violation would not be reported.

Bob felt there was danger in approving this because the model would be deemed
acceptable, but some simulators might still have problems dealing with this
extreme case.  So the model would have limited transportability.

Matthew Flora wanted to look at the IBIS Specification further to understand
better the problem.  We did not achieve a resolution and will continue the
discussion at a later meeting.


IBIS REFLECTOR ISSUES
No time remained for this discussion.


NEXT MEETING:
The meeting is the IBIS Summit Meeting on Thursday, October 15, 1998 at
Boxboro, Massachusetts.  No teleconference will be available.

The following meeting will be on Friday, November 6, 1998 from 8:00 AM to 
10:00 AM.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentorg.com
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            sjpeters@ichips.intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            mbflora@hyperlynx.com
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            jonp@qdt.com
            Senior Scientist, Viewlogic (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================

Matthew Flora
IBIS Open Forum Secretary
(425) 869-2320 PH
(425) 881-1008 FAX
mbflora@hyperlynx.com
HyperLynx, 17641 NE 67th Court, Redmond, WA 98052 USA

From owner-ibis  Fri Sep 25 15:20:17 1998
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From: "fabrizio zanella" <fabrizio=zanella%eng%emchop1@fishbowl02.lss.emc.com>
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Subject: IBIS model of switches
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I have a question regarding CBT switches.  I know that IBIS version 3.1 
release includes modeling of FET switches, but does anyone know how soon SI 
simulator companies will support v3.1 IBIS models so we can begins 
simulating nets with switches?
thanks, Fabrizio Zanella
EMC corporation
fzanella@emc.com
508-435-2075, x4645
fax 508-435-8949

From owner-ibis  Fri Sep 25 17:15:51 1998
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From: Elias Lozano <elias@3dfx.com>
To: ibis@vhdl.org
Cc: Elias Lozano <elias@3dfx.com>
Subject: 3v5 tolerant IO's for IBIS model generation
Date: Fri, 25 Sep 1998 17:10:08 -0700
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Hi,

I would like to find out if any one has an example of a 5V tolerant 3.3v
volt IO IBIS model generation. It seems to me that the IBIS model is not as
straight forward when mixed voltages are used in the IO and not having
direct pull-down/pull-up diodes.

Any information or examples would be really helpful.

Thanks a lot

Elias
From owner-ibis  Sat Sep 26 14:36:29 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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	id AA02482; Sat, 26 Sep 98 14:31:44 PDT
Date: Sat, 26 Sep 98 14:31:44 PDT
Message-Id: <9809262131.AA02482@bob>
To: ibis@eda.org
Subject: UNOFFICIAL IBIS VERSION 3.2B

To All:

An UNOFFICIAL IBIS ver3_2b.ibs has been uploaded in eda.org/pub/ibis/wip.
It contains approved BIRD53.1 and some editorial corrections.

Also one of the samples under eda.org/pub/ibis/samples/ver3.2 has been
corrected.

Bob Ross
Interconnectix/Mentor Graphics


From owner-ibis  Mon Sep 28 08:05:26 1998
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "\"ibis@vhdl.org\" " <ibis@vhdl.org>
Cc: "\"Elias Lozano\" " <elias@3dfx.com>
Subject: RE: 3v5 tolerant IO's for IBIS model generation
Date: Mon, 28 Sep 1998 07:59:00 -0700
MIME-Version: 1.0
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Content-Type: text/plain

Elias,

We made many 5 volt tolerant 3.3 volt models.  It is really not that
difficult 
to make them.  You can use the pullup reference voltage keyword at 3.3 V and
the
power clamp reference voltage keyword for the 5 V calmps.  Sweep the device
5 
volt relative when it is 3-stated, and sweep it 3.3 relative when it is
driving 
high.  This is to reflect which rail the pullup and the clamp is connected
to, 
but you actually don't even have to do this if you don't care about how the 
currents flow through the package.  In that case, you can sweep everything
3.3 
relative, but don't be surprised that in the 3-state mode your clamps will
show 
up 1.7 volts shifted compared with the way they normally look like.

Arpad Muranyi
Intel Corporation
============================================================================
====


Hi,

I would like to find out if any one has an example of a 5V tolerant 3.3v 
volt IO IBIS model generation. It seems to me that the IBIS model is not as 
straight forward when mixed voltages are used in the IO and not having 
direct pull-down/pull-up diodes.

Any information or examples would be really helpful.

Thanks a lot

Elias
From owner-ibis  Mon Sep 28 19:27:17 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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	id AA16511; Mon, 28 Sep 98 19:22:30 PDT
Date: Mon, 28 Sep 98 19:22:30 PDT
Message-Id: <9809290222.AA16511@bob>
To: ibis@eda.org
Subject: IBIS BIRD54 - PACKAGE MODEL CORRECTIONS

To All:

BIRD54 corrects a mistake in the IBIS Version 3.1 standard which causes
the ibischk3 parser to not process transmission line package models as
originally intended.  A (note 1) associated with a listing of keywords
needed to be revised.  BIRD54 covers this in more detail.

BIRD54 needs to be considered and approved before Version 3.2 can be
released.

Bob Ross
Interconnectix/Mentor Graphics

******************************************************************************
******************************************************************************

BIRD ID#:       54
ISSUE TITLE:    Package Model Corrections
REQUESTER:      Bob Ross, Mentor Graphics, Stephen Peters, Intel Corporation
DATE SUBMITTED: September 28, 1998
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

In compliance with an editorial mistake in the Package Modeling Section
the ibischk3 parser requires the Matrix Models defined even for tranmission
line sections.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The Note (1) and list of required keywords needs to be corrected.

The original section is shown:

|=============================================================================
|=============================================================================
|
|                                 Section 7
|
|                      P A C K A G E   M O D E L I N G
|
|=============================================================================
|=============================================================================
|
| The [Package Model] keyword is optional.  If more than the default RLC
| package model is desired, use the [Define Package Model] keyword.
|
| Use the [Package Model] keyword within a [Component] to indicate the package
| model for that component.  The specification permits .ibs files to contain
| the following additional list of package model keywords.  Note that the
| actual package models can be in a separate <package_file_name>.pkg file or
| can exist in the IBIS files between the [Define Package Model]...
| [End Package Model] keywords for each package model that is defined.  For
| reference, these keywords are listed below.  Full descriptions follow.
| Simulators that do not support these keywords will ignore all entries
| between the [Define Package Model] and [End Package Model] keywords.
|
|   [Define Package Model]     Required if the [Package Model] keyword is used
|   [Manufacturer]             (note 1)
|   [OEM]                      (note 1)
|   [Description]              (note 1)
|   [Number Of Sections]       (Optional)
|   [Number Of Pins]           (note 1)
|   [Pin Numbers]              (note 1)
|   [Model Data]               (note 1)
|   [Resistance Matrix]        Optional
|   [Inductance Matrix]        (note 1)
|   [Capacitance Matrix]       (note 1)
|   [Bandwidth]                Required (for Banded_matrix matrices only)
|   [Row]                      (note 1)
|   [End Model Data]           (note 1)
|   [End Package Model]        (note 1)
|
| (note 1) Required when the [Define Package Model] keyword is used
|

The list of keywords is revised when adding (note 2) and (note 3):

|   [Define Package Model]     Required if the [Package Model] keyword is used 
|   [Manufacturer]             (note 1)
|   [OEM]                      (note 1)
|   [Description]              (note 1)
|   [Number Of Sections]       (note 2)
|   [Number Of Pins]           (note 1)
|   [Pin Numbers]              (note 1)
|   [Model Data]               (note 2)
|   [Resistance Matrix]        Optional when [Model Data] is used
|   [Inductance Matrix]        (note 3)
|   [Capacitance Matrix]       (note 3)
|   [Bandwidth]                Required (for Banded_matrix matrices only)
|   [Row]                      (note 3)
|   [End Model Data]           (note 2)
|   [End Package Model]        (note 1)
|
| (note 1) Required when the [Define Package Model] keyword is used
| (note 2) Either the [Number or Sections] or the [Model Data]/[End Model Data]
|          keywords are required.  Note that [Number of Sections] and the 
|          [Model Data]/[End Model Data] keywords are mutually exclusive.
| (note 3) Required when the [Define Package Model] keyword is used
|          and the [Number Of Sections] keyword is not used.
|



******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

In IBIS Version 2.1, the [Pin Numbers] keyword list the pins and their order
to be used with the [Define Model] keyword that supported the coupled matrix
keywords.  (note 1) documented all of the required keywords in this context.

As a result of the BIRD28.3 and BIRD37.3 evolution, the syntax for the 
listing of pins under [Pin Numbers] was extended to include subparameter
sections for lumped and distributed elements.  The [Number Of Sections]
keyword was introduced.  (It had as stronger need when cascaded coupled
matrix sections were being discussed).  The final resolution was to support
both the matrix format of Version 2.1 and also the uncoupled lumped and
distributed elements on the [Pin Numbers] WITHOUT the matrix format of
Version 2.1.  The [Number Of Sections] keyword provided the flag that
[Pin Numbers] list now had additional elements.

The changed and extended keyword meanings are documented with the Package
Modeling section.   However, (note 1) was not properly reviewed when the
[Number of Sections] keyword was added to the list for IBIS Version 3.0.
Consequently, the [Define Model] keyword appeared to be required even
when uncoupled sections were documented.  (The ibischk3, version 3.1.0
parser requires this incorrect interpretation.)

BIRD54 corrects this editorial mistake by adding (note 2) and (note 3).
These notes document what is required when the package model has just
uncoupled lumped or distributed sections liste under the [Pin Numbers]
keyword.

It was never the intention to support the combination of BOTH partial
matrix descriptions for some pins and lumped or distributed sections for
other pins.


******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

See BIRD28.3 and BIRD37.3 under http://www.eda.org/pub/ibis/birds.

******************************************************************************








