Join Us for Accellera Systems Initiative Day at DVCon
Accellera Systems Initiative invites you to a special day dedicated to technical standards at the 2013 Design and Verification Conference. Find out the latest in EDA and IP standards such as UVM, UPF, SystemC, and AMS being developed and implemented by today’s leading electronics companies. Our Town Hall luncheon features an open question and answer session with Accellera board members, as well as presentation of the annual Technical Excellence Award for outstanding achievement and contribution to Accellera standards.
Join us at this day-long event to connect with experts and users as we learn, share, and network on the latest in standards innovations.
|8:30am - 12:00pm||Tutorial 1: Lessons from the Trenches: Migrating Legacy Verification Environments to UVM™ Read abstract|
|9:00am - 12:00pm||Tutorial 2: Increasing Productivity with SystemC™ in Complex System Design and Verification Read abstract|
|12:00pm - 1:15pm||Town Hall Lunch and Technical Excellence Award Presentation View details|
|1:30pm - 4:30pm||Tutorial 3: Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™ Read abstract|
|1:30pm - 4:30pm||Tutorial 4: User Experiences at the Forefront of Mixed-Signal Design and Verification Read abstract|
$85 per tutorial with online notes
$360 for tutorial package with online notes
Accellera Systems Initiative Day is brought to you by our global sponsors: ARM, Cadence, Mentor Graphics, and Synopsys.
Thomas Alsop - Intel Corp.
The Universal Verification Methodology (UVM) is the industry standard verification base class library (BCL) developed within the Accellera System Initiative Verification IP technical subcommittee (VIP-TSC). UVM has been released now for nearly two years and brings the industry together on VIP collaboration and reuse. All new technologies have end user challenges in terms of migration and/or adoption, and UVM is no different. Migrating to UVM from either OVM, VMM, Specman/’e’, or other verification BCLs is not always easy. Companies with legacy verification collateral often have to write wrapper environments for other VIPs, write complicated translation scripts, or manually convert code from one methodology to another. In this UVM migration and adoption session are the real stories from end users who work in the trenches making this conversion magic happen for their teams as they move to UVM. If you haven’t moved to UVM yet, this is a session you cannot miss.
John Aynsley - Doulos
Hassan Shehab - Intel Corp.
Richard Tseng - Qualcomm, Inc.
Asad Khan - Texas Instruments, Inc.
Mark Litterick - Verilab, Inc.
Wesley Queen - IBM Corp.
Charles Zhang - Paradigm Works, Inc.
Ravi Ram - Altera Corp.
Yatin Trivedi - Accellera Systems Initiative
After a decade of evolution, IEEE 1666™, a.k.a. SystemC™, is widely used for high level system design description and verification. As the system complexity increases, SystemC is becoming an enabler to build platforms for advanced design and verification techniques. Some of these techniques include high level synthesis, virtual platforms for prototyping, and a wide array of debug techniques to locate and isolate hard-to-find bugs. In this tutorial, some of the experienced users and tool developers will share their interdisciplinary use of SystemC in building verification environments that provide early hardware access to software developers.
Trevor Wieman - Intel Corp.
David Black - Doulos
Stuart Swan - Cadence Design Systems, Inc.
Shabtay Matalon - Mentor Graphics Corp.
Jon McDonald - Mentor Graphics Corp.
Nithya Ruff - Synopsys, Inc.
Charu Khosla - Synopsys, Inc.
Accellera Systems Initiative invites all attendees of the Monday tutorials to the Town Hall style discussion on issues you face in your projects. Within the confines of design and verification standards by Accellera, we will discuss some of the challenges of developing standards-by-committee and deploying standards in active projects. Questions will be asked and responses will be provided by the attendees, many of whom are long time participants in Accellera activities such as SystemC, SystemVerilog, Verilog-AMS, and IP-XACT.
The Annual Technical Excellence Award will be presented during the Town Hall session. Lunch will be served.
Host: Yatin Trivedi - Member of the Board of Directors, Accellera Systems Initiative
Erich Marschner - Mentor Graphics Corp.
Low power design and verification are increasingly necessary in today’s world, as electronic devices become increasingly portable, power and cooling become increasingly expensive, and consumer demand for more features with less power drive product development. The IEEE 1801 standard, Unified Power Format (UPF), enables low power design and verification in multi-vendor flows, from early RTL verification of the power management architecture through physical design and implementation. This lecture-format tutorial will present an overview of UPF-based low power design, verification, and implementation, as well as examples of UPF application from both the IP developer’s and the system integrator’s perspective.
This tutorial will cover the basics of Accellera UPF and then focus on the features of IEEE 1801 that enable the description of more sophisticated power management systems. The tutorial will also provide recommendations regarding migration from Accellera UPF to IEEE 1801 and the methodology changes that are required. It will identify some of the changes coming in 2013 to clarify and enhance the semantics of IEEE 1801.
Part 1 of the tutorial will be a detailed review of UPF and low power design concepts, including a discussion of power management techniques, power management architecture, and power intent specification. This section will cover power architectural elements such as power domains, isolation, level shifting, and retention; power distribution elements such as supply ports and nets, power switches, and supply sets; and power state modeling for supplies, supply sets, power domains, and systems. Methodology for effective use of these features will also be addressed, including the concepts of hierarchical specification of power intent and incremental refinement. This part of the tutorial will be presented by EDA tool developers.
Part 2 of the tutorial will present a UPF-based design flow highlighting the practical aspects of using UPF for verification and implementation. This section will cover the use of UPF for specification of low power constraints for IP blocks, logical configuration of those blocks for integration into a system, and the system’s technology-specific physical implementation. This flow will be illustrated with practical examples representative of real systems. Best practices for successful design and verification of low power systems with UPF will also be presented. This part of the tutorial will be presented by UPF users.
Tutorial attendees will gain a detailed understanding of not only the IEEE standard definition of UPF—concepts, terminology, and features—but also an understanding of the practical aspects of applying UPF in real world flows.
John Biggs - ARM, Inc.
Sushma Honnavara-Prasad - Broadcom Corp.
Dr. Qi Wang - Cadence Design Systems, Inc.
Erich Marschner - Mentor Graphics Corp.
Jeffrey Lee - Synopsys, Inc.
Martin Barnasconi - NXP Semiconductors
Hélène Thibiéroz - Synopsys, Inc.
In today’s embedded and integrated systems, we observe an increasingly tighter integration and interaction between the digital hardware and software (HW/SW) subsystem and analog/mixed-signal (AMS) blocks such as radio frequency (RF) interfaces, power management, or sensors and actuators. Examples are software defined radios, wireless sensor networks, and high-speed interfaces, in which analog circuits are controlled, configured, or calibrated using digital techniques in hardware or software.
In order to design and verify these complex mixed-signal systems, new techniques and methodologies are needed to better analyze, model, and simulate the interaction between the analog, digital, and software components in a more integral and holistic way.
In this tutorial we highlight the latest advancements in mixed-signal design and verification presented by end-users that are active at the forefront, using the latest and greatest technologies and methods. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, the usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system level.
Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see.
Mei-Cheng Huang - Advanced Micro Devices, Inc.
Ozan Erdogan - Maxim Integrated Products, Inc.
Thilo Voertler - Fraunhofer IIS
Christophe Curis - STMicroelectronics
Martin Barnasconi - NXP Semiconductors
Henry Chang - Designer’s Guide Consulting, Inc.
Thang Nguyen - Infineon Technologies AG