From jose Thu Oct 13 18:56:05 1994 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA20514; Thu, 13 Oct 94 18:56:05 PDT Date: Thu, 13 Oct 94 18:56:05 PDT From: jose (Jose Torres) Message-Id: <9410140156.AA20514@vhdl.vhdl.org> To: math@vhdl.org Subject: 9/94 minutes from Math package meeting VHDL MATH PACKAGE WORKING GROUP, P1076.2 Minutes of meeting in Grenoble, 23 September 1994 Present: Jose Torres, Synopsys (Chair), jose@synopsys.com Peter Sinander, European Space Agency (Minutes), psi@wd.estec.esa.nl Sylvie Hurat, Thomson-CSF, hurat@sctf.thomson.fr Adam Morawiec, Artemis/ECSI, Adam.Morawiec@imag.fr Next meeting: most probably at VIUF in November at Washington, DC, USA. 1. INTRODUCTION P1076.2 Working Group members are: - J. Torres, Synopsys (Chair) - C. Swart, Mentor Graphics - A. Zamfirescu, Intergraph - D. Hanson, University of Mississippi The VHDL math packages consist of basic functions and type conversions for real and complex types, and will be placed in the IEEE library. There are two packages: MATH_REAL and MATH_COMPLEX. A testbench will be prepared for each package, but it will not formally be part of the standard just a reference (see further section 4). 2. NEW RELEASE OF MATH PACKAGE A new release of the math package will be placed on the VI server in October. Several bugs were detected in the previous version, which have been corrected in the new version. The package is available through anonymous ftp from vhdl.org, in the directory /vi/math/package, file names are: math_head.9.30.94.vhd math_body.9.30.94.vhd The packages can be retrieved as follows: ftp vhdl.org username: anonymous password: ftp> cd /vi/math/package ftp> get math_head.9.30.94.vhd ftp> get math_body.9.30.94.vhd ftp> bye 3. PLANNED ACTIVITIES The work on the testbench is still in progress. There is a need for more effort in this task, and anybody that could provide help should contact Jose Torres. The ballot constituency will take place in October/November, by invitation through the math package reflector as well as direct e-mail to certain persons. The balloting is planned for January 1995. The IEEE approval is currently foreseen for mid 1995. There is a possibility that Rita Clover will help with the preparation of the standard, which need to be written according to the IEEE standard format. 4. IMPLEMENTATION DETAILS The body of the math package is written in VHDL, though in most cases simulator vendors will implement it in C-code for optimized performance. The minimum precision is that of the VHDL LRM; minimum 6 bits precision in a range from -1E38 to 1E38 is required, but an implementation is allowed to provide higher precision. Sylvie Hurat stressed the importance of a double precision version of the Math packages becoming available, since this is required for system simulations and analog VHDL. It is important that other WGs (particularly the analog WG) do not define their own packages. It is proposed to ballot the single-precision version of the packages now, and later create a double precision version by overloading the funtions when the double precision data type is defined by the analog WG. No new functions should be added for the double precision versions. See further section 5. It was agreed at the meeting that the precision of the constants declared should at least cover the IEEE-754 double precision accuracy, i.e. 16 digits. It is required that the functions detect and report invalid parameters (out of range), but underflow/overflow detection is optional. The severity level can be defined by the user, with the default being Error. The package will be written to conform with both VHDL-1987 and VHDL-1993. 4. TESTBENCHES AND VERIFICATION APPROACH The testbench, which is not part of the standard and will be provided as a reference only. In principle, the test bench will exercise all data points for all the functions in each package, it will compare the outputs from an implementation against a set of "golden" outputs, and will produce a report with differences found. Final details on the process are still being worked out. It is important to note that the math package results may be slightly different on different workstation combinations due to the workstations particular support for floating point arithmetic, which may not be immediately apparent to the average VHDL user. However, since most workstations use the IEEE-754 floating point format the variations will be limited in practice. 5. OPEN ISSUES Jose Torres has proposed to start the balloting process even though the testbenches have not been completed. This was considered as a practical approach by the meeting participants, since the testbench is not part of the standard. The final decision will be taken by the WG members. It is desirable that all IEEE packages should report errors in a standardized way, so contact is necessary with the other IEEE WGs. The contents of the error messages should also be reviewed to be understandable and useful for the average VHDL user (and not only for numerical experts). The coordination with the analog WG is minimal, no formal feedback has yet been received from this WG. However, Sylvie Hurat who is following that WG stated that they have basically defined what functions they need. Another question is whether double precision reals will be called Real or renamed to a new type called Float. Jose Torres will contact J.-M. Berge or A. Vachoux to obtain formal comments from the analog WG. 6. MISCELLANEOUS Jose Torres mentioned that the activity on the e-mail reflector has been low during the past months, but should increase with the event of the new release of the package and the balloting process. It was stated that no problems are expected with vendors adopting the Math packages, since this topic does not seem to be a controversial one and different vendors have provided input or offered a version of their own packages as a starting point for this standard. From jose@Synopsys.COM Fri Oct 14 15:47:21 1994 Return-Path: Received: from chronos.synopsys.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02527; Fri, 14 Oct 94 15:47:21 PDT Received: from gaea.synopsys.com by chronos.synopsys.com with SMTP id AA21826 (5.65c/IDA-1.4.4 for ); Fri, 14 Oct 1994 15:43:25 -0700 Received: from jose.synopsys.com by gaea.synopsys.com with SMTP id AA28903 (5.65c/IDA-1.4.4 for ); Fri, 14 Oct 1994 15:43:23 -0700 Received: by jose.synopsys.com (4.1/SNPS-Sub02) id AA24261; Fri, 14 Oct 94 15:43:22 PDT Date: Fri, 14 Oct 94 15:43:22 PDT From: jose@Synopsys.COM (Jose Torres) Message-Id: <9410142243.AA24261@jose.synopsys.com> To: math@vhdl.org Subject: vhdl math package (declaration) ------------------------------------------------------------------------ -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE MATH_REAL -- -- Library: This package shall be compiled into a library -- symbolically named IEEE. -- -- Purpose: VHDL declarations for mathematical package MATH_REAL -- which contains common real constants, common real -- functions, and real trascendental functions. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- History: -- Version 0.1 (Strawman) Jose A. Torres 6/22/92 -- Version 0.2 Jose A. Torres 1/15/93 -- Version 0.3 Jose A. Torres 4/13/93 -- Version 0.4 Jose A. Torres 4/19/93 -- Version 0.5 Jose A. Torres 4/20/93 Added RANDOM() -- Version 0.6 Jose A. Torres 4/23/93 Renamed RANDOM as -- UNIFORM. Modified -- rights banner. -- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility -- with package body. -- Version 0.8 Jose A. Torres 9/2/94 Rev up for compatibility -- with package body. -- Version 0.9 Jose A. Torres 9/30/94 Rev up for distribution ------------------------------------------------------------- Library IEEE; Package MATH_REAL is -- -- commonly used constants -- constant MATH_E : real := 2.71828_18284_59045_23536; -- value of e constant MATH_1_E: real := 0.36787_94411_71442_32160; -- value of 1/e constant MATH_PI : real := 3.14159_26535_89793_23846; -- value of pi constant MATH_1_PI : real := 0.31830_98861_83790_67154; -- value of 1/pi constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942; -- natural log of 2 constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402; -- natural log of10 constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074; -- log base 2 of e constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765; -- log base 10 of e constant MATH_SQRT2: real := 1.41421_35623_73095_04880; -- sqrt of 2 constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440; -- sqrt of 1/2 constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730; -- sqrt of pi constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577; -- conversion factor from degree to radian constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685; -- conversion factor from radian to degree -- -- attribute for functions whose implementation is foreign (C native) -- attribute FOREIGN : string; -- predefined attribute in VHDL-1992 -- -- function declarations -- function SIGN (X: real ) return real; -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0 function CEIL (X : real ) return real; -- returns smallest integer value (as real) not less than X function FLOOR (X : real ) return real; -- returns largest integer value (as real) not greater than X function ROUND (X : real ) return real; -- returns integer FLOOR(X + 0.5) if X > 0; -- return integer CEIL(X - 0.5) if X < 0 function FMAX (X, Y : real ) return real; -- returns the algebraically larger of X and Y function FMIN (X, Y : real ) return real; -- returns the algebraically smaller of X and Y procedure UNIFORM (variable Seed1,Seed2:inout integer; variable X:out real); -- returns a pseudo-random number with uniform distribution in the -- interval (0.0, 1.0). -- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must -- be initialized to values in the range [1, 2147483562] and -- [1, 2147483398] respectively. The seed values are modified after -- each call to UNIFORM. -- This random number generator is portable for 32-bit computers, and -- it has period ~2.30584*(10**18) for each set of seed values. -- function SRAND (seed: in integer ) return integer; -- -- sets value of seed for sequence of -- pseudo-random numbers. -- It uses the foreign native C function srand(). attribute FOREIGN of SRAND : function is "C_NATIVE"; function RAND return integer; -- -- returns an integer pseudo-random number with uniform distribution. -- It uses the foreign native C function rand(). -- Seed for the sequence is initialized with the -- SRAND() function and value of the seed is changed every -- time SRAND() is called, but it is not visible. -- The range of generated values is platform dependent. attribute FOREIGN of RAND : function is "C_NATIVE"; function GET_RAND_MAX return integer; -- -- returns the upper bound of the range of the -- pseudo-random numbers generated by RAND(). -- The support for this function is platform dependent, and -- it uses foreign native C functions or constants. -- It may not be available in some platforms. -- Note: the value of (RAND() / GET_RAND_MAX()) is a -- pseudo-random number distributed between 0 & 1. attribute FOREIGN of GET_RAND_MAX : function is "C_NATIVE"; function SQRT (X : real ) return real; -- returns square root of X; X >= 0 function CBRT (X : real ) return real; -- returns cube root of X function "**" (X : integer; Y : real) return real; -- returns Y power of X ==> X**Y; -- error if X = 0 and Y <= 0.0 -- error if X < 0 and Y does not have an integer value function "**" (X : real; Y : real) return real; -- returns Y power of X ==> X**Y; -- error if X = 0.0 and Y <= 0.0 -- error if X < 0.0 and Y does not have an integer value function EXP (X : real ) return real; -- returns e**X; where e = MATH_E function LOG (X : real ) return real; -- returns natural logarithm of X; X > 0 function LOG (BASE: positive; X : real) return real; -- returns logarithm base BASE of X; X > 0 function SIN (X : real ) return real; -- returns sin X; X in radians function COS ( X : real ) return real; -- returns cos X; X in radians function TAN (X : real ) return real; -- returns tan X; X in radians -- X /= ((2k+1) * PI/2), where k is an integer function ASIN (X : real ) return real; -- returns -PI/2 < asin X < PI/2; | X | <= 1 function ACOS (X : real ) return real; -- returns 0 < acos X < PI; | X | <= 1 function ATAN (X : real) return real; -- returns -PI/2 < atan X < PI/2 function ATAN2 (X : real; Y : real) return real; -- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0 function SINH (X : real) return real; -- hyperbolic sine; returns (e**X - e**(-X))/2 function COSH (X : real) return real; -- hyperbolic cosine; returns (e**X + e**(-X))/2 function TANH (X : real) return real; -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X)) function ASINH (X : real) return real; -- returns ln( X + sqrt( X**2 + 1)) function ACOSH (X : real) return real; -- returns ln( X + sqrt( X**2 - 1)); X >= 1 function ATANH (X : real) return real; -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1 end MATH_REAL; --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE MATH_COMPLEX -- -- Purpose: VHDL declarations for mathematical package MATH_COMPLEX -- which contains common complex constants and basic complex -- functions and operations. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body uses package IEEE.MATH_REAL -- -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- History: -- Version 0.1 (Strawman) Jose A. Torres 6/22/92 -- Version 0.2 Jose A. Torres 1/15/93 -- Version 0.3 Jose A. Torres 4/13/93 -- Version 0.4 Jose A. Torres 4/19/93 -- Version 0.5 Jose A. Torres 4/20/93 -- Version 0.6 Jose A. Torres 4/23/93 Added unary minus -- and CONJ for polar -- Version 0.7 Jose A. Torres 5/28/93 Rev up for compatibility -- with package body. -- Version 0.8 Jose A. Torres 9/2/94 Rev up for compatibility -- with package body. -- Version 0.9 Jose A. Torres 9/30/94 Rev up for distribution ------------------------------------------------------------- Library IEEE; Package MATH_COMPLEX is type COMPLEX is record RE, IM: real; end record; type COMPLEX_VECTOR is array (integer range <>) of COMPLEX; type COMPLEX_POLAR is record MAG: real; ARG: real; end record; constant CBASE_1: complex := COMPLEX'(1.0, 0.0); constant CBASE_j: complex := COMPLEX'(0.0, 1.0); constant CZERO: complex := COMPLEX'(0.0, 0.0); function CABS(Z: in complex ) return real; -- returns absolute value (magnitude) of Z function CARG(Z: in complex ) return real; -- returns argument (angle) in radians of a complex number function CMPLX(X: in real; Y: in real:= 0.0 ) return complex; -- returns complex number X + iY function "-" (Z: in complex ) return complex; -- unary minus function "-" (Z: in complex_polar ) return complex_polar; -- unary minus function CONJ (Z: in complex) return complex; -- returns complex conjugate function CONJ (Z: in complex_polar) return complex_polar; -- returns complex conjugate function CSQRT(Z: in complex ) return complex_vector; -- returns square root of Z; 2 values function CEXP(Z: in complex ) return complex; -- returns e**Z function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar; -- converts complex to complex_polar function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex; -- converts complex_polar to complex -- arithmetic operators function "+" ( L: in complex; R: in complex ) return complex; function "+" ( L: in complex_polar; R: in complex_polar) return complex; function "+" ( L: in complex_polar; R: in complex ) return complex; function "+" ( L: in complex; R: in complex_polar) return complex; function "+" ( L: in real; R: in complex ) return complex; function "+" ( L: in complex; R: in real ) return complex; function "+" ( L: in real; R: in complex_polar) return complex; function "+" ( L: in complex_polar; R: in real) return complex; function "-" ( L: in complex; R: in complex ) return complex; function "-" ( L: in complex_polar; R: in complex_polar) return complex; function "-" ( L: in complex_polar; R: in complex ) return complex; function "-" ( L: in complex; R: in complex_polar) return complex; function "-" ( L: in real; R: in complex ) return complex; function "-" ( L: in complex; R: in real ) return complex; function "-" ( L: in real; R: in complex_polar) return complex; function "-" ( L: in complex_polar; R: in real) return complex; function "*" ( L: in complex; R: in complex ) return complex; function "*" ( L: in complex_polar; R: in complex_polar) return complex; function "*" ( L: in complex_polar; R: in complex ) return complex; function "*" ( L: in complex; R: in complex_polar) return complex; function "*" ( L: in real; R: in complex ) return complex; function "*" ( L: in complex; R: in real ) return complex; function "*" ( L: in real; R: in complex_polar) return complex; function "*" ( L: in complex_polar; R: in real) return complex; function "/" ( L: in complex; R: in complex ) return complex; function "/" ( L: in complex_polar; R: in complex_polar) return complex; function "/" ( L: in complex_polar; R: in complex ) return complex; function "/" ( L: in complex; R: in complex_polar) return complex; function "/" ( L: in real; R: in complex ) return complex; function "/" ( L: in complex; R: in real ) return complex; function "/" ( L: in real; R: in complex_polar) return complex; function "/" ( L: in complex_polar; R: in real) return complex; end MATH_COMPLEX; From jose@Synopsys.COM Fri Oct 14 15:48:06 1994 Return-Path: Received: from chronos.synopsys.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA02535; Fri, 14 Oct 94 15:48:06 PDT Received: from gaea.synopsys.com by chronos.synopsys.com with SMTP id AA21848 (5.65c/IDA-1.4.4 for ); Fri, 14 Oct 1994 15:43:59 -0700 Received: from jose.synopsys.com by gaea.synopsys.com with SMTP id AA28918 (5.65c/IDA-1.4.4 for ); Fri, 14 Oct 1994 15:43:55 -0700 Received: by jose.synopsys.com (4.1/SNPS-Sub02) id AA24266; Fri, 14 Oct 94 15:43:54 PDT Date: Fri, 14 Oct 94 15:43:54 PDT From: jose@Synopsys.COM (Jose Torres) Message-Id: <9410142243.AA24266@jose.synopsys.com> To: math@vhdl.org Subject: VHDL math package (body) -- current version --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE BODY MATH_REAL -- -- Library: This package shall be compiled into a library -- symbolically named IEEE. -- -- Purpose: VHDL declarations for mathematical package MATH_REAL -- which contains common real constants, common real -- functions, and real trascendental functions. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- Source code and algorithms for this package body comes from the -- following sources: -- IEEE VHDL Math Package Study Group participants, -- U. of Mississippi, Mentor Graphics, Synopsys, -- Viewlogic/Vantage, Communications of the ACM (June 1988, Vol -- 31, Number 6, pp. 747, Pierre L'Ecuyer, Efficient and Portable -- Random Number Generators), Handbook of Mathematical Functions -- by Milton Abramowitz and Irene A. Stegun (Dover), Regents of -- the University of California. -- -- History: -- Version 0.1 Jose A. Torres 4/23/93 First draft -- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code -- Version 0.3 Jose A. Torres 11/21/93 Fixed code in log,ceil,floor -- and round -- Version 0.4 Jose A. Torres 9/2/94 Modified/fixed code in the -- following functions: -- ceil, floor, round, "**", -- exp, log, sqrt, cbrt, sin, cos, -- asin, acos, atan, atan2, tanh, -- acosh, atanh -- Version 0.9 Jose A. Torres 9/30/94 Rev'd up for distribution. -- and additional changes in sqrt ------------------------------------------------------------- Library IEEE; Package body MATH_REAL is -- -- some constants for use in the package body only -- constant Q_PI : real := MATH_PI/4.0; constant HALF_PI : real := MATH_PI/2.0; constant TWO_PI : real := MATH_PI*2.0; constant MAX_ITER: integer := 27; -- max precision factor for cordic constant MAX_COUNT: integer := 50; -- max count for number of tries constant MIN_EPS: real := 0.000001; -- min eps for convergence criteria -- -- some type declarations for cordic operations -- constant KC : REAL := 6.0725293500888142e-01; -- constant for cordic type REAL_VECTOR is array (NATURAL range <>) of REAL; type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; subtype REAL_VECTOR_N is REAL_VECTOR (0 to max_iter); subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); subtype QUADRANT is INTEGER range 0 to 3; type CORDIC_MODE_TYPE is (ROTATION, VECTORING); -- -- auxiliary functions for cordic algorithms -- function POWER_OF_2_SERIES (d : NATURAL_VECTOR; initial_value : REAL; number_of_values : NATURAL) return REAL_VECTOR is variable v : REAL_VECTOR (0 to number_of_values); variable temp : REAL := initial_value; variable flag : boolean := true; begin for i in 0 to number_of_values loop v(i) := temp; for p in d'range loop if i = d(p) then flag := false; end if; end loop; if flag then temp := temp/2.0; end if; flag := true; end loop; return v; end POWER_OF_2_SERIES; constant two_at_minus : REAL_VECTOR := POWER_OF_2_SERIES( NATURAL_VECTOR'(100, 90),1.0, MAX_ITER); constant epsilon : REAL_VECTOR_N := ( 7.8539816339744827e-01, 4.6364760900080606e-01, 2.4497866312686413e-01, 1.2435499454676144e-01, 6.2418809995957351e-02, 3.1239833430268277e-02, 1.5623728620476830e-02, 7.8123410601011116e-03, 3.9062301319669717e-03, 1.9531225164788189e-03, 9.7656218955931937e-04, 4.8828121119489829e-04, 2.4414062014936175e-04, 1.2207031189367021e-04, 6.1035156174208768e-05, 3.0517578115526093e-05, 1.5258789061315760e-05, 7.6293945311019699e-06, 3.8146972656064960e-06, 1.9073486328101870e-06, 9.5367431640596080e-07, 4.7683715820308876e-07, 2.3841857910155801e-07, 1.1920928955078067e-07, 5.9604644775390553e-08, 2.9802322387695303e-08, 1.4901161193847654e-08, 7.4505805969238281e-09 ); function CORDIC ( x0 : REAL; y0 : REAL; z0 : REAL; n : NATURAL; -- precision factor CORDIC_MODE : CORDIC_MODE_TYPE -- rotation (z -> 0) -- or vectoring (y -> 0) ) return REAL_ARR_3 is variable x : REAL := x0; variable y : REAL := y0; variable z : REAL := z0; variable x_temp : REAL; begin if CORDIC_MODE = ROTATION then for k in 0 to n loop x_temp := x; if ( z >= 0.0) then x := x - y * two_at_minus(k); y := y + x_temp * two_at_minus(k); z := z - epsilon(k); else x := x + y * two_at_minus(k); y := y - x_temp * two_at_minus(k); z := z + epsilon(k); end if; end loop; else for k in 0 to n loop x_temp := x; if ( y < 0.0) then x := x - y * two_at_minus(k); y := y + x_temp * two_at_minus(k); z := z - epsilon(k); else x := x + y * two_at_minus(k); y := y - x_temp * two_at_minus(k); z := z + epsilon(k); end if; end loop; end if; return REAL_ARR_3'(x, y, z); end CORDIC; -- -- non-trascendental functions -- function SIGN (X: real ) return real is -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0 begin if ( X > 0.0 ) then return 1.0; elsif ( X < 0.0 ) then return -1.0; else return 0.0; end if; end SIGN; function CEIL (X : real ) return real is -- returns smallest integer value (as real) not less than X -- No conversion to an integer type is expected, so truncate cannot -- overflow for large arguments. variable large: real := 1073741824.0; type long is range -1073741824 to 1073741824; -- 2**30 is longer than any single-precision mantissa variable rd: real; begin if abs( X) >= large then return X; else rd := real ( long( X)); if X > 0.0 then if rd >= X then return rd; else return rd + 1.0; end if; elsif X = 0.0 then return 0.0; else if rd <= X then return rd + 1.0; else return rd; end if; end if; end if; end CEIL; function FLOOR (X : real ) return real is -- returns largest integer value (as real) not greater than X -- No conversion to an integer type is expected, so truncate -- cannot overflow for large arguments. -- variable large: real := 1073741824.0; type long is range -1073741824 to 1073741824; -- 2**30 is longer than any single-precision mantissa variable rd: real; begin if abs( X ) >= large then return X; else rd := real ( long( X)); if X > 0.0 then if rd <= X then return rd; else return rd - 1.0; end if; elsif X = 0.0 then return 0.0; else if rd >= X then return rd - 1.0; else return rd; end if; end if; end if; end FLOOR; function ROUND (X : real ) return real is -- returns integer FLOOR(X + 0.5) if X > 0; -- return integer CEIL(X - 0.5) if X < 0 begin if X > 0.0 then return FLOOR(X + 0.5); elsif X < 0.0 then return CEIL( X - 0.5); else return 0.0; end if; end ROUND; function FMAX (X, Y : real ) return real is -- returns the algebraically larger of X and Y begin if X > Y then return X; else return Y; end if; end FMAX; function FMIN (X, Y : real ) return real is -- returns the algebraically smaller of X and Y begin if X < Y then return X; else return Y; end if; end FMIN; -- -- Pseudo-random number generators -- procedure UNIFORM(variable Seed1,Seed2:inout integer;variable X:out real) is -- returns a pseudo-random number with uniform distribution in the -- interval (0.0, 1.0). -- Before the first call to UNIFORM, the seed values (Seed1, Seed2) must -- be initialized to values in the range [1, 2147483562] and -- [1, 2147483398] respectively. The seed values are modified after -- each call to UNIFORM. -- This random number generator is portable for 32-bit computers, and -- it has period ~2.30584*(10**18) for each set of seed values. -- variable z, k: integer; begin k := Seed1/53668; Seed1 := 40014 * (Seed1 - k * 53668) - k * 12211; if Seed1 < 0 then Seed1 := Seed1 + 2147483563; end if; k := Seed2/52774; Seed2 := 40692 * (Seed2 - k * 52774) - k * 3791; if Seed2 < 0 then Seed2 := Seed2 + 2147483399; end if; z := Seed1 - Seed2; if z < 1 then z := z + 2147483562; end if; X := REAL(Z)*4.656613e-10; end UNIFORM; function SRAND (seed: in integer ) return integer is -- -- sets value of seed for sequence of -- pseudo-random numbers. -- Returns the value of the seed. -- It uses the foreign native C function srand(). begin return(-1); -- *** dummy return value for VHDL compliance *** -- (actual return value is the one generated by -- the C function srand()) end SRAND; function RAND return integer is -- -- returns an integer pseudo-random number with uniform distribution. -- It uses the foreign native C function rand(). -- Seed for the sequence is initialized with the -- SRAND() function and value of the seed is changed every -- time SRAND() is called, but it is not visible. -- The range of generated values is platform dependent. begin return(-1); -- *** dummy return value for VHDL compliance *** -- (actual return value is the one generated by -- the C function rand()) end RAND; function GET_RAND_MAX return integer is -- -- returns the upper bound of the range of the -- pseudo-random numbers generated by RAND(). -- The support for this function is platform dependent, and -- it uses foreign native C functions or constants. -- It may not be available in some platforms. -- Note: the value of (RAND / GET_RAND_MAX) is a -- pseudo-random number distributed between 0 & 1. begin return(-1); -- *** dummy return value for VHDL compliance *** -- (actual return value is a function of the platform) end GET_RAND_MAX; -- -- trascendental and trigonometric functions -- function SQRT (X : real ) return real is -- returns square root of X; X >= 0 -- -- Computes square root using the Newton-Raphson approximation: -- F(n+1) = 0.5*[F(n) + x/F(n)]; -- constant eps : real := MIN_EPS; constant relative_err : real := eps*X; variable count : integer := 1; variable inival: real; variable oldval : real ; variable newval : real ; begin -- check validity of argument if ( X < 0.0 ) then assert false report "X < 0 in SQRT(X)" severity ERROR; return (0.0); end if; -- get the square root for special cases if X = 0.0 then return 0.0; else if ( X = 1.0 ) then return 1.0; -- return exact value end if; end if; -- get the square root for general cases inival := exp(log(x)*(0.5)); -- Mathematically correct but imprecise oldval := inival; newval := (X/oldval + oldval)/2.0; -- check for both absolute and relative error while ( (( abs(newval -oldval) > eps ) OR ( abs(newval -oldval) > relative_err)) AND ( count < MAX_COUNT ) ) loop oldval := newval; newval := (X/oldval + oldval)/2.0; count := count + 1; -- for future use if a count limit needed end loop; return newval; end SQRT; function CBRT (X : real ) return real is -- returns cube root of X -- Computes square root using the Newton-Raphson approximation: -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; -- constant eps : real := MIN_EPS; constant relative_err : real := eps*abs(X); variable inival: real; variable xlocal : real := X; variable negative : boolean := X < 0.0; variable oldval : real ; variable newval : real ; variable count : integer := 1; begin -- compute root for special cases if X = 0.0 then return 0.0; elsif ( X = 1.0 ) then return 1.0; else if X = -1.0 then return -1.0; end if; end if; -- compute root for general cases if negative then xlocal := -X; end if; inival := exp(log(xlocal)/(3.0)); -- mathematically correct but -- imprecise oldval := inival; newval := (xlocal/(oldval*oldval) + 2.0*oldval)/3.0; -- check for absolut and relative errors and max count while ( (( abs(newval -oldval) > eps ) OR ( abs(newval -oldval) > relative_err)) AND ( count < MAX_COUNT ) ) loop oldval := newval; newval :=(xlocal/(oldval*oldval) + 2.0*oldval)/3.0; count := count + 1; end loop; if negative then newval := -newval; end if; return newval; end CBRT; function "**" (X : integer; Y : real) return real is -- returns Y power of X ==> X**Y; -- error if X = 0 and Y <= 0.0 -- error if X < 0 and Y does not have an integer value begin -- check validity of argument if ( X = 0 ) and ( Y <= 0.0 ) then assert false report "X = 0 and Y <= 0.0 in X**Y" severity ERROR; return (0.0); end if; if ( X < 0 ) and ( Y /= REAL(INTEGER(Y)) ) then assert false report "X < 0 and Y \= integer in X**Y" severity ERROR; return (0.0); end if; -- compute the result if ( X = 0 ) then return (0.0); end if; return EXP (Y * LOG (REAL(X))); end "**"; function "**" (X : real; Y : real) return real is -- returns Y power of X ==> X**Y; -- error if X = 0.0 and Y <= 0.0 -- error if X < 0.0 and Y does not have an integer value begin -- check validity of argument if ( X = 0.0 ) and ( Y <= 0.0 ) then assert false report "X = 0.0 and Y <= 0.0 in X**Y" severity ERROR; return (0.0); end if; if ( X < 0.0 ) and ( Y /= REAL(INTEGER(Y)) ) then assert false report "X < 0.0 and Y \= integer in X**Y" severity ERROR; return (0.0); end if; -- compute the result if ( X = 0.0 ) then return (0.0); end if; return EXP (Y * LOG (X)); end "**"; function EXP (X : real ) return real is -- returns e**X; where e = MATH_E -- -- This function computes the exponential using the following series: -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; x > 0 -- constant eps : real := MIN_EPS; -- precision criteria variable reciprocal: boolean := x < 0.0;-- check sign of argument variable xlocal : real := abs(x); -- use positive value variable oldval: real ; -- following variables are variable count: integer ; variable newval: real ; variable last_term: real ; begin -- compute value for special cases if X = 0.0 then return 1.0; else if X = 1.0 then return MATH_E; end if; end if; -- compute value for general cases oldval := 1.0; last_term := xlocal; newval:= oldval + last_term; count := 2; while ( abs(newval - oldval) > eps OR count < MAX_COUNT ) loop if reciprocal and newval > 1.0E19 then return 0.0; end if; oldval := newval; last_term := (last_term / (real(count))) * xlocal; newval := oldval + last_term; count := count + 1; end loop; if reciprocal then newval := 1.0/newval; end if; return newval; end EXP; -- -- auxiliary functions to compute LOG -- function ILOGB(X: real) return integer IS --return n such that --1 <= abs(x)/2^n < 2 variable n: integer := 0; variable y: real := abs(x); begin if(y = 1.0 or y = 0.0) then return 0; end if; if( y > 1.0) then while y >= 2.0 loop y := y/2.0; n := n+1; end loop; return n; end if; -- O < y < 1 while y < 1.0 loop y := y*2.0; n := n -1; end loop; return n; end ILOGB; function LDEXP(x:real; n:integer) RETURN real IS --return x*2^n begin return x*(2.0 ** n); end LDEXP; function LOG (X : real ) return real IS -- Copyright (c) 1992 Regents of the University of California. -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- 3. All advertising materials mentioning features or use of this -- software must display the following acknowledgement: -- This product includes software developed by the University of -- California, Berkeley and its contributors. -- 4. Neither the name of the University nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -- DAMAGE. -- -- NOTE: This VHDL version was generated using the C version of the -- original function by the IEEE VHDL Mathematical Package -- Working Group (CS/JT) constant N: integer := 128; -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. -- Used for generation of extend precision logarithms. -- The constant 35184372088832 is 2^45, so the divide is exact. -- It ensures correct reading of logF_head, even for inaccurate -- decimal-to-binary conversion routines. (Everybody gets the -- right answer for integers less than 2^53.) -- Values for log(F) were generated using error < 10^-57 absolute -- with the bc -l package. type REAL_VECTOR is array (NATURAL range <>) of REAL; constant A1:real := 0.08333333333333178827; constant A2:real := 0.01250000000377174923; constant A3:real := 0.002232139987919447809; constant A4:real := 0.0004348877777076145742; constant logF_head:real_vector(0 TO N) := ( 0.0, 0.007782140442060381246, 0.015504186535963526694, 0.023167059281547608406, 0.030771658666765233647, 0.038318864302141264488, 0.045809536031242714670, 0.053244514518837604555, 0.060624621816486978786, 0.067950661908525944454, 0.075223421237524235039, 0.082443669210988446138, 0.089612158689760690322, 0.096729626458454731618, 0.103796793681567578460, 0.110814366340264314203, 0.117783035656430001836, 0.124703478501032805070, 0.131576357788617315236, 0.138402322859292326029, 0.145182009844575077295, 0.151916042025732167530, 0.158605030176659056451, 0.165249572895390883786, 0.171850256926518341060, 0.178407657472689606947, 0.184922338493834104156, 0.191394852999565046047, 0.197825743329758552135, 0.204215541428766300668, 0.210564769107350002741, 0.216873938300523150246, 0.223143551314024080056, 0.229374101064877322642, 0.235566071312860003672, 0.241719936886966024758, 0.247836163904594286577, 0.253915209980732470285, 0.259957524436686071567, 0.265963548496984003577, 0.271933715484010463114, 0.277868451003087102435, 0.283768173130738432519, 0.289633292582948342896, 0.295464212893421063199, 0.301261330578199704177, 0.307025035294827830512, 0.312755710004239517729, 0.318453731118097493890, 0.324119468654316733591, 0.329753286372579168528, 0.335355541920762334484, 0.340926586970454081892, 0.346466767346100823488, 0.351976423156884266063, 0.357455888922231679316, 0.362905493689140712376, 0.368325561158599157352, 0.373716409793814818840, 0.379078352934811846353, 0.384411698910298582632, 0.389716751140440464951, 0.394993808240542421117, 0.400243164127459749579, 0.405465108107819105498, 0.410659924985338875558, 0.415827895143593195825, 0.420969294644237379543, 0.426084395310681429691, 0.431173464818130014464, 0.436236766774527495726, 0.441274560805140936281, 0.446287102628048160113, 0.451274644139630254358, 0.456237433481874177232, 0.461175715122408291790, 0.466089729924533457960, 0.470979715219073113985, 0.475845904869856894947, 0.480688529345570714212, 0.485507815781602403149, 0.490303988045525329653, 0.495077266798034543171, 0.499827869556611403822, 0.504556010751912253908, 0.509261901790523552335, 0.513945751101346104405, 0.518607764208354637958, 0.523248143765158602036, 0.527867089620485785417, 0.532464798869114019908, 0.537041465897345915436, 0.541597282432121573947, 0.546132437597407260909, 0.550647117952394182793, 0.555141507540611200965, 0.559615787935399566777, 0.564070138285387656651, 0.568504735352689749561, 0.572919753562018740922, 0.577315365035246941260, 0.581691739635061821900, 0.586049045003164792433, 0.590387446602107957005, 0.594707107746216934174, 0.599008189645246602594, 0.603290851438941899687, 0.607555250224322662688, 0.611801541106615331955, 0.616029877215623855590, 0.620240409751204424537, 0.624433288012369303032, 0.628608659422752680256, 0.632766669570628437213, 0.636907462236194987781, 0.641031179420679109171, 0.645137961373620782978, 0.649227946625615004450, 0.653301272011958644725, 0.657358072709030238911, 0.661398482245203922502, 0.665422632544505177065, 0.669430653942981734871, 0.673422675212350441142, 0.677398823590920073911, 0.681359224807238206267, 0.685304003098281100392, 0.689233281238557538017, 0.693147180560117703862); constant logF_tail:real_vector(0 TO N) := ( 0.0, -0.00000000000000543229938420049, 0.00000000000000172745674997061, -0.00000000000001323017818229233, -0.00000000000001154527628289872, -0.00000000000000466529469958300, 0.00000000000005148849572685810, -0.00000000000002532168943117445, -0.00000000000005213620639136504, -0.00000000000001819506003016881, 0.00000000000006329065958724544, 0.00000000000008614512936087814, -0.00000000000007355770219435028, 0.00000000000009638067658552277, 0.00000000000007598636597194141, 0.00000000000002579999128306990, -0.00000000000004654729747598444, -0.00000000000007556920687451336, 0.00000000000010195735223708472, -0.00000000000017319034406422306, -0.00000000000007718001336828098, 0.00000000000010980754099855238, -0.00000000000002047235780046195, -0.00000000000008372091099235912, 0.00000000000014088127937111135, 0.00000000000012869017157588257, 0.00000000000017788850778198106, 0.00000000000006440856150696891, 0.00000000000016132822667240822, -0.00000000000007540916511956188, -0.00000000000000036507188831790, 0.00000000000009120937249914984, 0.00000000000018567570959796010, -0.00000000000003149265065191483, -0.00000000000009309459495196889, 0.00000000000017914338601329117, -0.00000000000001302979717330866, 0.00000000000023097385217586939, 0.00000000000023999540484211737, 0.00000000000015393776174455408, -0.00000000000036870428315837678, 0.00000000000036920375082080089, -0.00000000000009383417223663699, 0.00000000000009433398189512690, 0.00000000000041481318704258568, -0.00000000000003792316480209314, 0.00000000000008403156304792424, -0.00000000000034262934348285429, 0.00000000000043712191957429145, -0.00000000000010475750058776541, -0.00000000000011118671389559323, 0.00000000000037549577257259853, 0.00000000000013912841212197565, 0.00000000000010775743037572640, 0.00000000000029391859187648000, -0.00000000000042790509060060774, 0.00000000000022774076114039555, 0.00000000000010849569622967912, -0.00000000000023073801945705758, 0.00000000000015761203773969435, 0.00000000000003345710269544082, -0.00000000000041525158063436123, 0.00000000000032655698896907146, -0.00000000000044704265010452446, 0.00000000000034527647952039772, -0.00000000000007048962392109746, 0.00000000000011776978751369214, -0.00000000000010774341461609578, 0.00000000000021863343293215910, 0.00000000000024132639491333131, 0.00000000000039057462209830700, -0.00000000000026570679203560751, 0.00000000000037135141919592021, -0.00000000000017166921336082431, -0.00000000000028658285157914353, -0.00000000000023812542263446809, 0.00000000000006576659768580062, -0.00000000000028210143846181267, 0.00000000000010701931762114254, 0.00000000000018119346366441110, 0.00000000000009840465278232627, -0.00000000000033149150282752542, -0.00000000000018302857356041668, -0.00000000000016207400156744949, 0.00000000000048303314949553201, -0.00000000000071560553172382115, 0.00000000000088821239518571855, -0.00000000000030900580513238244, -0.00000000000061076551972851496, 0.00000000000035659969663347830, 0.00000000000035782396591276383, -0.00000000000046226087001544578, 0.00000000000062279762917225156, 0.00000000000072838947272065741, 0.00000000000026809646615211673, -0.00000000000010960825046059278, 0.00000000000002311949383800537, -0.00000000000058469058005299247, -0.00000000000002103748251144494, -0.00000000000023323182945587408, -0.00000000000042333694288141916, -0.00000000000043933937969737844, 0.00000000000041341647073835565, 0.00000000000006841763641591466, 0.00000000000047585534004430641, 0.00000000000083679678674757695, -0.00000000000085763734646658640, 0.00000000000021913281229340092, -0.00000000000062242842536431148, -0.00000000000010983594325438430, 0.00000000000065310431377633651, -0.00000000000047580199021710769, -0.00000000000037854251265457040, 0.00000000000040939233218678664, 0.00000000000087424383914858291, 0.00000000000025218188456842882, -0.00000000000003608131360422557, -0.00000000000050518555924280902, 0.00000000000078699403323355317, -0.00000000000067020876961949060, 0.00000000000016108575753932458, 0.00000000000058527188436251509, -0.00000000000035246757297904791, -0.00000000000018372084495629058, 0.00000000000088606689813494916, 0.00000000000066486268071468700, 0.00000000000063831615170646519, 0.00000000000025144230728376072, -0.00000000000017239444525614834); variable m, j:integer; variable F1, f2, g, q, u, u2, v: real; variable zero:real := 0.0;--made variable so no constant folding occurs variable one:real := 1.0; --made variable so no constant folding occurs -- double logb(), ldexp(); variable u1:real; begin -- check validity of argument if ( x <= 0.0 ) then assert false report "X <= 0 in LOG(X)" severity ERROR; return(REAL'LOW); end if; -- Argument reduction: 1 <= g < 2; x/2^m = g; -- y = F*(1 + f/F) for |f| <= 2^-8 m := ilogb(x); g := ldexp(x, -m); j := integer(real(N)*(g-1.0)); -- C code adds 0.5 for rounding F1 := (1.0/real(N)) * real(j) + 1.0; --F1*128 is an integer in [128,512] f2 := g - F1; -- Approximate expansion for log(1+f2/F1) ~= u + q g := 1.0/(2.0*F1+f2); u := 2.0*f2*g; v := u*u; q := u*v*(A1 + v*(A2 + v*(A3 + v*A4))); -- case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750 -- if ( j /= 0 or m /= 0) then u1 := u + 513.0; u1 := u1 - 513.0; -- case 2: |1-x| < 1/256.The m- and j- dependent terms are zero -- u1 = u to 24 bits. -- else u1 := u; --TRUNC(u1); --in c this is u1 = (double) (float) (u1) end if; u2 := (2.0*(f2 - F1*u1) - u1*f2) * g; -- u1 + u2 = 2f/(2F+f) to extra precision. -- log(x) = log(2^m*F1*(1+f2/F1)) = -- (m*log2_hi+logF_head(j)+u1) + (m*log2_lo+logF_tail(j)+q); -- (exact) + (tiny) u1 := u1 + real(m)*logF_head(N) + logF_head(j); -- exact u2 := (u2 + logF_tail(j)) + q; -- tiny u2 := u2 + logF_tail(N)*real(m); return (u1 + u2); end LOG; function LOG (BASE: positive; X : real) return real is -- returns logarithm base BASE of X; X > 0 begin -- check validity of argument if ( x <= 0.0 ) then assert false report "X <= 0.0 in LOG(BASE, X)" severity ERROR; return(REAL'LOW); end if; -- compute the value return ( LOG(X)/LOG(REAL(BASE))); end LOG; function SIN (X : real ) return real is -- returns sin X; X in radians variable n : INTEGER; variable nx : real; constant eps : real := MIN_EPS; begin if (abs(x) < eps) then return (0.0); elsif ( x > 0.0) then nx := x / MATH_PI; nx := nx - floor(nx); if (nx < eps) then return (0.0); end if; else nx := x / MATH_PI; nx := nx - ceil(nx); if (abs(nx) < eps) then return (0.0); end if; end if; if (x < 1.6 ) and (x > -1.6) then return CORDIC( KC, 0.0, x, 27, ROTATION)(1); end if; n := INTEGER( x / HALF_PI ); case QUADRANT( n mod 4 ) is when 0 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 1 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 2 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 3 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); end case; end SIN; function COS (x : REAL) return REAL is -- returns cos X; X in radians variable n : INTEGER; variable xlocal, int_part : real; constant eps : real := MIN_EPS; begin if (abs(x) = HALF_PI) then return (0.0); elsif ( x > 0.0) then xlocal := x / HALF_PI; int_part := floor(xlocal); xlocal := xlocal - int_part; if (xlocal < eps) and ((INTEGER(int_part) rem 2) = 1) then return (0.0); end if; else xlocal := x / HALF_PI; int_part := ceil(xlocal); xlocal := xlocal - int_part; if (abs(xlocal) < eps) and ((INTEGER(int_part) rem 2) = 1) then return (0.0); end if; end if; if (x < 1.6 ) and (x > -1.6) then return CORDIC( KC, 0.0, x, 27, ROTATION)(0); end if; n := INTEGER( x / HALF_PI ); case QUADRANT( n mod 4 ) is when 0 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 1 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); when 2 => return -CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(0); when 3 => return CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION)(1); end case; end COS; function TAN (x : REAL) return REAL is -- returns tan X; X in radians -- X /= ((2k+1) * PI/2), where k is an integer variable n : INTEGER := INTEGER( x / HALF_PI ); variable v : REAL_ARR_3 := CORDIC( KC, 0.0, x - REAL(n) * HALF_PI, 27, ROTATION); begin if n mod 2 = 0 then return v(1)/v(0); else return -v(0)/v(1); end if; end TAN; function ASIN (x : real ) return real is -- returns -PI/2 < asin X < PI/2; | X | <= 1 begin if abs x > 1.0 then assert false report "Out of range parameter passed to ASIN" severity ERROR; return x; elsif abs x = 0.0 then return 0.0; elsif abs x < 0.9 then return atan(x/(sqrt(1.0 - x*x))); elsif x > 0.0 then return HALF_PI - atan(sqrt(1.0 - x*x)/x); else return - HALF_PI + atan((sqrt(1.0 - x*x))/x); end if; end ASIN; function ACOS (x : REAL) return REAL is -- returns 0 < acos X < PI; | X | <= 1 begin if abs x > 1.0 then assert false report "Out of range parameter passed to ACOS" severity ERROR; return x; elsif abs x = 1.0 then return 0.0; elsif abs x > 0.9 then if x > 0.0 then return atan(sqrt(1.0 - x*x)/x); else return MATH_PI - atan(sqrt(1.0 - x*x)/x); end if; else return HALF_PI - atan(x/sqrt(1.0 - x*x)); end if; end ACOS; function ATAN (x : REAL) return REAL is -- returns -PI/2 < atan X < PI/2 begin return CORDIC( 1.0, x, 0.0, 27, VECTORING )(2); end ATAN; function ATAN2 (x : REAL; y : REAL) return REAL is -- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0 begin if y = 0.0 then assert false report "atan2(x, 0.0) is undetermined, returned 0,0" severity NOTE; return 0.0; end if; if x = 0.0 then if y > 0.0 then return 0.0; else return MATH_PI; end if; end if; if y > 0.0 then if x > 0.0 then return CORDIC( y, x, 0.0, 27, VECTORING )(2); else return -CORDIC( y, -x, 0.0, 27, VECTORING )(2); end if; else if x > 0.0 then return MATH_PI - CORDIC( -y, x, 0.0, 27, VECTORING )(2); else return -MATH_PI + CORDIC( -y, -x, 0.0, 27, VECTORING )(2); end if; end if; end ATAN2; function SINH (X : real) return real is -- hyperbolic sine; returns (e**X - e**(-X))/2 begin return ( (EXP(X) - EXP(-X))/2.0 ); end SINH; function COSH (X : real) return real is -- hyperbolic cosine; returns (e**X + e**(-X))/2 begin return ( (EXP(X) + EXP(-X))/2.0 ); end COSH; function TANH (X : real) return real is -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X)) variable xlocal, pos_result: real; variable negative: boolean; begin negative := ( x < 0.0); if negative then xlocal := -x; else xlocal := x; end if; if ( xlocal <= 1.0e-10 ) then pos_result := xlocal; elsif ( xlocal > 22.0 ) then pos_result := 1.0; else pos_result := (EXP(xlocal)-EXP(-xlocal))/(EXP(xlocal)+EXP(-xlocal)); end if; if negative then return -pos_result; else return pos_result; end if; end TANH; function ASINH (X : real) return real is -- returns ln( X + sqrt( X**2 + 1)) begin return ( LOG( X + SQRT( X**2 + 1.0)) ); end ASINH; function ACOSH (X : real) return real is -- returns ln( X + sqrt( X**2 - 1)); X >= 1 begin if abs x < 1.0 then assert false report "Out of range parameter passed to ACOSH" severity ERROR; return x; end if; return ( LOG( X + SQRT( X**2 - 1.0)) ); end ACOSH; function ATANH (X : real) return real is -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1 begin if abs x >= 1.0 then assert false report "Out of range parameter passed to ATANH" severity ERROR; return x; end if; return( LOG( (1.0+X)/(1.0-X) )/2.0 ); end ATANH; end MATH_REAL; --------------------------------------------------------------- -- -- This source file may be used and distributed without restriction. -- No declarations or definitions shall be included in this package. -- This package cannot be sold or distributed for profit. -- -- **************************************************************** -- * * -- * W A R N I N G * -- * * -- * This DRAFT version IS NOT endorsed or approved by IEEE * -- * * -- **************************************************************** -- -- Title: PACKAGE BODY MATH_COMPLEX -- -- Purpose: VHDL declarations for mathematical package MATH_COMPLEX -- which contains common complex constants and basic complex -- functions and operations. -- -- Author: IEEE VHDL Math Package Study Group -- -- Notes: -- The package body uses package IEEE.MATH_REAL -- -- The package body shall be considered the formal definition of -- the semantics of this package. Tool developers may choose to implement -- the package body in the most efficient manner available to them. -- -- Source code for this package body comes from the following -- following sources: -- IEEE VHDL Math Package Study Group participants, -- U. of Mississippi, Mentor Graphics, Synopsys, -- Viewlogic/Vantage -- -- History: -- Version 0.1 Jose A. Torres 4/23/93 First draft -- Version 0.2 Jose A. Torres 5/28/93 Fixed potentially illegal code -- Version 0.3 Jose A. Torres 9/2/94 Fixed COMPLEX_TO_POLAR() -- Version 0.9 Jose A. Torres 9/30/94 Rev'd up for distribution -- ------------------------------------------------------------- Library IEEE; Use IEEE.MATH_REAL.all; -- real trascendental operations Package body MATH_COMPLEX is function CABS(Z: in complex ) return real is -- returns absolute value (magnitude) of Z variable ztemp : complex_polar; begin ztemp := COMPLEX_TO_POLAR(Z); return ztemp.mag; end CABS; function CARG(Z: in complex ) return real is -- returns argument (angle) in radians of a complex number variable ztemp : complex_polar; begin ztemp := COMPLEX_TO_POLAR(Z); return ztemp.arg; end CARG; function CMPLX(X: in real; Y: in real := 0.0 ) return complex is -- returns complex number X + iY begin return COMPLEX'(X, Y); end CMPLX; function "-" (Z: in complex ) return complex is -- unary minus; returns -x -jy for z= x + jy begin return COMPLEX'(-z.Re, -z.Im); end "-"; function "-" (Z: in complex_polar ) return complex_polar is -- unary minus; returns (z.mag, z.arg + MATH_PI) begin return COMPLEX_POLAR'(z.mag, z.arg + MATH_PI); end "-"; function CONJ (Z: in complex) return complex is -- returns complex conjugate (x-jy for z = x+ jy) begin return COMPLEX'(z.Re, -z.Im); end CONJ; function CONJ (Z: in complex_polar) return complex_polar is -- returns complex conjugate (z.mag, -z.arg) begin return COMPLEX_POLAR'(z.mag, -z.arg); end CONJ; function CSQRT(Z: in complex ) return complex_vector is -- returns square root of Z; 2 values variable ztemp : complex_polar; variable zout : complex_vector (0 to 1); variable temp : real; begin ztemp := COMPLEX_TO_POLAR(Z); temp := SQRT(ztemp.mag); zout(0).re := temp*COS(ztemp.arg/2.0); zout(0).im := temp*SIN(ztemp.arg/2.0); zout(1).re := temp*COS(ztemp.arg/2.0 + MATH_PI); zout(1).im := temp*SIN(ztemp.arg/2.0 + MATH_PI); return zout; end CSQRT; function CEXP(Z: in complex ) return complex is -- returns e**Z begin return COMPLEX'(EXP(Z.re)*COS(Z.im), EXP(Z.re)*SIN(Z.im)); end CEXP; function COMPLEX_TO_POLAR(Z: in complex ) return complex_polar is -- converts complex to complex_polar begin if ( z.re = 0.0 ) then if ( z.im = 0.0 ) then return COMPLEX_POLAR'(0.0, 0.0); elsif ( z.im > 0.0 ) then return COMPLEX_POLAR'(z.im, MATH_PI/2.0); else return COMPLEX_POLAR'(-z.im, -MATH_PI/2.0); end if; end if; return COMPLEX_POLAR'(sqrt(z.re**2 + z.im**2),atan2(z.im,z.re)); end COMPLEX_TO_POLAR; function POLAR_TO_COMPLEX(Z: in complex_polar ) return complex is -- converts complex_polar to complex begin return COMPLEX'( z.mag*cos(z.arg), z.mag*sin(z.arg) ); end POLAR_TO_COMPLEX; -- -- arithmetic operators -- function "+" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re + R.Re, L.Im + R.Im); end "+"; function "+" (L: in complex_polar; R: in complex_polar) return complex is variable zL, zR : complex; begin zL := POLAR_TO_COMPLEX( L ); zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(zL.Re + zR.Re, zL.Im + zR.Im); end "+"; function "+" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re + R.Re, zL.Im + R.Im); end "+"; function "+" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re + zR.Re, L.Im + zR.Im); end "+"; function "+" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L + R.Re, R.Im); end "+"; function "+" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re + R, L.Im); end "+"; function "+" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L + zR.Re, zR.Im); end "+"; function "+" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re + R, zL.Im); end "+"; function "-" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re - R.Re, L.Im - R.Im); end "-"; function "-" ( L: in complex_polar; R: in complex_polar) return complex is variable zL, zR : complex; begin zL := POLAR_TO_COMPLEX( L ); zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(zL.Re - zR.Re, zL.Im - zR.Im); end "-"; function "-" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re - R.Re, zL.Im - R.Im); end "-"; function "-" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re - zR.Re, L.Im - zR.Im); end "-"; function "-" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L - R.Re, -1.0 * R.Im); end "-"; function "-" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re - R, L.Im); end "-"; function "-" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L - zR.Re, -1.0*zR.Im); end "-"; function "-" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re - R, zL.Im); end "-"; function "*" ( L: in complex; R: in complex ) return complex is begin return COMPLEX'(L.Re * R.Re - L.Im * R.Im, L.Re * R.Im + L.Im * R.Re); end "*"; function "*" ( L: in complex_polar; R: in complex_polar) return complex is variable zout : complex_polar; begin zout.mag := L.mag * R.mag; zout.arg := L.arg + R.arg; return POLAR_TO_COMPLEX(zout); end "*"; function "*" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re*R.Re - zL.Im * R.Im, zL.Re * R.Im + zL.Im*R.Re); end "*"; function "*" ( L: in complex; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L.Re*zR.Re - L.Im * zR.Im, L.Re * zR.Im + L.Im*zR.Re); end "*"; function "*" ( L: in real; R: in complex ) return complex is begin return COMPLEX'(L * R.Re, L * R.Im); end "*"; function "*" ( L: in complex; R: in real ) return complex is begin return COMPLEX'(L.Re * R, L.Im * R); end "*"; function "*" ( L: in real; R: in complex_polar) return complex is variable zR : complex; begin zR := POLAR_TO_COMPLEX( R ); return COMPLEX'(L * zR.Re, L * zR.Im); end "*"; function "*" ( L: in complex_polar; R: in real) return complex is variable zL : complex; begin zL := POLAR_TO_COMPLEX( L ); return COMPLEX'(zL.Re * R, zL.Im * R); end "*"; function "/" ( L: in complex; R: in complex ) return complex is variable magrsq : REAL := R.Re ** 2 + R.Im ** 2; begin if (magrsq = 0.0) then assert FALSE report "Attempt to divide by (0,0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'( (L.Re * R.Re + L.Im * R.Im) / magrsq, (L.Im * R.Re - L.Re * R.Im) / magrsq); end if; end "/"; function "/" ( L: in complex_polar; R: in complex_polar) return complex is variable zout : complex_polar; begin if (R.mag = 0.0) then assert FALSE report "Attempt to divide by (0,0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else zout.mag := L.mag/R.mag; zout.arg := L.arg - R.arg; return POLAR_TO_COMPLEX(zout); end if; end "/"; function "/" ( L: in complex_polar; R: in complex ) return complex is variable zL : complex; variable temp : REAL := R.Re ** 2 + R.Im ** 2; begin if (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else zL := POLAR_TO_COMPLEX( L ); return COMPLEX'( (zL.Re * R.Re + zL.Im * R.Im) / temp, (zL.Im * R.Re - zL.Re * R.Im) / temp); end if; end "/"; function "/" ( L: in complex; R: in complex_polar) return complex is variable zR : complex := POLAR_TO_COMPLEX( R ); variable temp : REAL := zR.Re ** 2 + zR.Im ** 2; begin if (R.mag = 0.0) or (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'( (L.Re * zR.Re + L.Im * zR.Im) / temp, (L.Im * zR.Re - L.Re * zR.Im) / temp); end if; end "/"; function "/" ( L: in real; R: in complex ) return complex is variable temp : REAL := R.Re ** 2 + R.Im ** 2; begin if (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else temp := L / temp; return COMPLEX'( temp * R.Re, -temp * R.Im ); end if; end "/"; function "/" ( L: in complex; R: in real ) return complex is begin if (R = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'(L.Re / R, L.Im / R); end if; end "/"; function "/" ( L: in real; R: in complex_polar) return complex is variable zR : complex := POLAR_TO_COMPLEX( R ); variable temp : REAL := zR.Re ** 2 + zR.Im ** 2; begin if (R.mag = 0.0) or (temp = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else temp := L / temp; return COMPLEX'( temp * zR.Re, -temp * zR.Im ); end if; end "/"; function "/" ( L: in complex_polar; R: in real) return complex is variable zL : complex := POLAR_TO_COMPLEX( L ); begin if (R = 0.0) then assert FALSE report "Attempt to divide by (0.0,0.0)" severity ERROR; return COMPLEX'(REAL'RIGHT, REAL'RIGHT); else return COMPLEX'(zL.Re / R, zL.Im / R); end if; end "/"; end MATH_COMPLEX; From jose Mon Oct 17 10:58:16 1994 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07571; Mon, 17 Oct 94 10:58:16 PDT Date: Mon, 17 Oct 94 10:58:16 PDT From: jose (Jose Torres) Message-Id: <9410171758.AA07571@vhdl.vhdl.org> To: analog, isac, math, parallel, tac, vhdledif, vhdlsynth, vital, waves Subject: Call for participants in the VHDL Math Package balloting group ************************************************************************* ATTENTION! STANDARD VHDL MATHEMATICAL PACKAGES ARE COMING .... ************************************************************************* YOU ARE INVITED TO PARTICIPATE IN THE BALLOTING GROUP for STANDARDIZING VHDL MATHEMATICAL PACKAGES. IF INTERESTED, PLEASE USE THE APPLICATION FORM that appears below. "CUT" along the dotted line, fill out the form and either: Send a hard copy by mail to Rosemary Tennis at the address given at the bottom, or Fax it to Rosemary Tennis at 908-562-1571, or E-mail to rtennis@stdsmail.ieee.org For e-mail, please make sure to enter Re: P1076.2 in the subject line. If you are interested in previewing the packages, these can be downloaded from the vhdl.org machine. The packages are in ftp: //vhdl.org/vi/math/package/math_head.9.30.94.vhd //vhdl.org/vi/math/package/math_body.9.30.94.vhd or //vhdl.org/vi/math/package/math_package.tar.Z or in other words: ftp vhdl.org username: anonymous password: ftp> cd /vi/math/package ftp> get math_package.tar.Z ftp> bye Please send all technical feedback on these packages to: math-request@vhdl.org Thank you, - Jose A. Torres, Working Group Chair, PAR 1076.2 (jose@vhdl.org) ----------------------------- cut here ---------------------------------------- The Design Automation Standards Committee of the IEEE Computer Society invites you to ballot on P1076.2: Standard VHDL Language Mathematical Package Return deadline: November 17, 1994 SCOPE: Definition of a set of standard mathematical packages for VHDL that include most oftenly used real and complex elementary functions. Examples are trigonometric, hyperbolic, random number generators, etc. PURPOSE:Many model descriptions need this type of mathematical functions. However, IEEE Standard 1076 does not provide as part of the language a pre-defined standard set of mathematical functions for this purpose. This Standard will define a set of packages, with a basic set of mathematical functions, to allow portability of VHDL descriptions that use this type of functionality. Your Category of Interest in this Standards Ballot (i.e., do you use or produce the items in this standard?): User__ Producer__ Academic__ General Interest__ (Note: Please choose only ONE of the above. If you have any combination of Interests, check the General Interest Category) Please Print Clearly: New address? Yes or No Name: Phone: Fax: Company: Mailing Address: EMail: Home address (important: confidential; it will only be used in case of returned mail): IEEE or Computer Society Membership Number_______________ Check here if not a member of IEEE or the Computer Society ______ Balloter's Responsibility If you become part of the balloting body, you will have 30 days to review and respond to the draft. In order for the Sponsor Ballot to be valid, at least 75% of the ballots sent must be returned. For that reason: VOTERS HAVE AN OBLIGATION TO RESPOND. Eligible voters are members of the IEEE or Computer Society and non-members will comment as Parties of Interest. For Membership Application, Call (908) 562-5524 Signature: Date: If you want confirmation that this form has been received by the IEEE Standards Office, please enclose a stamped, pre-addressed post card along with this form (if sent by mail) or indicate that you want a "return receipt" if sent by e-mail. ____Yes, I want to be part of the DASC Balloting Pool. Please return by November 17, 1994 to: Rosemary Tennis IEEE Standards Office 445 Hoes Lane, PO. Box 1331 Piscataway, NJ 08855-1331 Fax: 908/562-1571 From EEHANSON@VM.CC.OLEMISS.EDU Tue Feb 7 14:52:06 1995 Return-Path: Received: from VM.CC.OLEMISS.EDU by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA20145; Tue, 7 Feb 95 14:52:06 PST Message-Id: <9502072252.AA20145@vhdl.vhdl.org> Received: from VM.CC.OLEMISS.EDU by VM.CC.OLEMISS.EDU (IBM VM SMTP V2R2) with BSMTP id 5446; Tue, 07 Feb 95 16:46:25 CST Received: by UMSVM (Mailer R2.10 ptf000) id 2725; Tue, 07 Feb 95 16:46:24 CST Date: Tue, 07 Feb 95 16:45:22 CST From: Don Hanson Subject: Comments on FAXed Document To: Math Package Folks Cc: Jose Comments on FAXed IEEE VHDL Math Package - draft Under 2.1 Math_Real line 20 trascendental -> transcendental (sp) page 12 function "**" (X: integer; Y: real ) return real; --X**Y function "**" (X: real; Y: real ) return real; --X**Y We have (X: integer; Y: real ) and (X: real; Y: real ) do we need (X: integer; Y: integer ) and (X: real; Y: integer ) ?? or are these recommended to use the integer (Y) function explicitly. Page 13 previous functions have had error lines Do we need error lines for LOG, TAN, etc functions?? function LOG( X: real) return real; --returns natural logarithm of X; X>0 --error if X<=0 <<---?? Page 13 Should PI be MATH_PI in comments?? Page 13 function ASINH(X:real) return real; -- returns ln(x + sqrt( x**2 + 1 )) Should this comment be in the VHDL Math package style or otherwise?? -- return LOG(X + SQRT( X**2 + 1 )) NOTE: X**2 is not defined currently... we need a function-->> function "**" (X: real; Y: integer ) return real; --X**Y same for ACOSH and ATANH ?? Page 15 function CABS(Z: in complex) return real; -- return absolute value (magnitude) of Z Should we give the formula SQRT( Z.re**2 + Z.im**2 ) in another comment?? function CARG(Z: in complex) return real; -- returns argument (angle) in radians of a complex number Should we say: returns ATAN2(Z.re, Z.im) We have two functions with complex_polar returned... These are "-" and CONJ. As far as I can tell, these are the only functions with complex_polar returned besides the explicit COMPLEX_TO_POLAR function. Since all arithmetic operators return only complex and never complex_polar, it isn't clear why these are needed?? All arithmetic operations end up with a complex result. Why use complex_polar at all except for final output results?? Page 18.. A.4 Precision and convergence of functions in Math_Real The iterative nature of the algorithms is undesirable, and unneeded. The usual approach is to study the algorithm analytically for an upper bound to the error and take a FIXED number of terms. However, I have used the same basic algorithms that you are using with good success. Given the maximum error, one can find the maximum argument that can be used to within that error. So there is a tradeoff. Do you want to have maximum speed for small to medium arguments, or do you want maximum accuracy for all arguments. With a little analytical work, the values of the "counters" that stop the iteration can be found. I would prefer to see this work done--it is probably already done somewhere in the literature--than to imply that the functions are inaccurate. Further optimization of speed of the functions would require storing arrays of numbers, so that they would not have to be computed every time they are used, which is the algorithm you are using. The bodies that I am looking at were the last e-mailed to me:: The series for exp(x) that is used is exp(x) = 1+x+x**2/2!+x**3/3!+... x >0 This approach is asking for trouble. It is better to use that fact that: exp(x+y) = exp(x)*exp(y) There are many ways this can be used. For example, if y is made an integer value, then x is non-integral (in general) and this limits the range of the arguments exp(x) = 1+x+x**2/2!+... for 1<=x <=2 or some such thing. Then limits on the accuracy of this part of the function can be found. Then it is just necessary to take e to an integral power. There are many references that I could find that use this approach. Since all of the hyperbolic functions are based on EXP, it is important to get the EXP efficient. Also, your hyperbolic functions may be error prone for certain arguments and you are also recomputing the EXP function twice, when it only needs to be done once. This needs to be fixed. Your use of eps in the SIN function in some cases seems overly harsh. For example, If ( abs(x) <= eps ) then return 0.0; There are many times when we want the SIN ( 1.0E-30 ) and want significant digits. Your approach gives 0.0 instead of 1.0E-30. It gives 0.0 instead of significant digits as long as x <= 1.E-06. Most people don't want this. One problem that I have is that the only VHDL I have right now is several years old, from MCC. This limits my ability to test the package body. However, I am trying to get an updated version of VHDL. This makes it impossible for me to test any of these functions. However, they could be done much better in light of the SIN issue above. Let me know if I can help in any way. _______ / | ====/ * |=============================================================== | / Oxford | Dr. Donald F. Hanson Department of | | / | Associate Professor Electrical Engineering | | \ | Fax: (601)232-7231 University of Mississippi | | | | Phone: (601)232-5389 University, MS | | / | eehanson@vm.cc.olemiss.edu 38677 | ===/ |=============================================================== |______ | / | \____| From jose Fri Feb 10 01:06:24 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA21312; Fri, 10 Feb 95 01:06:24 PST Date: Fri, 10 Feb 95 01:06:24 PST From: jose (Jose Torres) Message-Id: <9502100906.AA21312@vhdl.vhdl.org> To: math@vhdl.org Subject: vhdl math package status The purpose of this message is to let you know where we are at regarding the math package. A balloting group has been approved by IEEE and a draft of the documentation is currently under review by the working group and IEEE. We hope to be able to send the documentation out for general distribution and balloting by March. ***************************** HELP ******************************** > We NEED VOLUNTEERS to help finish a test suite for the whole package. > We have a template for the test bench with some data points for > the functions which can be used as a guideline. If you are interested, please > send a message to jose@vhdl.org ************************************************************************ As part of the process of balloting the package, I am working on putting together a tutorial to disseminate information on the package, its purpose, usage, and applications. ***************************** HELP ******************************** > I would appreciate any feedback/comments on applications that you are planning > to use this functionality for or are currently using it, as well as > any warnings you may have for other people. I would like to include > this information in the tutorial, since one of the objectives is to spread > knowledge on where and how you can use this functionality and also provide > an insight on things to watch for when using it. ************************************************************************ I am also planning to talk with some people in the technical press, and it very likely that they would be interested in talking with users of the package or this type of functionality. ***************************** HELP ******************************** > If you are a user and would be interested in participate in a telephone > conference call with the press for this purpose, please let me know as soon > as possible (no later than Tuesday 2/15). ************************************************************************ We are in the process of running additional checks and fixing reported problems. As soon as a new version is available for general consumption I will let you know. Thanks for your interest. Regards, Jose A. Torres (jose@vhdl.org) From jose Sat Mar 25 00:26:34 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA04790; Sat, 25 Mar 95 00:26:34 PST Date: Sat, 25 Mar 95 00:26:34 PST From: jose (Jose Torres) Message-Id: <9503250826.AA04790@vhdl.vhdl.org> To: math@vhdl.org Subject: new version of the math package Cc: jose Hello everyone, There is a new version of the package that incorporates several of the suggestions and feedback that we received through the reflector, as well as feedback generated during the creation of the template for the test bench. The new version of the package is located in the following directory (server machine: vhdl.org): /vi/math/package under the following file names: math_head.3.24.95.vhd -- contains the package declaration math_body.3.24.95.vhd -- contains the package body math.3.24.95.tar.Z -- compacted tar file that contains the previous two. If you do not have access to ftp and would like to receive a copy through e-mail, please let me know. This new version of the package has several changes with respect the previous broadcasted version. In summary, the changes in the package include: - fixes to the algorithms in functions that were generating incorrect results, - changes in the order of arguments in some functions for consistency with usage of equivalent functionality in other languages - changes in the name of some functions for clarity and consistency with names in ADA and to take advantage of the overloading capabilities of VHDL - addition of new functions that were considered necessary as part of the basic building blocks - deletion of the foreign functions in order to have a package that is VHDL only - enhancements in comments to include valid ranges and domains for the functions, as well as error conditions. We would appreciate your feedback on this new version as soon as possible, since we are planning to send the ballots out around the middle of next month. We are still in the process of finishing the template for the test bench. For those of you who have volunteered to help on the completion of the test bench, we will let you know pretty soon how you can help us to finish this task. A detailed list of all the major changes follows: 1) For most of the functions, the comments after their declaration were modified to include the purpose of the function, the domain of its arguments, the range of its return value, error conditions, and predefined results for special cases. 2) Changed the usage of LOG(BASE, X) to be LOG(X, BASE) for consistency with ADA, and as per request of some users 3) Removed the definition of COMPLEX_VECTOR in math-complex for consistency with math_real 4) Renamed the following functions for consistency with ADA and to take advantage of VHDL overloading facilities: CABS -> ABS CARG -> ARG CSQRT -> SQRT CEXP -> EXP ASIN -> ARCSIN ACOS -> ARCCOS ATAN -> ARCTAN ATAN2 -> ARCTAN ASINH -> ARCSINH ACOSH -> ARCCOSH ATANH -> ARCTANH 5) Changed CSQRT (now SQRT) to return only one value; the one with positive real part. 6) Added the following constants: MATH_HALF_PI MATH_Q_PI MATH_3_HALF_PI MATH_TWO_PI 7) Modified CEIL and FLOOR to fix error 8) Modified FMAX and FMIN to return X when X = Y 9) Modified convergence criteria in SQRT and CBRT 10) Modified MATH_EPS to represent 5 fractional decimal digits for consistency with minimum LRM requirements. 11) Modified all trigonometric functions to return predefined values for special cases such as 0, pi, pi/2, 3pi/2, and 2pi 12) Modified SINH, COSH, and TANH to fix computation for special cases 13) Modified "**" check for error condition and value computation 14) Modified EXP to make use of the relation EXP(x+y) = EXP(x)*EXP(y) for better accuracy 15) Modified EXP and LOG to check for illegal ranges and to compute predefined values for special cases 16) Modified SIN, COS, TAN for greater accuracy 17) Modified ASINH, ACOSH, and ATANH for special cases 18) Added the following functions in math_real: TRUNC(X) MOD(X,Y) 19) Added the following function in math_complex: LOG(Z) 20) Modified the order of arguments in ARCTAN() from ARCTAN(X,Y) to ARCTAN(Y,X) for consistency with usage in other languages 21) Added complete support for the type COMPLEX_POLAR in MATH_COMPLEX. The new version now supports the same functions for both COMPLEX and COMPLEX_POLAR. Some people feel that complex_polar should be part of a different package, I would like to hear your position regarding this matter. 22) Removed the complex arithmetic operators that had a combination of COMPLEX and COMPLEX_POLAR argument types, as part of the process of providing same functionality for both types. 23) Removed all the foreign functions, so that the package has no dependencies on non-VHDL functions. The deleted functions are SRAND RAND GET_RAND_MAX 24) Modified package banners to fit IEEE requirements. 25) The draft of the documentation has been revised by IEEE and the corresponding changes have been incorporated. From baker@prl.philips.nl Mon May 8 08:51:52 1995 Return-Path: Received: from relay.philips.nl by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA23230; Mon, 8 May 95 08:51:52 PDT Received: from prl.philips.nl ([130.144.1.112]) by relay.philips.nl (8.6.9/8.6.9-950414) with SMTP id RAA13249 for ; Mon, 8 May 1995 17:33:43 +0200 From: baker@prl.philips.nl Received: by prl.philips.nl; Mon, 8 May 1995 17:33:42 +0200 Received: by elaps.prl.philips.nl ; Mon, 8 May 1995 17:33:41 +0200 Message-Id: <199505081533.AA292117221@elaps.prl.philips.nl> Subject: help To: math@vhdl.org Date: Mon, 08 May 1995 17:33:41 METDST X-Mailer: Elm [revision: 109.14] help -- Baker, m.sc. K. Philips Research Laboratories Building WAY4 101, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands Phone: +31-40-743640 E-mail: baker@prl.philips.nl From verstrae@prl.philips.nl Tue May 9 07:46:23 1995 Return-Path: Received: from relay.philips.nl by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA07017; Tue, 9 May 95 07:46:23 PDT Received: from prl.philips.nl ([130.144.1.112]) by relay.philips.nl (8.6.9/8.6.9-950414) with SMTP id QAA26738 for ; Tue, 9 May 1995 16:40:34 +0200 From: verstrae@prl.philips.nl Received: by prl.philips.nl; Tue, 9 May 1995 16:40:33 +0200 Received: by casarea.prl.philips.nl ; Tue, 9 May 1995 16:40:32 +0200 Message-Id: <199505091440.AA249300432@casarea.prl.philips.nl> Subject: info To: math@vhdl.org Date: Tue, 09 May 1995 16:40:32 METDST X-Mailer: Elm [revision: 109.14] -- Verstraelen, ing. M.J.W. Philips Research Laboratories Building WAY4 073, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands Phone: +31-40-743728 E-mail: verstrae@prl.philips.nl From jose Wed May 10 12:26:32 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA24906; Wed, 10 May 95 12:26:32 PDT Date: Wed, 10 May 95 12:26:32 PDT From: jose (Jose Torres) Message-Id: <9505101926.AA24906@vhdl.vhdl.org> To: math@vhdl.org Subject: Standard Simulation Control Language Please find enclosed information about a new standardization effort that I have been asked to pass along. >>>>>>>>>>>>>>>>>> Announcing the formation of the Standard Simulation Control Language Study Group of the IEEE DASC A new Study Group has been approved by IEEE Computer Society Design Automation Standards Committee. The purpose of the Study Group is the following: Standardize a simulation control language that is portable across simulation environments. The Study Group is asking for participation from members of the Verilog and VHDL community who are willing to work on this *HDL- INDEPENDENT* effort. We would like to have participation from the EDA vendors as well as the user community. To view the Study Group's home page, view: http://vhdl.org/vi/scl/Welcome.html To find out more info about a group, send an email request to: scl-info@vhdl.org To get added to an email exploder and be made aware of the groups activities, send your email address to: scl-request@vhdl.org To submit a message to an email exploder, email the message to: scl@vhdl.org (Please do not send maintenance requests to this address!!) From eee3932d@descg2.desc.dla.mil Wed May 10 12:33:04 1995 Return-Path: Received: from descg2.desc.dla.mil by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA25013; Wed, 10 May 95 12:33:04 PDT Received: by descg2.desc.dla.mil (5.61++/1.34) id AA15914; Wed, 10 May 95 15:27:35 -0400 Date: Wed, 10 May 95 15:27:35 -0400 From: eee3932d@descg2.desc.dla.mil (Tom Ricciuti) Message-Id: <9505101927.AA15914@descg2.desc.dla.mil> To: math@vhdl.org, verstrae@prl.philips.nl Subject: Re: info Cc: tricciuti@descg2.desc.dla.mil Prof. Holstlaan, What information are you seeking? Tom Ricciuti From jose Wed May 10 12:38:57 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA25069; Wed, 10 May 95 12:38:57 PDT Date: Wed, 10 May 95 12:38:57 PDT From: jose (Jose Torres) Message-Id: <9505101938.AA25069@vhdl.vhdl.org> To: math@vhdl.org Subject: Math package status The purpose of this message is to let you know where we are at regarding the balloting of P1076.2. The status is as follows: 1) All the material was submitted to IEEE about 2 weeks ago. 2) IEEE is currently in the process of putting together the balloting packages. Their distribution will most probably happen within the next three weeks. 3) The last version of the package is located in the directory /vi/math/package at vhdl.org in the following files math_head.3.24.95.vhd -- package declaration math_body.3.24.95.vhd -- package body or math.3.24.95.tar.Z -- compressed tar file of the previous two 4) A template for the test bench is available now, but I need volunteers to fill in the information in the test bench before we can make it available. The job consists on entering input and output values, as well as running a simulator on it to check that things are in order. If you do not have access to ftp and want to have a copy of the package, please let me know it and I will e-mail the package to you. Regards, Jose A. Torres From jose Sun May 14 18:18:21 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA18195; Sun, 14 May 95 18:18:21 PDT Date: Sun, 14 May 95 18:18:21 PDT From: jose (Jose Torres) Message-Id: <9505150118.AA18195@vhdl.vhdl.org> To: math Subject: VITAL workshop For your information. If you are planning to attend DAC at San Francisco this year, then you may be interested on this workshop. >>>>> cut here VHDL INTERNATIONAL TO CONDUCT VITAL WORKSHOP SERIES First in Series Slated June 15-16 VHDL International is sponsoring a series of comprehensive two-day technical workshops to train ASIC library developement and modelling engineers to develop VHDL Initiative Toward ASIC Libraries (VITAL) models. The first workshop is scheduled June 15-16 at the Biltmore Hotel & Suites in Santa Clara, California. These seminars will help ASIC library developers world-wide to come up to speed rapidly on the VITAL 3.0 standard. Rapid adoption of the VITAL strategy for ASIC modeling will be beneficial for the ASIC and VHDL industry as a whole. Members of the IEEE VITAL team will be present at the workshop to assist partcipants and answer any questions during the design example session Some of the topics to be covered at the workshop are: * VITAL Overview * What is new in VITAL 3.0 and what has changed since 2.2b * Back Annotation Introduction to SDF (Purpose; Organization SDF to VITAL Mapping * VITAL Model Classification Level 0 Modeling (Requirements) Level 1 Modeling (Requirements) * Tables Truth Tables State Tables * Modeling Strategy Pin-to-pin Delay Modeling Distributed Delay Modeling Conditional delays and timing checks * Negative Timing Constraints Back Annotation and Negative Constraint Calculation Limitations * Application and Examples Combinational Model Sequential Models Bus Models Memories * Special Topics Differential Inputs Wired Logic Preleminary Workshop Agenda Day 1 June 15th, 1995 9:00 AM - 5:00 PM VITAL Basics SDF Delay styles Level 0 and level 1 requirements Day 2 June 16th, 1995 9:00 AM - 4:00 PM Application Design examples Negative constraints Changes from 2.2b Instructor: Ray Ryan, a full-time member of the technical staff at Synopsys in Mountain View, Calif., member of the IEEE Technical Action Group responsible for the VITAL specification and a former principal of Ryan & Ryan, will teach the workshop in Santa Clara. Course materials were developed by Ryan & Ryan of San Jose, Calif. Fees: $ 150.00 per person for VI corporate members $ 250.00 per person for non-members The fees include materials and lunch for two days. Cancellation Policy: A fee of $ 20.00 will be charged for cancellation prior to June 2, 95. 50% of the fees wil be refunded for cancellation between June 2 - June 9 No refund for cancellation after June 9th Payment: Cheque or credit card only. No Ppurchase orders. Make cheque payable to VHDL International Registration: The workshop is open on a first-come, first-served basis, with a limit of 100 attendees. For reservations, please provide the following info via fax or email to Lilia Periana of VHDL International: Name____________________________ Title_______________________ Company _______________________________________________________ Address________________________________________________________ ________________________________________________________ Tel: ____________________________Fax:________________________ email _____________________________ If paying by credit card then please provide the following: Credit card number:____________________________ Expires on:_______ Type of crdit card: Visa/MasterCard/________________________________ VHDL International, 3140 De La Cruz Blvd, Suite 200, Santa Clara, CA 95054 Tel: 408-492-9806 Fax: 408-970-4274 Email: viadmin@vhdl.org From jose Mon Jun 19 01:29:22 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA17864; Mon, 19 Jun 95 01:29:22 PDT Date: Mon, 19 Jun 95 01:29:22 PDT From: jose (Jose Torres) Message-Id: <9506190829.AA17864@vhdl.vhdl.org> To: math Subject: minutes from meeting on 6/16/95 VHDL MATH PACKAGE WORKING GROUP, P1076.2 Minutes of meeting in San Jose, 16 June 1995 Present: Jose Torres (Chair), jose@vhdl.org Charles Swart Chuck Swart John Hines Greg Peterson Joanne DeGroat Next meeting: most probably at VIUF in October at Boston, MA, USA. SUMMARY OF MEETING J. Torres presented an overview of deliverables for this group, status of the standardization process for this standard, expected schedule, and open issues. C. Swart presented an overview on the test bench for 1076.2, as well as issues regarding accuracy to compare results and compare with zero. Open issues were discussed and proposals for resolution were presented 1. DELIVERABLES for P1076.2 The VHDL math packages (P1076.2) will consist of basic functions and type conversions for real and complex types. It consists of two packages: MATH_REAL and MATH_COMPLEX. The packages will be installed in library IEEE. The deliverables will consist of the following: package declarations, package bodies, and documentation for the standard. A testbench will be prepared for each package as a guideline for implementors, but it will not formally be part of the standard and/or the documentation. The latest version of the packages is available through anonymous ftp from vhdl.org, in the directory /vi/math/package, file names are: math_head.6.13.95.vhd math_body.6.13.95.vhd or math.6.13.95.tar.Z -- for tar compressed version of the 2 files The packages can be retrieved as follows: ftp vhdl.org username: anonymous password: ftp> cd /vi/math/package ftp> get math_head.6.13.95.vhd ftp> get math_body.6.13.95.vhd ftp> bye If you do not have access to ftp, send an e-mail request to jose@vhdl.org 2. STATUS of P1076.2 All documentation for P1076.2 has been sent to IEEE for balloting. Based on the most up-to-date information, IEEE is planning to start sending ballots out by 6/15/95. Assuming that ballots are mailed around 6/15/95, the current tentative schedule is as follows: - balloting: 6/22 - 7/22 - address negative ballots: 7/22- 8/22 - submit standard to IEEE board: 9/15/95 - get IEEE approval: 12/95 (board gets together every quarter) For all of you who are part of the balloting group, please MAKE SURE TO RETURN YOUR MATERIALS ASAP so that we have time to address your answers and make the 9/15/95 date, which is critical. If we miss the September date, then we may need to wait until 3/96 to get IEEE approval. The following is an extract of the conformance rules discussed and mentioned in the documentation that apply and pertain to the use and implementation of this standard: a) No modifications shall be made to the package declarations whatsoever b) The standard mathematical definition and conventional meaning of the mathematical functions that are part of this standard, which are clarified by the Math_Real and Math_Complex package bodies, represent the formal semantics of the implementation of the Math_Real and Math_Complex package declarations. Implementers of these packages may choose to simply compile the package bodies as they are; or they may choose to implement the package bodies in the most efficient form available to the user. Users shall not implement a semantic that differs from the formal semantic specified herein. c) The Math_Real package shall be built on top of the standard data type and precision requirements for floating point operations defined in IEEE P1076-1993 (STD.STANDARD) d) The minimum precision required is that of the VHDL LRM (IEEE P1076): minimum of six decimal digits of precision in a range contained within the bounds -1E38 to 1E38 inclusive. Because of this reason and the fact that the functions are implemented on digital computers with only finite precision, the functions provided in this set of packages can, at best, only approximate the corresponding mathematically defined functions. An implementation is allowed to provide a higher precision. e) For some functions, the implementation must deliver "prescribed results" for certain special arguments, as defined in the comments for the functions both in the function declaration and the function body. The purpose is to strengthen the accuracy requirements at special argument values. Prescribed results take precedence over maximum relative error requirements. f) The semantics of the standard require that all the functions in the packages detect and report invalid parameters (out of range) through an assert statement. Domain of valid values is indicated in the Math_Real and Math_Complex package declarations. The default value of the severity level shall be Error. An implementation is allowed to provide a mechanism for the user to redefine the value of the severity level. g) The semantics of the standard do not require detection of overflow or underflow. Therefore, detection of underflow/overflow is optional and implementation dependent h) A definition of what comprises the capability of representing and distinguishing signed zeroes is beyond the scope of this standard. Implementations are allowed the freedom not to exploit the capability even when available. i) If an implementation chooses to provide any extensions beyond the minimum requirements of this standard (e.g., precision, overflow handling, ...), then it shall document its behavior accordingly. 3. ISSUES with P1076.2 Currently IEEE is in the process of reviewing the scope and text of copyright declarations, as well as whether or not the source code part of a standard will be available for free distribution or not. Therefore, the current copyright in the packages for P1076.2 is temporary and subject to change based on IEEE's resolution on this matter. This is a very controversial matter that is being reviewed by all the standardization groups that are in the process of submitting documentation for balloting. A proposal was presented to modify the documentation to document the standard without including the source code for the packages (POSIX like), and put the source code in a different place for free access. We will address this issue during the balloting period. 4. TESTBENCH: Status and Issues The testbench, which is not part of the standard, will be provided as a reference for implementors and will not be part of the documentation. The testbench is completely self-contained and fully written in VHDL. The test bench exercises data points for all the functions, compares the values generated by an implementation against a set of "golden" outputs, and produces a report with min accuracy found for each function. The goal of the test bench is to provide a clue on how close an implementation is to the expected results and accuracy, but not to be a validation tool. It is important to note that the math package results may be slightly different on different workstation combinations due to the workstations particular support for floating point arithmetic, which may not be immediately apparent to the average VHDL user. Also, there are issues regarding the comparison of values against zero (i.e., should e-25 be considered close or far from e-40?). The current status of the test bench is as follows: a template for all the functions is available, a reasonable/adequate set of data points is available for some functions but not all, further work/help is needed to complete the sets of data points, it has been run on 4 different commercial VHDL simulation tools. The current version of the test bench is only available upon request, since it is not complete. If you are interested on receiving a copy, please send e-mail to jose@vhdl.org or cswart@analogy.com. Once the test bench is complete, it will be placed in the /vi/math/package directory and eventually will be transferred to John Hines, so that it becomes part of the VHDL test suite his group is responsible for. From VhdlCohen@aol.com Tue Jun 20 20:53:18 1995 Return-Path: Received: from mail04.mail.aol.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA08610; Tue, 20 Jun 95 20:53:18 PDT Received: by mail04.mail.aol.com (1.37.109.11/16.2) id AA090476423; Tue, 20 Jun 1995 23:47:03 -0400 Date: Tue, 20 Jun 1995 23:47:03 -0400 From: VhdlCohen@aol.com Message-Id: <950620234336_99068088@aol.com> To: math@vhdl.org Subject: Book Announcement: "VHDL Coding Styles and Methodologies" VHDL Coding Styles and Methodologies by Ben Cohen VHDL Coding Styles and Methodologies provides an in-depth study of the VHDL language rules, coding styles, and methodologies. This book clearly distinguishes good from poor coding methodologies using an easy to remember symbology notation along with a rationale for each guideline. The VHDL concepts, rules and styles are demonstrated using complete compilable and simulatable examples which are also supplied on the accompanying disk. VHDL Coding Styles and Methodologies provides practical applications of VHDL and techniques that are current in the industry. It explains how to apply the VHDL guidelines using several complete examples. The 'learning by example' teaching approach along with an in-depth presentation of the language rules application methodology provides the necessary knowledge to create digital hardware designs and models that are readable, maintainable, predictable, and efficient. VHDL Coding Styles and Methodologies is intended for both college students and design engineers. It provides a practical approach to learning VHDL. Combining methodologies and coding styles along with VHDL rules leads the reader in the rights direction from the beginning. Contents: Preface. About the Disk. Notation Conventions. 1. VHDL Overview and Concepts. 2. Basic Language Elements. 3. Control Structures. 4. Drivers. 5. VHDL Timing. 6. Elements of Entity/Architecture. 7. Subprograms. 8. Packages. 9. User Defined Attributes, Specifications, and Configurations. 10. Functional Models and Testbenches. 11. UART Project. 12. Vital. 13. Design for Synthesis. Appendix A: VHDL'93 and VHDL'87 Syntax Summary. Appendix B: Package Standard. Appendix C: Package Textio. Appendix D: Package STD_Logic_1164. Appendix E: VHDL Predefined Attributes. Kluwer Academic Publishers, Boston Date of publishing: July 1995 392 pp. Hardbound ISBN: 0-7923-9598-0 Prices: NLG: 160.00 USD: 94.00 GBP: 63.95 ================================================================= Author: Ben Cohen Title: VHDL Coding Styles and Methodologies ( ) Hardbound / ISBN: 0-7923-9598-0 NLG: 160.00 USD: 94.00 GBP: 63.95 Ref: KAPIS ( ) Payment enclosed to the amount of _____________________ ( ) Please send invoice ( ) Please charge my credit card account: Card no.: |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| Expiry date: ________ () Access () American Express () Mastercard () Diners Club () Eurocard () Visa Name of Card holder: __________________________________________ Delivery address: Title : _____________________ Initials: ____________M/F______ First name : ________________ Surname: ________________________ Organization: _____________________________________________________ Department : _____________________________________________________ Address : _____________________________________________________ Postal Code : ___________________ City: ___________________________ Country : _______________________Telephone: ________________ Email : _______________________________________________ Date : _______________ Signature: _______________________ Our European VAT registration number is: |_|_|_|_|_|_|_|_|_|_|_|_|_|_| To be sent to: For customers in Mexico, USA and Canada: Rest of the world: Kluwer Academic Publishers Kluwer Academic Publishers Group Order Department Order Department P.O. Box 358 P.O. Box 322 Accord Station 3300 AH Dordrecht Hingham, MA 02018-0358 The Netherlands U.S.A. Tel : 617 871 6600 Tel : +31 78 524400 Fax : 617 871 6528 Fax : +31 78 524474 Email : kluwer@world.std.com Email : services@wkap.nl Payment will be accepted in any convertible currency. Please check the rate of exchange with your bank. Prices are subject to change without notice. All prices are exclusive of Value Added Tax (VAT). Customers in the Netherlands please add 6% VAT. Customers from other countries in the European Community: * please fill in the VAT number of your institute/company in the appropriate space on the orderform: or * please add 6% VAT to the total order amount (customers from the U.K. are not charged VAT). ================================================================= ============================================================================== = Ben Cohen is the author of "VHDL Coding Styles and Methodologies ... an In-Depth Tutorial" (ISBN 0-7923-9598-0) to be published in July 95 by Kluwer Academic -- Publishers. (see gopher://gopher.wkap.nl for more information, or write to kluwer@world.std.com). (Book was written as an independent project to help teach VHDL) Hughes Aircraft Co, RE- R1/B507 2000 East Imperial Hwy El Segundo, Ca, 90245 (310) 334-7389, fax: (310) 334-1749 ====================================================================== From jose Mon Jul 17 12:32:57 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA14996; Mon, 17 Jul 95 12:32:57 PDT Date: Mon, 17 Jul 95 12:32:57 PDT From: jose (Jose Torres) Message-Id: <9507171932.AA14996@vhdl.vhdl.org> To: math Subject: balloting group for 1076a. For your information, please find enclosed the application form to become part of the balloting group for standard 1076a (shared variables). If you want to participate, please follow directions shown at end of attached document. Otherwise, discard this message. Thanks. Jose A. Torres ------cut here------------- P1076a: SUPPLEMENT to the VHDL Standard LRM for Shared Variables Return deadline: September 24, 1995 SCOPE: Add semantics for shared variables to the VHDL standard. PURPOSE: VHDL currently has no semantics defined for global variables. This effort will solve that problem Your Category of Interest in this Standards Ballot (i.e. do you use or produce the items in this standard?): User Producer Academic General Interest (Note: Please choose only ONE of the above. If you have any combination of Interests, check the General Interest Category) Please Print Clearly: New address? ___ Yes or ____ No Name: Phone: Fax: EMail: Company: Mailing Address: IEEE or Computer Society Membership Number: Check here if not a member of IEEE or the Computer Society ____ Balloter's Responsibility: If you become part of the balloting body, you will have 30 days to review and respond to the draft. In order for the Sponsor Ballot to be valid, at least 75% of the ballots sent must be returned. For that reason: VOTERS HAVE AN OBLIGATION TO RESPOND. Eligible voters are members of the IEEE or Computer Society and non-members will comment as Parties of Interest. For Membership Application, Call (908) 562-5524 Signature: Date: If you want confirmation that this form has been received by the IEEE Standards Office, please press "return receipt" when sending electronically, or enclose a stamped, pre-addressed post card along with this form. _____Yes, I want to be part of the DASC Balloting Pool and receive invitations to ballot future DASC drafts. -----cut here------------ Please return by September 24, 1995 to: Rosemary Tennis IEEE Standards Office 445 Hoes Lane, PO. Box 1331 Piscataway, NJ 08855-1331 Fax: 908/562-1571 To respond by e-mail send to: rtennis@stdsmail.ieee.org With subject filled in to : 1076a ballot With CC to: stephen@srbailey.com want From jose Thu Sep 14 22:22:13 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA03529; Thu, 14 Sep 95 22:22:13 PDT Date: Thu, 14 Sep 95 22:22:13 PDT From: jose (Jose Torres) Message-Id: <9509150522.AA03529@vhdl.vhdl.org> To: math Subject: DASC meetings in October -- for your information =============================================================================== IEEE COMPUTER SOCIETY DESIGN AUTOMATION STANDARDS COMMITTEE MEETINGS IN CONJUNCTION WITH THE FALL 1995 VHDL INTERNATIONAL USERS' FORUM 17-18 OCTOBER 1995 NEWTON MARRIOTT HOTEL MASSACHUSETTS TURNPIKE AND I-95 NEWTON, MA SCHEDULE AS OF 14 September 1995 THURSDAY, 17 OCTOBER Note: All rooms today (except Lexington) are available only until 5:00 PM. Therefore, I have scheduled today's meetings from 8:00 AM to 5:00 PM. 8:00 AM-12:00 N OBJECT-ORIENTED EXTENSIONS TO VHDL STUDY GROUP Contact: Doug Dunlop, Chair 703-827-2606 Intermetrics, Inc. 703-827-2609 [Fax] 7918 Jones Branch Drive, Suite 710 dunlop@wash.inmet.com McLean, VA 22102 This meeting will take place in the Lexington room. 8:00 AM-12:00 N OPEN MODELING STUDY GROUP Contact: Gabe Moretti, Chair 303-581-2324 Intergraph Electronics 303-581-9143 [Fax] 6101 Lookout Road, Suite A gmoretti@ingr.com Boulder, CO 80301 This meeting will take place in Salon F. 8:00 AM-12:00 N LIBRARY IEEE CONTENTS STUDY GROUP Contact: Andrew Guyler, Chair 503-685-1163 Mentor Graphics, Inc. 503-685-1268 [Fax] C-3 andrew_guyler@mentorg.com 8005 S.W. Boeckman Road Wilsonville, OR 97070-7777 This meeting will take place in Salon G. 8:00 AM-10:00 AM VHDL-EDIF INTEROPERABILITY WORKING GROUP--P1165 Contact: J. Bhasker, Chair 215-770-3983 AT&T Bell Labs 215-770-2773 [Fax] 1247 South Cedar Crest Boulevard, 2R242 jb7@mhcnet.att.com Allentown, PA 18103 This meeting will take place in Salon H. 10:00 AM-12:00 N VHDL MATH PACKAGE WORKING GROUP--P1076.2 Contact: Jose Torres, Chair 415-327-2023 1540 Oak Creek Drive, #305 jose@vhdl.org Palo Alto, CA 94304 This meeting will take place in Salon H. 1:00 PM-5:00 PM VHDL SHARED VARIABLES WORKING GROUP--P1076A Contact: Steve Bailey, Chair 408-271-7048 SRBailey Consulting 408-377-1206 [Fax] 911-C Apricot Avenue stephen@srbailey.com Campbell, CA 95008 This meeting will take place in the Lexington room. 1:00 PM-5:00 PM SYSTEM DESIGN & DESCRIPTION LANGUAGE STUDY GROUP Contact: Dave Barton, Chair 703-827-2606 Intermetrics, Inc. 703-827-2609 [Fax] 7918 Jones Branch Drive, Suite 710 dlb@hudson.wash.inmet.com McLean, VA 22102 This meeting will take place in Salon F. 1:00 PM-5:00 PM VHDL ANALOG EXTENSIONS WORKING GROUP LDC--P1076.1 Contact: Jean-Michel Berge, Chair +33 76 76 43 35 CNS-CCI +33 76 90 34 43 Chemin Du Vieux Chene--BP 98 berge@cns.cnet.fr MEYLAN CEDEX F-38243 FRANCE This meeting will take place in Salon G. 1:00 PM-5:00 PM WAVEFORM AND VECTOR EXCHANGE SPEC. WORKING GROUP--1029.1 Contact: Bob Hillman, Chair 315-330-2813 Rome Laboratory/ERG 315-330-2885 [Fax] 525 Brooks Road hillmanr@ernet.af.mil Griffiss AFB, NY 13441-4505 This meeting will take place in Salon H. 5:30 PM-7:30 PM DASC STEERING COMMITTEE MEETING Contact: Paul Menchini, Chair 919-990-9506 Menchini & Associates 919-990-9507 [Fax] 2 Davis Drive mench@mench.com P.O. Box 13036 Research Triangle Park, NC 27709-3036 This meeting will take place in the Lexington room. FRIDAY, 18 OCTOBER 8:30 AM-5:30 PM VHDL ANALOG EXTENSIONS WORKING GROUP--P1076.1 Contact: Jean-Michel Berge, Chair This meeting will take place in the Lexington room. 8:30 AM-12:30 PM VHDL TIMING METHODOLOGY WORKING GROUP--P1076.4 Contact: Victor Berman, Chair 508-446-6276 Cadence Design Systems, Inc. 508-262-6777 [Fax] 270 Billerica Road berman@cadence.com Chelmsford, MA 01824 This meeting will take place in Salon F. 1:30 PM-3:30 PM VERILOG ANALYSIS AND STANDARDIZATION GROUP--P1364 Contact: Maq Mannan 408-721-6340 National Semiconductor, Inc. 408-721-5382 [Fax] 2900 Semiconductor Drive mannan@galaxy.nsc.com Santa Clara, CA 95051 This meeting will take place in Salon F. 3:30 PM-5:30 PM VHDL PARALLEL SIMULATION STUDY GROUP Contact: John Willis, Chair 507-288-3154 FTL Systems, Inc. 507-288-3154 [Fax] 924 Sierra Lane NE jwillis@acm.org Rochester, MN 55901 This meeting will take place in Salon F. From jose Wed Oct 4 13:05:20 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA21844; Wed, 4 Oct 95 13:05:20 PDT Date: Wed, 4 Oct 95 13:05:20 PDT From: jose (Jose Torres) Message-Id: <9510042005.AA21844@vhdl.vhdl.org> To: math@vhdl.org Subject: P1076.2 Passes! I am glad to inform you that the balloting for the Math package closed on 9/14/95 with a majority of affirmative votes. Vital 95 passed, here's the results: 76% Returned 46 Affirmative 7 Negative 3 Abstentions => 86% Afirmative The next step for the working group is to review the comments and negative votes and prepare an answer to address them, as well as to update schedule for submitting the proposal to the IEEE Board. As soon as I have information on the schedule I will let you know. Thanks a lot to all of you who have contributed during the process. Jose A. Torres Chair of P1076.2 From jose Mon Nov 20 21:09:52 1995 Return-Path: Received: by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA10192; Mon, 20 Nov 95 21:09:52 PST Date: Mon, 20 Nov 95 21:09:52 PST From: jose (Jose Torres) Message-Id: <9511210509.AA10192@vhdl.vhdl.org> To: math Subject: minutes from DASC meeting on 10/19/95 VHDL MATH PACKAGE WORKING GROUP, P1076.2 Minutes of meeting in Newton, MA on October 19, 1995 Present: Jose Torres (Chair), jose@vhdl.org John Hines Ernst Christen Bob Collins Next meeting: most probably at next VIUF meeting SUMMARY OF MEETING J. Torres presented an overview of balloting results, gave a summary of main areas addressed by either negative ballots or comments, discussed status of the IEEE copyright issue regarding distribution of the source code for the packages, and presented the tentative schedule to bring this effort to completion. Ernst C. talked about needs of the Analog group and situation regarding the floating point precision in VHDL and the Analog group requirements. There was a discussion on what to do regarding the source code for the packages and the documentation for the standard. 1. BALLOTING RESULTS Balloting for 1076.2 was closed around the middle of September with the following results: Affirmative votes: 46 Negative votes: 7 Abstentions: 2 TOTAL 55 Number of eligible voters in the balloting group: 72 Therefore, 1076.2 PASSED with 86% affirmative votes, and 76% eligible ballots were returned. The main comments received in the ballots are in the following areas: - style and consistency (naming conventions, error messages, use of constants) - typos - rejection of IEEE copyright restriction on distribution of packages - extensions for additional functionality - problems found in some functions for corner cases It was mentioned that the working group is working on addressing all the comments and making necessary changes to convert the negative ballots into positive ones. Depending on the magnitude of the changes, a decision will be made at that point on whether or not a re-balloting is necessary. 2. IEEE COPYRIGHT ISSUE There were 4 negative ballots due to the request from IEEE to remove the free distribution clause from the packages. People attending the meeting also mentioned that they or their companies were not happy with such decision and suggested to remove the source code from the documentation to avoid this constraint and document the standard in the way is done in ADA for similar functionality. Jose took the action item to check with IEEE the status of this item and present the suggestion to the working group for their consideration when addressing the comments from the ballots. 3. SCHEDULE The following tentative schedule was presented (contingent on the decision to re-ballot the standard): - Review Ballots and address comments: 10/15 - 11/30 - Submit to IEEE board: 12/15 - Approval: either Q4'95 or Q1'96 If reballoting is recommended, the the schedule would look like follows: - Review Ballots and address comments: 10/15 - 11/30 - Re-ballot: 12/15 - 2/1 - Review ballots: 2/15 - 3/15 - Submit to IEEE board: 4/15 - Approval: Q2'96 4. ANALOG GROUP STATUS on PRECISION for TYPE REAL Ernst C. mentioned that the most likely direction in the Analog working group regarding the precision issue (currently LRM only requires 6 digits of precision) was to request a change in the LRM to increase the precision for type REAL. If this is the final recommendation, then no additional changes will be required in the Math packages to support the required precision by Analog, since the changes would be in the simulators themselves to support the new precision required by the LRM. 5. WHERE TO FIND INFORMATION The latest version of the packages is available through anonymous ftp from vhdl.org, in the directory /vi/math/package, file names are: math_head.6.13.95.vhd math_body.6.13.95.vhd or math.6.13.95.tar.Z -- for tar compressed version of the 2 files The packages can be retrieved as follows: ftp vhdl.org username: anonymous password: ftp> cd /vi/math/package ftp> get math_head.6.13.95.vhd ftp> get math_body.6.13.95.vhd ftp> bye If you do not have access to ftp, send an e-mail request to jose@vhdl.org From ume@imaisun.tutics.tut.ac.jp Fri Dec 1 06:55:54 1995 Received: from imaisun.tutics.tut.ac.jp by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet) id AA20464; Fri, 1 Dec 95 06:55:54 PST Received: by imaisun.tutics.tut.ac.jp (5.67+1.6W/6.4JAIN) id AA16724; Fri, 1 Dec 95 23:45:54 JST Date: Fri, 1 Dec 95 23:45:54 JST From: ume@imaisun.tutics.tut.ac.jp (Keijiro Umehara) Return-Path: Message-Id: <9512011445.AA16724@imaisun.tutics.tut.ac.jp> To: math@vhdl.org Subject: about transform floating pint number Dear Sirs: I am studying VLSI design in VHDL at Dept of Info. & Comp. Science, Toyohashi Univ. of Tech., Aichi, Japan. I would like to have some advices from you. I want to transform a single precise floating point number, represented in the forms of IEEE754's std_logic_vector, into a real value. But the VHDL simulator (synopsys inc.) cannot calculate the following expression because of the over_flow error. (-1)**(s)*2**(e-127)*(1+f) ex. 11111111011111111111111111111111 -> (-1)**(1)*2**(127)*(2.0) (can't calculate this) -> 3.40*10**38 How to transform a single precise floating point number, represented in the forms of IEEE754's std_logic_vector, into a real value? Please teach me. Thank you. -- Keijiro Umehara (e-mail : ume@imaisun.tutics.tut.ac.jp) From owner-math Tue Feb 20 17:16:09 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id RAA23046 for math@vhdl.org; Tue, 20 Feb 1996 17:16:09 -0800 (PST) Date: Tue, 20 Feb 1996 17:16:09 -0800 (PST) From: Jose Torres Message-Id: <199602210116.RAA23046@vhdl.vhdl.org> To: math@vhdl.org Subject: 1076.2 comments to ballots As a result of the balloting process for 1076.2, we need your feedback on the following proposed changes: 1) Since the package body is not normative (i.e., mandatory) and there are issues regarding free distribution of the package body due to IEEE copyright new policies, we are planning to remove the package body from the documentation, have a reference to it in the non-normative part of the standard, and place the package body in a central repository such as the "vhdl.org" machine sponsored by VI. Would this be OK with you? Please state your reasons for either a positive or a negative answer. 2) There have been requests to remove all complex functions that have polar arguments except the functions to convert between complex polar and complex non-polar. Main reasons for this request are that these functions are not used very often and basic functionality is already provided with the availability of the conversion functions and the functions for non-polar complex arguments. Would you support this change? Please state your reasons for either a positive or a negative answer. We need your feedback as soon as possible, since we would like to finish the changes for the package by the end of the month to submit a new revision by next month. Thanks for your help on this matter. Regards, Jose A. Torres Chair 1076.2 From owner-math Tue Feb 20 18:22:26 1996 Received: from relay5.UU.NET (relay5.UU.NET [192.48.96.15]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id SAA23496; Tue, 20 Feb 1996 18:22:25 -0800 (PST) Received: from uucp6.UU.NET by relay5.UU.NET with SMTP id QQaduu08674; Tue, 20 Feb 1996 21:13:59 -0500 (EST) Received: from signal.UUCP by uucp6.UU.NET with UUCP/RMAIL ; Tue, 20 Feb 1996 21:14:00 -0500 Received: from loop. by model.com (5.x/SMI-SVR4) id AA02572; Tue, 20 Feb 1996 17:55:00 -0800 Date: Tue, 20 Feb 1996 17:55:00 -0800 From: signal!bgriffin@uunet.uu.net (Brian Griffin) Message-Id: <9602210155.AA02572@model.com> Received: by loop. (1.39.111.2/SMI-SVR4) id AA166637747; Tue, 20 Feb 1996 17:55:47 -0800 To: uunet!vhdl.org!jose@uunet.uu.net Cc: uunet!vhdl.org!math@uunet.uu.net In-Reply-To: <199602210116.RAA23046@vhdl.vhdl.org> (uunet!vhdl.org!jose) Subject: Re: 1076.2 comments to ballots > >Received: from vhdl.vhdl.org by relay3.UU.NET with ESMTP > id QQaduq03789; Tue, 20 Feb 1996 20:10:56 -0500 (EST) > Date: Tue, 20 Feb 1996 17:16:09 -0800 (PST) > From: Jose Torres > Content-Type: text > Content-Length: 1375 > > > As a result of the balloting process for 1076.2, we need your feedback > on the following proposed changes: > > 1) Since the package body is not normative (i.e., mandatory) and there > are issues regarding free distribution of the package body due to > IEEE copyright new policies, we are planning to remove the package > body from the documentation, have a reference to it in the non-normative > part of the standard, and place the package body in a central repository > such as the "vhdl.org" machine sponsored by VI. > > Would this be OK with you? Please state your reasons for either > a positive or a negative answer. I vote yes. The body needs to be publicly available so that implementers and users can verify any given implementation. > > 2) There have been requests to remove all complex functions that have > polar arguments except the functions to convert between complex polar > and complex non-polar. Main reasons for this request are that these > functions are not used very often and basic functionality is already > provided with the availability of the conversion functions and the > functions for non-polar complex arguments. > > Would you support this change? Please state your reasons for > either a positive or a negative answer. This sounds ok to me. I can't pass judgment on usefulness of these functions, but, if there are alternative ways of getting the necessary results, then, by all means, simplify the package. > > We need your feedback as soon as possible, since we would like to finish > the changes for the package by the end of the month to submit a new > revision by next month. > > Thanks for your help on this matter. > > Regards, > > Jose A. Torres > Chair 1076.2 > > > > -Brian Griffin -- USE STD.DISCLAIMER.ALL; -- __ -- mailto:brian_griffin@model.com /__) . __ ,__o -- phone: (503)641-1340 /___)_/-,_/_(_(_/V/_ _-\_<, -- fax: (503)526-5410 / (U)/'(*) -- http://www.model.com My other car is a bicycle -------- -- Model Technology 8905 SW Nimbus Avenue Suit 150 Beaverton OR 97008 From owner-math Wed Feb 21 06:20:05 1996 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id GAA04189; Wed, 21 Feb 1996 06:20:02 -0800 (PST) Received: (from mench@localhost) by mench.mench.com (8.6.9/8.6.9) id JAA13692; Wed, 21 Feb 1996 09:10:51 -0500 Date: Wed, 21 Feb 1996 09:10:51 -0500 From: "Paul J. Menchini" Message-Id: <199602211410.JAA13692@mench.mench.com> To: jose@vhdl.org Subject: Re: 1076.2 comments to ballots Cc: math@vhdl.org, mench@mench.mench.com, c.rowden@ieee.org > As a result of the balloting process for 1076.2, we need your feedback > on the following proposed changes: > > 1) Since the package body is not normative (i.e., mandatory) and there > are issues regarding free distribution of the package body due to > IEEE copyright new policies, we are planning to remove the package > body from the documentation, have a reference to it in the non-normative > part of the standard, and place the package body in a central repository > such as the "vhdl.org" machine sponsored by VI. > > Would this be OK with you? Please state your reasons for either > a positive or a negative answer. No it would not. There are several problems with this approach: * The package body is the most consise and precise definition of the semantics of the package. To move it to a non-normative section of the standard, or to eliminate it from the standard, at the very least sends the wrong message. Also, it possibly will make models using the package non-portable, since the standard would then either not define the semantics of the package or would have a possibly imprecise or incorrect definition. * I suspect that moving the body to a non-normative section of the standard wouldn't achieve the desired result. It's still part of the standard and would still have to be licensed from the IEEE. Let me also point out several fallacies with the statement. "Normative" is not equivalent to "mandatory." Normative means "contributes to the definition of the standard. I hope the package body *is* normative! Of course, if we resort to defining the semantics by appealing to "the mathematical definition" the particular function with specifications of accuracy and precision, that would be one way out. But then, why bother to have a package body at all? It's at least superfuluous and perhaps contradictory to the "real" definition. The IEEE copyright policies are not "new." What, in my opinion, is new, is that the IEEE has decided to enforce their existing rights under copyright law and is working towards what are hopefully fair and equitable procedures and charges for the redistribution of VHDL code that is part of IEEE copyrighted materials. > 2) There have been requests to remove all complex functions that have > polar arguments except the functions to convert between complex polar > and complex non-polar. Main reasons for this request are that these > functions are not used very often and basic functionality is already > provided with the availability of the conversion functions and the > functions for non-polar complex arguments. > > Would you support this change? Please state your reasons for > either a positive or a negative answer. My feelings on this matter are not a strong as those on the first. If this proposal had been made earlier in the process, it would be worth supporting. At this stage, all the standardization work has been done, so we'd be in the position of throwing away work. Of course, doing so would presumably simplify matters for implementors. But, implementors can always (at least initially) implement the polar complex functions by using the conversion functions wrapped around the corresponding rectilinear complex functions, subject to precision and accuracy limitations, so it seems that very little is gained by this proposal at this stage. I recommend that we keep the functions. Paul -- Paul Menchini | email: mench@mench.com | WWW: http://www.mench.com/ Menchini & Associates | voice: 919-990-9506 | "Se tu sarai solo, 2 Davis Dr./POB 13036 | pager: 800-306-8494 | tu sarai tutto tuo." RTP, NC 27709-3036 | fax: 919-990-9507 | -- Leonardo Da Vinci From owner-math Wed Feb 21 09:35:59 1996 Received: from chronos.synopsys.com (chronos.synopsys.com [146.225.8.10]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id JAA05849; Wed, 21 Feb 1996 09:35:58 -0800 (PST) Received: from atropos.synopsys.com by chronos.synopsys.com with SMTP id AA26827 (5.65c/IDA-1.4.4); Wed, 21 Feb 1996 09:27:19 -0800 Received: from gong.synopsys.com (gong.synopsys.com [146.225.92.17]) by atropos.synopsys.com (8.6.9/8.6.9) with ESMTP id JAA06196; Wed, 21 Feb 1996 09:27:18 -0800 From: Gong Wen Huang Received: (gong@localhost) by gong.synopsys.com (8.6.9/8.6.5) id JAA18053; Wed, 21 Feb 1996 09:27:16 -0800 Date: Wed, 21 Feb 1996 09:27:16 -0800 Message-Id: <199602211727.JAA18053@gong.synopsys.com> To: jose@vhdl.org, mench@mench.com Subject: Re: 1076.2 comments to ballots Cc: c.rowden@ieee.org, math@vhdl.org, mench@mench.mench.com I agree with Paul's vote. For second item, I have an additinal point: Removing those functions will force an unefficient way to implement and to use the functinalities. (also, a package is not something needed to be read and to be analyzed everyday. An user selects what is needed then s/he could forget the rest.) -gong From owner-math Thu Feb 22 01:50:48 1996 Received: from netcom.netcom.com (alexz@netcom.netcom.com [192.100.81.100]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id BAA12720; Thu, 22 Feb 1996 01:50:47 -0800 (PST) Received: by netcom.netcom.com (8.6.12/Netcom) id BAA15046; Thu, 22 Feb 1996 01:41:16 -0800 Date: Thu, 22 Feb 1996 01:41:16 -0800 From: alexz@netcom.com (Alex Z) Message-Id: <199602220941.BAA15046@netcom.netcom.com> To: jose@vhdl.org, math@vhdl.org Subject: Re: 1076.2 comments to ballots My vote is to keep the body as normative part of the standard and to leave the COMPLEX_POLAR functions as they are now. My reason is that the body is used for the semantics and there will be no problem about the copyright since most vendors are implementing the body in an optimized form and there is no big advantage to step into for example the "sin" function, you can even think it's a sin :-) The reason for leaving the polar functions in is efficiency. These functions (the complex operators) are not optimizable with a lot of advantage and most tools can not do better then the vhdl algorithm. However, DSP users might want to have control on the algorithm and the representation comes in handy. Therefore, with both representations available DSP algorithms can be written and executed in VHDL as efficient as in any low level language. I have thought this through and have examples that prove this point. I left them in Vantage. I am glad Vantage was kind enough to donate their math packages to the IEEE, and I would not expect to to be able to show you what was used during their design. In conclusion (and that seems to be also Paul Menchini's view) we can be safely "pro-life" in this case. The body and the functions should be delivered, and IEEE is a right "parent." Best regards, Alex Zamfirescu P.S. The argument about simplification does not hold. A user uses as much as (s)he wants from a package. AZ From owner-math Thu Feb 22 10:47:56 1996 Received: from tiny.sprintlink.net (tiny.sprintlink.net [199.0.55.90]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id KAA22247 for ; Thu, 22 Feb 1996 10:47:54 -0800 (PST) Received: from analogy.com (analogy.analogy.com [149.117.1.1]) by tiny.sprintlink.net (8.6.9/8.6.9) with SMTP id NAA28159 for ; Thu, 22 Feb 1996 13:39:26 -0500 Received: from miller.analogy.com by analogy.com (4.1/Shared_Spool_1.3) id AA03053; Thu, 22 Feb 96 10:41:37 PST Received: from glacier.analogy.com by miller.analogy.com (4.1/SMI-3.2) id AA10894; Thu, 22 Feb 96 10:41:36 PST Received: by glacier.analogy.com (5.x/SMI-SVR4) id AA07491; Thu, 22 Feb 1996 10:41:35 -0800 Date: Thu, 22 Feb 1996 10:41:35 -0800 From: cswart@analogy.com (Charles F. Swart) Message-Id: <9602221841.AA07491@glacier.analogy.com> To: math@vhdl.org Subject: comments to ballots X-Sun-Charset: US-ASCII Jose and I are trying to move forward on the Math Package approval process. We very much appreciate comments from all of you on the two questions: (1) Should we remove the package bodies from the documentation? (2) Should we remove the complex functions involving polar arguments? However, I think that comments made by Paul and Alex require a clarification. It was never the intention that the package bodies be used to define the semantics of the functions. In fact, the opposite is the case. The semantics are intended to be defined in the package headers alone. There are (at least) two reasons for this. First, the code in the package body was obtained from a wide variety of sources, and its correctness cannot be guaranteed. Implementations should not be expected to reproduce incorrect results which the code in the package bodies could supply. Second, the package bodies are as portable as we could get. Consequently, the results produced are in many cases not as accurate as could be obtained by implementation dependent methods. It is not desirable to restrict accuracy of implementations to the accuracy supplied by the package bodies. So vote as you see fit, but please don't expect the package bodies to supply semantics. From owner-math Thu Feb 22 11:19:24 1996 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id LAA22455 for ; Thu, 22 Feb 1996 11:19:22 -0800 (PST) Received: (from mench@localhost) by mench.mench.com (8.6.9/8.6.9) id OAA01090; Thu, 22 Feb 1996 14:11:33 -0500 Date: Thu, 22 Feb 1996 14:11:33 -0500 From: "Paul J. Menchini" Message-Id: <199602221911.OAA01090@mench.mench.com> To: cswart@analogy.com Subject: Re: comments to ballots Cc: math@vhdl.org, c.rowden@ieee.org Chuck, > Jose and I are trying to move forward on the Math Package approval process. > We very much appreciate comments from all of you on the two questions: > (1) Should we remove the package bodies from the documentation? > (2) Should we remove the complex functions involving polar arguments? > > However, I think that comments made by Paul and Alex require a clarification. > It was never the intention that the package bodies be used to define the > semantics of the functions. In fact, the opposite is the case. The semantics > are intended to be defined in the package headers alone. There are (at least) > two reasons for this. First, the code in the package body was obtained from a > wide variety of sources, and its correctness cannot be guaranteed. > Implementations should not be expected to reproduce incorrect results which > the code in the package bodies could supply. Second, the package bodies are > as portable as we could get. Consequently, the results produced are in many > cases not as accurate as could be obtained by implementation dependent methods. > It is not desirable to restrict accuracy of implementations to the accuracy > supplied by the package bodies. > > So vote as you see fit, but please don't expect the package bodies to supply > semantics. Thanks for the clarification. If it is the case that the package bodies do not supply semantics, then they should *not* be part of the normative portion of the standard--this much, I believe, is absolutely clear. One could argue that the bodies should not be part of the standard at all--in which case, subject to IEEE clarification, perhaps they *can* be posted on vhdl.org for any who are interested. I believe that IEEE clarification is needed since the bodies were, at one time, part of the draft. One question: Given Chuck's comments, what *is* the purpose of the bodies? Are they merely suggestions for possible implementations? Given that their correctness cannot be determined, are they worth promulgating at all? Perhaps they should not be placed on vhdl.org.... Paul -- Paul Menchini | email: mench@mench.com | WWW: http://www.mench.com/ Menchini & Associates | voice: 919-990-9506 | "Se tu sarai solo, 2 Davis Dr./POB 13036 | pager: 800-306-8494 | tu sarai tutto tuo." RTP, NC 27709-3036 | fax: 919-990-9507 | -- Leonardo Da Vinci From owner-math Thu Feb 22 17:47:59 1996 Received: from sndda3.edaca.ingr.com (sndda3.dazixca.ingr.com [129.135.106.126]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id RAA25258 for ; Thu, 22 Feb 1996 17:47:57 -0800 (PST) Received: by sndda3.edaca.ingr.com (4.1/SMI-4.1) id AA15435; Thu, 22 Feb 96 17:37:03 PST Date: Thu, 22 Feb 96 17:37:03 PST From: azamfire@sndda3.edaca.ingr.com (Alex Zamfirescu) Message-Id: <9602230137.AA15435@sndda3.edaca.ingr.com> To: math@vhdl.org, cswart@analogy.com Subject: Re: comments to ballots On Thu, 22 Feb 1996 10:41:35 -08 Dr: Charles F. Swart wrote: > Jose and I are trying to move forward on the Math Package approval process. > We very much appreciate comments from all of you on the two questions: > (1) Should we remove the package bodies from the documentation? > (2) Should we remove the complex functions involving polar arguments? > > However, I think that comments made by Paul and Alex require a clarification. > It was never the intention that the package bodies be used to define the > semantics of the functions. Let's clarify this. The confusion is between "semantics" and "normative" or required features. I used "semantics" as meaning "meaning" or "giving some meaning" (note not "complete or full semantics"). In my mind with real valued functions you can do one or more of the following: 1. Give complete semantics talking about the interval (value and tolerances, value and precision) 2. Give some meaning by specifying an algorithm (algorithm description plus minimal precision in VHDL real computations for the implemented tool) 4. Pretend that functions are well known from mathematics and require that the return values represent the mathematical values with a required precision 3. Not give any values or algorithm and expect the users to guess what the functions are. The choices are in pointing whichone (of the 1 to 4 above) is the "normative" and what else if anything you use to enforce implementation q_u_a_l_i_t_y. Without bodies 4 is normative and you get 6 decimals (if you are lucky and get somebody that knows your naming conventions - is sin the sine). You can also go through mathematics and clarify that, but you still get only 6 decimals of the value. If you give the bodies you have a better chance for correctness. You do not require ("normative") that the implementor follows your algorithm but give him a chance to come closer to the image of the ideal value if (s)he choses to compute the functions using your algorithms. Of course (s)he can use the bodies just to understand about which function you are talking about and implement it via direct calls in C. Even then your bodies can be used to check the implementations (most functions return over 9 exact decimals with 13 as typical). > In fact, the opposite is the case. The semantics > are intended to be defined in the package headers alone. There are (at least) > two reasons for this. First, the code in the package body was obtained from a > wide variety of sources, and its correctness cannot be guaranteed. Nobody tells you about the precision of the sin function in C either. The issue here is that the 6 decimals (only) required by VHDL make any noise invisible. > Implementations should not be expected to reproduce incorrect results which > the code in the package bodies could supply. Sure, but it's OK to execute the bodies when a function is called. One is what's OK the other is what is required. My claim is that without bodies and with the "math and 6 decimals" approach you still include any values that might be returned. If there are cases where that's not true, (I am not aware of such cases), you are still compliant if your tool returns the value obtained by executing the specified algorithm on your implementation, or any value closer to your implementation image of the mathematical, ideal value. > Second, the package bodies are > as portable as we could get. Consequently, the results produced are in many > cases not as accurate as could be obtained by implementation dependent methods. I completely agree with you on this. Here there is no point since you start with the assumption that the bodies can not be optimized which is not true. See the paragraph about implementations. > It is not desirable to restrict accuracy of implementations to the accuracy > supplied by the package bodies. Who does that? > > So vote as you see fit, but please don't expect the package bodies to supply > semantics. Since the rule is "at least execute the body on your implementation (which has to be VHDL 6 decimals compliant) if you can not do better" this last statement will (IMHO) at least in some cases not invalidated by pragmatics. The meaning comes from the bodies when there is no better way. Have a very nice weekend, hope to see you all at VIUF next week. Best regards, Alex Zamfirescu From owner-math Thu Feb 22 18:10:43 1996 Received: from tiny.sprintlink.net (tiny.sprintlink.net [199.0.55.90]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id SAA25409 for ; Thu, 22 Feb 1996 18:10:39 -0800 (PST) Received: from analogy.com (analogy.analogy.com [149.117.1.1]) by tiny.sprintlink.net (8.6.9/8.6.9) with SMTP id VAA15964 for ; Thu, 22 Feb 1996 21:02:12 -0500 Received: from miller.analogy.com by analogy.com (4.1/Shared_Spool_1.3) id AA07382; Thu, 22 Feb 96 18:04:24 PST Received: from glacier.analogy.com by miller.analogy.com (4.1/SMI-3.2) id AA13574; Thu, 22 Feb 96 18:04:22 PST Received: by glacier.analogy.com (5.x/SMI-SVR4) id AA07631; Thu, 22 Feb 1996 18:04:21 -0800 Date: Thu, 22 Feb 1996 18:04:21 -0800 From: cswart@analogy.com (Charles F. Swart) Message-Id: <9602230204.AA07631@glacier.analogy.com> To: math@vhdl.org Subject: semantics in math package bodies X-Sun-Charset: US-ASCII Let me make a clarification on my own "clarification." I stated that the semantics of the functions are intended to be defined in the package headers alone. I must point out that this was an early decision made by the math_package working group. As such, it is open for review, discussion, and possible reversal. From owner-math Mon Feb 26 17:59:29 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id RAA16774 for ; Mon, 26 Feb 1996 17:59:28 -0800 (PST) From: jtorres@ccmail-fremont.viewlogic.com Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA10694; Mon, 26 Feb 1996 20:26:21 +0500 Received: from ccmail-fremont.viewlogic.com (ccmail-fremont.vas.viewlogic.com) by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA14181; Mon, 26 Feb 96 17:49:46 PST Received: from ccMail by ccmail-fremont.viewlogic.com (SMTPLINK V2.10.08) id AA825385786; Mon, 26 Feb 96 17:44:21 pst Date: Mon, 26 Feb 96 17:44:21 pst Message-Id: <9601268253.AA825385786@ccmail-fremont.viewlogic.com> To: stds.dasc@ieee.org, math@vhdl.org Cc: mench@mench.mench.com Subject: Re: REVISED DASC Schedule at OVI/VIUF The VHDL Math meeting scheduled for Saturday March 2nd at 9 am will not take place. For update on status, please send a note to jose@vhdl.org Jose A. Torres Chair 1076.2 ______________________________ Reply Separator _________________________________ Subject: REVISED DASC Schedule at OVI/VIUF Author: "Paul J. Menchini" at Unix Date: 2/14/96 8:59 AM Ladies and Gentlemen of the DASC: Due to popular demand, I've moved all DASC meetings formerly scheduled for Monday to Saturday. All meetings start at 7:30 PM, except for the Saturday meetings. I'm trying to verify the availability of the Saturday rooms, but unless you hear differently, assume the Saturday meetings start at 9:00 AM. Also, VITAL has decided not to meet; Synthesis will take the vacated slot. The revised schedule is as follows: +-----------+----------------+-------------+----------+-----------+-----------+ | Day: | Tuesday | Wednesday | Thursday | Friday | Saturday | | Date: | 27 Feb | 28 Feb | 29 Feb | 1 Mar | 2 Mar | +-----------+----------------+-------------+----------+-----------+-----------+ | Meeting 1 | VHDL Synthesis | Lib IEEE | SVWG | DASC | VHDL Math | +-----------+----------------+-------------+----------+ +-----------+ | Meeting 2 | Parallel VHDL | OMI | Lib Util | Steering | OO-VHDL | +-----------+----------------+-------------+----------+ +-----------+ | Meeting 3 | HW/SW Codesign | Analog VHDL | Analog | Committee | WAVES | +-----------+----------------+-------------+----------+-----------+-----------+ Note that I still do not have specific room assignments. I will provide these as soon as I have them--at minimum, at OVI/VIUF. Paul From owner-math Wed Mar 13 16:15:23 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id QAA12225 for math@vhdl.org; Wed, 13 Mar 1996 16:15:23 -0800 (PST) Date: Wed, 13 Mar 1996 16:15:23 -0800 (PST) From: Jose Torres Message-Id: <199603140015.QAA12225@vhdl.vhdl.org> To: math@vhdl.org Subject: 1076.2 -- need your feedback on name changes As part of the ballots review process, it has been proposed to rename the functions FMAX and FMIN to MAX and MIN for clarity, since the F is not necessary in VHDL and can create confusion. This change would not cause these functions to break, but if there is a local definition for MAX and MIN then that definition would overwrite the 1076.2 definition. Also, models that are currently using FMAX or FMIN would need to be updated to reflect the change. We need your feedback as soon as possible on whether or not you would approve or disapprove this change. Please state your reasons. Thanks, Jose A. Torres From owner-math Fri Mar 22 14:56:13 1996 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id OAA05951; Fri, 22 Mar 1996 14:56:11 -0800 (PST) Received: (from mench@localhost) by mench.mench.com (8.6.9/8.6.9) id RAA07600; Fri, 22 Mar 1996 17:48:42 -0500 Date: Fri, 22 Mar 1996 17:48:42 -0500 From: "Paul J. Menchini" Message-Id: <199603222248.RAA07600@mench.mench.com> To: math@vhdl.org, jose@vhdl.org Subject: Re: 1076.2 -- need your feedback on name changes Cc: mench@mench.mench.com Jose, > As part of the ballots review process, it has been proposed to rename > the functions FMAX and FMIN to MAX and MIN for clarity, since the F > is not necessary in VHDL and can create confusion. > > This change would not cause these functions to break, but if there is > a local definition for MAX and MIN then that definition would overwrite > the 1076.2 definition. Also, models that are currently using FMAX or > FMIN would need to be updated to reflect the change. > > We need your feedback as soon as possible on whether or not you would > approve or disapprove this change. Please state your reasons. Sorry I didn't respond sooner, I've been out of town for 3 weeks and am wending my way through > 500 messages.... I think this is a bad idea. Unfortunately, there's a MIN in Std.Standard, so this doesn't work: process use IEEE..all; begin constant Minimum: := MIN (, ); You would get an error at the MIN, since both Std.Standard.MIN and IEEE..MIN would be "potentially directly visible," which, because of VHDL's use clause rules (as applied to these two names) results in an ambiguity. Regards, Paul From owner-math Thu Apr 11 04:46:08 1996 Received: from xr1.atlas.fr (xr1.atlas.fr [194.51.9.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with ESMTP id EAA14197; Thu, 11 Apr 1996 04:46:01 -0700 (PDT) X400-Received: by /PRMD=INTERNET/ADMD=ATLAS/C=FR/; Relayed; Thu, 11 Apr 1996 13:36:49 +0200 X400-Received: by mta xr1.atlas.fr in /PRMD=INTERNET/ADMD=ATLAS/C=FR/; Relayed; Thu, 11 Apr 1996 13:36:49 +0200 X400-Received: by /ADMD=ATLAS/C=FR/; Relayed; Thu, 11 Apr 1996 13:36:47 +0200 X400-Received: by /PRMD=THOMSON/ADMD=ATLAS/C=FR/; Relayed; Thu, 11 Apr 1996 14:35:53 +0200 Date: Thu, 11 Apr 1996 14:35:53 +0200 X400-Originator: LASSERRE@TTM.thomson.fr X400-Recipients: vital@vhdl.org, vhdlsynth@vhdl.org, TC93-wg2-request@hike.te.chiba-u.ac.jp, math@vhdl.org, libutil@vhdl.org, 1076-1@epfl.ch X400-MTS-Identifier: [/PRMD=THOMSON/ADMD=ATLAS/C=FR/;960411123553] X400-Content-Type: P2-1984 (2) Content-Identifier: CSI NC V3.0 Alternate-Recipient: Allowed From: Lasserre Sylvie Message-ID: <0002B600.MAI*/S=LASSERRE/O=TTM/PRMD=THOMSON/ADMD=ATLAS/C=FR/@MHS> To: "VHDL - 1076.1" <1076-1@epfl.ch> (Receipt Notification Requested) (Non Receipt Notification Requested), "VHDL - 1076.5" (Receipt Notification Requested) (Non Receipt Notification Requested), "VHDL - 1076.2" (Receipt Notification Requested) (Non Receipt Notification Requested), TC93-wg2-request (Receipt Notification Requested) (Non Receipt Notification Requested), "VHDL - 1076.3" (Receipt Notification Requested) (Non Receipt Notification Requested), "VHDL - 1076.4" (Receipt Notification Requested) (Non Receipt Notification Requested) Subject: new email Please note my new email adress: lasserre@ttm.thomson.fr From owner-math Fri May 17 16:13:38 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id QAA22232 for math@vhdl.org; Fri, 17 May 1996 16:13:38 -0700 (PDT) Date: Fri, 17 May 1996 16:13:38 -0700 (PDT) From: Jose Torres Message-Id: <199605172313.QAA22232@vhdl.vhdl.org> To: math@vhdl.org Subject: Status Update on VHDL Mathematical Packages (1076.2) The purpose of this communication is to update you on the status of the VHDL Mathematical Packages Standard (P1076.2). As many of you know, the P1076.2 standard received 86% of affirmative votes. The voting breakdown was as follows: Total in balloting group 88 Total eligible to vote 72 Affirmative votes 46 Negative votes 7 Abstentions 2 Over the last 6 months, the Working Group has been engaged in discussing and corresponding with various negative voters and balloters who have sent in comments. As a result of these efforts some negative voters have changed their votes to yes votes. All the comments regarding typos, style, and editorial changes have been taken care of. In addition, some technical changes were required. The major changes are 1. Renaming of some constants (e.g., MATH_HALF_PI as MATH_PI_OVER_2) and functions (e.g., FMAX and FMIN as REALMAX and REALMIN) 2. Addition of some constants (e.g., MATH_PI_OVER_3) 3. Modification of (sub)types of the arguments SEED1 and SEED2 in UNIFORM from INTEGER to POSITIVE and of the argument BASE in LOG from POSITIVE to REAL 4. Correction of severity level of some errors from NOTE to ERROR 5. Addition of the following functions of type REAL: LOG2 and LOG10 6. Addition of the following subtypes for elements of type COMPLEX_POLAR: POSITIVE_REAL and PRINCIPAL_VALUE 7. Modification of the COMPLEX_POLAR type to use new subtypes 8. Addition of the following functions of type COMPLEX and COMPLEX_POLAR: LOG(Z, BASE), LOG2, LOG10, SIN, COS, ARCSIN, ARCCOS. 9. Addition of the following functions of type COMPLEX_POLAR: GET_PRINCIPAL_VALUE 10. Overloading of the following relational operators for type COMPLEX_POLAR: "=" and "/=" 11. Modification of valid range of values for COMPLEX_POLAR functions to be the principal value (i.e., -MATH_PI < ARG(result) <= MATH_PI) 12. Modification of the type of the value returned for the following functions in MATH_COMPLEX: ABS and ARG. Types were changed from REAL to POSITIVE_REAL and PRINCIPAL_VALUE respectively 13. Additional details on what the normative and informative parts of the document are (in paticular, the package bodies are informative only), as well as changes in organization and coding style for reserved and non-reserved words. As a result of these changes a new ballot will be recirculated to the members of the balloting group. The documentation has been sent to IEEE, and we expect the new ballots to go out no later than June. New versions of the package declarations and package bodies have been created, as well as a set of test benches for MATH_REAL and MATH_COMPLEX. As per new IEEE regulations, the new version of the packages are not available for free distribution any longer. If you wish to have access to a copy of the new version of the packages, please contact: Cheryl Rowden IEEE Standards Activities Phone: (908)562-3804 e-mail: c.rowden@ieee.org However, the test benches are available for free distribution and are located in the machine sponsored by VHDL International at: http://vhdl.org/vi/math/testbench/real_tests.vhd http://vhdl.org/vi/math/testbench/complex_tests.vhd Thanks for your interest and participation in this effort. Sincerely, Jose A. Torres Chair, IEEE P1076.2 PS> If you are a member of the balloting group and you have changed your address since last June 95, please communicate your new address as soon as possible to Carol Buonfiglio IEEE Standards Department 445 Hoes Lane Piscataway NJ 08855-1331 FAX: (908) 562-1571 e-mail: c.buonfiglio@ieee.org Thanks. From owner-math Sun May 19 13:04:57 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id NAA23140 for math@vhdl.org; Sun, 19 May 1996 13:04:57 -0700 (PDT) Date: Sun, 19 May 1996 13:04:57 -0700 (PDT) From: Jose Torres Message-Id: <199605192004.NAA23140@vhdl.vhdl.org> To: math@vhdl.org Subject: catalog of parts in new version of Math packages (1076.2) For your information, here is a list of constants and functions in the new version of the packages MATH_REAL and MATH_COMPLEX. Constants and functions are grouped by area of functionality rather than by alphabetical order. Constants of type REAL in MATH_REAL: MATH_E MATH_LOG_OF_2 MATH_DEG_TO_RAD MATH_1_OVER_E MATH_LOG_OF_10 MATH_RAD_TO_DEG MATH_LOG2_OF_E MATH_PI MATH_LOG10_OF_E MATH_2_PI MATH_1_OVER_PI MATH_SQRT2 MATH_PI_OVER_2 MATH_SQRT1_OVER_2 MATH_PI_OVER_3 MATH_SQRT_PI MATH_PI_OVER_4 MATH_3_PI_OVER_2 Functions/procedures of type REAL in MATH_REAL: SIGN(X) EXP(X) SINH(X) CEIL(X) LOG(X) COSH(X) FLOOR(X) LOG2(X) TANH(X) ROUND(X) LOG10(X) TRUNC(X) LOG(X, BASE) ARCSINH(X) "MOD"(X, Y) ARCCOSH(X) SIN(X) ARCTANH(X) REALMAX(X, Y) COS(X) REALMIN(X, Y) TAN(X) UNIFORM(SEED1, SEED2, X) ARCSIN(X) ARCCOS(X) SQRT(X) ARCTAN(Y) CBRT(X) ARCTAN(Y, X) "**"(X, Y) Types and subtypes in MATH_COMPLEX: COMPLEX POSITIVE_REAL COMPLEX_POLAR PRINCIPAL_VALUE Constants of type COMPLEX in MATH_COMPLEX: MATH_CBASE_1 MATH_CBASE_J MATH_CZERO Type conversion functions for COMPLEX and COMPLEX_POLAR in MATH_COMPLEX: CMPLX(X, Y) POLAR_TO_COMPLEX(Z) COMPLEX_TO_POLAR(Z) GET_PRINCIPAL_VALUE(X) Overloaded relational functions for type COMPLEX_POLAR in MATH_COMPLEX: "="(L, R) "/="(L, R) Functions for arguments of type COMPLEX and COMPLEX_POLAR in MATH_COMPLEX: "ABS"(Z) EXP(Z) SIN(Z) ARG(Z) LOG(Z) COS(Z) LOG2(Z) "-"(Z) LOG10(Z) SINH(Z) CONJ(Z) LOG(Z, BASE) COSH(Z) SQRT(Z) Arithmetic functions for arguments of type COMPLEX and COMPLEX_POLAR in MATH_COMPLEX: "+" "*" "-" "/" Regards, Jose A. Torres From owner-math Fri May 24 13:19:44 1996 Received: from vdd.VLSI.LL.MIT.EDU (VDD.VLSI.LL.MIT.EDU [129.55.10.3]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id NAA15217 for ; Fri, 24 May 1996 13:19:43 -0700 (PDT) Received: (from anderson@localhost) by vdd.VLSI.LL.MIT.EDU (8.6.12/8.6.12) id QAA17507 for math@vhdl.org; Fri, 24 May 1996 16:09:00 -0400 Date: Fri, 24 May 1996 16:09:00 -0400 From: "Allan H. Anderson" Message-Id: <199605242009.QAA17507@vdd.VLSI.LL.MIT.EDU> To: math@vhdl.org Subject: Where can I get a copy of the VHDL math package? I have a copy of Vers. 0.7 of the draft math package but the original owner changed the atan2 and round functions. I would like to compare with either the original or the most recent version. I could not get into the vhdl.org:vi/math/package. Please respond directly, I am not on this reflector. Thank you, Allan H. Anderson MIT Lincoln Laboratory anderson@ll.mit.edu From owner-math Mon Jun 10 23:22:05 1996 Received: from hitel.kol.net (hitel.kol.co.kr [204.252.145.2]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id XAA20851 for ; Mon, 10 Jun 1996 23:22:03 -0700 (PDT) From: Doggy@hitel.kol.co.kr Received: (from root@localhost) by hitel.kol.net (8.6.9H1/8.6.9) id PAA20782 for math@vhdl.org; Tue, 11 Jun 1996 15:16:13 +0900 Date: Tue, 11 Jun 1996 15:16:13 +0900 Message-Id: <199606110616.PAA20782@hitel.kol.net> Subject: subscribe Apparently-To: math@vhdl.org subscribe From owner-math Mon Jun 10 23:46:39 1996 Received: from hitel.kol.net (hitel.kol.co.kr [204.252.145.2]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id XAA21243 for ; Mon, 10 Jun 1996 23:46:31 -0700 (PDT) From: Doggy@hitel.kol.co.kr Received: (from root@localhost) by hitel.kol.net (8.6.9H1/8.6.9) id PAA26648 for math@vhdl.org; Tue, 11 Jun 1996 15:40:29 +0900 Date: Tue, 11 Jun 1996 15:40:29 +0900 Message-Id: <199606110640.PAA26648@hitel.kol.net> Subject: Apparently-To: math@vhdl.org e From owner-math Tue Jun 11 01:15:13 1996 Received: from camcon.co.uk (io.camcon.co.uk [193.35.220.5]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id BAA22107 for ; Tue, 11 Jun 1996 01:15:11 -0700 (PDT) Received: from esprit.camcon.co.uk by camcon.co.uk (4.1/SMI-4.1) id AA17831; Tue, 11 Jun 96 09:00:30 BST Received: from ccMail by esprit.camcon.co.uk (IMA Internet Exchange 1.04b) id 1bd28760; Tue, 11 Jun 96 09:04:06 +0100 Mime-Version: 1.0 Date: Tue, 11 Jun 1996 08:56:02 +0100 Message-Id: <1bd28760@camcon.co.uk> From: Graham.Pink@camcon.co.uk (Graham Pink) To: Doggy@hitel.kol.co.kr, math@vhdl.org Subject: Re: subscribe Content-Type: multipart/mixed; boundary="IMA.Boundary.642084438" This is a Mime message, which your current mail reader may not understand. Parts of the message will appear as text. To process the remainder, you will need to use a Mime compatible mail reader. Contact your vendor for details. --IMA.Boundary.642084438 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Description: cc:Mail note part Has my mail address been added to a reflector or something ? Graham Pink gpp@camcon.co.uk __________Original message from Doggy@hitel.kol.cp.kr_______ subscribe --IMA.Boundary.642084438 Content-Type: text/plain; charset=US-ASCII; name="RFC822 message headers" Content-Transfer-Encoding: 7bit Content-Description: cc:Mail note part Received: from io by esprit.camcon.co.uk with SMTP (IMA Internet Exchange 1.04b) id 1bd13280; Tue, 11 Jun 96 07:33:13 +0100 Received: from ganymede.camcon.co.uk by camcon.co.uk (4.1/SMI-4.1) id AA13208; Tue, 11 Jun 96 07:29:20 BST Received: by ganymede.camcon.co.uk (4.1/SMI-4.1) id AA05335; Tue, 11 Jun 96 07:29:17 BST Received: from vhdl.vhdl.org(198.31.14.3) by ganymede.camcon.co.uk via smap (V1.3 ) id sma005330; Tue Jun 11 07:29:02 1996 Received: from hitel.kol.net (hitel.kol.co.kr [204.252.145.2]) by vhdl.vhdl.org ( 8.7.3/8.7.3) with SMTP id XAA20851 for ; Mon, 10 Jun 1996 23:22:03 -0700 (PDT) From: Doggy@hitel.kol.co.kr Received: (from root@localhost) by hitel.kol.net (8.6.9H1/8.6.9) id PAA20782 for math@vhdl.org; Tue, 11 Jun 1996 15:16:13 +0900 Date: Tue, 11 Jun 1996 15:16:13 +0900 Message-Id: <199606110616.PAA20782@hitel.kol.net> Subject: subscribe Apparently-To: math@vhdl.org --IMA.Boundary.642084438-- From owner-math Tue Jun 11 09:02:22 1996 Received: from sunset.backbone.olemiss.edu (eehanson@sunset.backbone.olemiss.edu [130.74.1.75]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id JAA02710; Tue, 11 Jun 1996 09:02:20 -0700 (PDT) Received: by sunset.backbone.olemiss.edu (940816.SGI.8.6.9/930416.SGI) id KAA17136; Tue, 11 Jun 1996 10:52:42 -0500 Date: Tue, 11 Jun 1996 10:52:42 -0500 From: eehanson@sunset.backbone.olemiss.edu (Donald F Hanson) Message-Id: <199606111552.KAA17136@sunset.backbone.olemiss.edu> To: eehanson@sunset.backbone.olemiss.edu, math@vhdl.org, jose@vhdl.org Subject: Ballot Hi-- It looks like you've been doing a lot of work. I haven't had time to test the package yet, but I looked it over carefully. I will be voting Affirmative, with comments. The only comments that I have are about Annex A.8--side effect. It is not clear to me why both COMPLEX and COMPLEX_POLAR are needed when there is a simple conversion between them. There may be implementers that do not want both in their system. Should the IEEE standard force them to do both? Why not make the package compact--COMPLEX only and then have conversions? Also, a reference to CORDIC is needed. Otherwise it looks good. Keep me posted. Thanks. --Don _______ / | ====/ * |=============================================================== | / Oxford | Dr. Donald F. Hanson Department of | | / | Associate Professor Electrical Engineering | | \ | Fax: (601)232-7231 University of Mississippi | | | | Phone: (601)232-5389 University, MS | | / | eehanson@sunset.backbone.olemiss.edu 38677 | ===/ |=============================================================== |______ | / | \____| From owner-math Thu Jun 13 08:48:16 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id IAA01276 for math@vhdl.org; Thu, 13 Jun 1996 08:48:16 -0700 (PDT) Date: Thu, 13 Jun 1996 08:48:16 -0700 (PDT) From: Jose Torres Message-Id: <199606131548.IAA01276@vhdl.vhdl.org> To: math@vhdl.org Subject: 1076.2 Balloting If you are not part of the balloting group, please ignore this message. Due to mail delays as well as the fact that DAC took place in the middle of the balloting period and several people were travelling at the time, the deadline to return the ballots has been extended to June 30, 1996. Please make sure to return your ballots by that date. Thanks again for your participation. Regards, Jose A. Torres Chair, P1076.2 From owner-math Wed Jul 24 03:42:33 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id DAA06646 for math@vhdl.org; Wed, 24 Jul 1996 03:42:33 -0700 (PDT) Date: Wed, 24 Jul 1996 03:42:33 -0700 (PDT) From: Jose Torres Message-Id: <199607241042.DAA06646@vhdl.vhdl.org> To: math@vhdl.org Subject: Results on Reballoting of 1076.2 Dear P1076.2 (IEEE Standard VHDL Mathematical Packages) balloting members and interested parties, Thank you very much for your comments and participation in the recirculation and balloting of P1076.2. I am glad to report that the P1076.2 standard received 96% of affirmative votes. The voting breakdown is given below: Total eligible to vote 72 Affirmative votes 54 Negative votes 2 Abstentions 2 Total votes 58 % of returned votes 80% % of affirmative votes 96% All the comments regarding typos, style, and editorial changes will be taken care of in the final version of the P1076.2 document. The two negative votes are part of the negative votes from the first balloting of P1076.2, and no new negative votes came in on the changes made to the recirculated draft. The negative votes cannot be resolved, since they are requesting a change in the IEEE distribution policies for the standard in order to change the vote to affirmative. No technical changes will be made to the final version of the document. The current plans are to submit the final version of the document for final approval to the IEEE Standards Department Board before their next meeting (September 96). Thanks again for your participation and making this balloting process a success. Best regards, Jose A. Torres Chair, IEEE P1076.2 Working Group E-mail: jose@vhdl.org From owner-math Tue Aug 20 10:06:48 1996 Received: (from jose@localhost) by vhdl.vhdl.org (8.7.3/8.7.3) id KAA06406 for math; Tue, 20 Aug 1996 10:06:48 -0700 (PDT) Date: Tue, 20 Aug 1996 10:06:48 -0700 (PDT) From: Jose Torres Message-Id: <199608201706.KAA06406@vhdl.vhdl.org> To: math Subject: DASC meetings at EuroDAC FYI, Dear Group Chairs and Members of DASC Below is the plan for Working Group meetings to be held at the EuroDAC with EuroVHDL conferences at Geneva. Please cascade this message to your group members. Group meetings will be as outlined below. Tuesday September 17, 6-9 pm Room 1 Hardware/Software Co-Design Room 2 Open Modelling Wednesday September 18, 6-9 pm Room 1 WAVES Room 2 VHDL Analog & Mixed Signal Thursday September 19, 6-9 pm Room 1 OO-VHDL Room 2 Synthesis Tutorial by Alex Samfirescu Room 3 Shared Variable & Parallel Simulation These meetings will be held at the conference centre. All room allocations will be displayed on a notice board at the reception, also will be supported by enquiries at the conference reception desk. Friday September 20 (all day) 8.30 - 11.30 DASC Plenary Session (with a coffee break midway) Agenda: Status report from each of Group Chairs plus a short report from: Professor Imai (EIAJ); Jose Torres (Math); Paul Menchini (VASG)and Ron Waxman (IEC/TC93) Each lasting no more than 15 minutes including discussions. 11.30 - 13.00 Steering Meeting Agenda to be provided by Victor Berman at the meeting. 13.00 - 14.00 Lunch Break on your own 14.00 - 18.00 (to finish) VASG meeting chaired by Paul Menchini, VHDL'98. Meetings on Friday September 20, will be held in "Villa Sarrasin" (3 min. from the conference location). One room (50 persons) will be available the whole day. Two coffee breaks are planned (one in the morning, and one in the afternoon). This room is provided with the compliment of Mentor Graphics Switzerland. The DASC membership would like to express our thanks for this generous contribution. Our thanks also go to Alain Vachoux for arranging meeting rooms. See you all at Geneva. Best regards John Hillawi DADSC Vice Chair DA Solutions Limited, 10 Galemoor Avenue, Gosport, PO12 2SJ, Uk Tel: +44 1705 365 473, Fax: +44 1705 526 630 Email: hillawi@cix.compulink.co.uk (or) John.Hillawi@dasl.compulink.co.uk URL: http://www.compulink.co.uk/~dasl/ ************************************************************************** * Are you about to select your next VHDL or Verilog simulator? * * Do you want to know how well your current simulator is performing? * * Get the latest DA Solutions' Simulators Benchmark Report for 1995/96 * ************************************************************************** From owner-math Tue Oct 1 10:14:20 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id KAA12966 for ; Tue, 1 Oct 1996 10:14:19 -0700 (PDT) From: jtorres@ccmail-fremont.VAS.viewlogic.com Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA08877; Tue, 1 Oct 1996 13:03:10 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA25943; Tue, 1 Oct 96 10:03:05 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.10.08) id AA844188812; Tue, 01 Oct 96 10:00:07 pst Date: Tue, 01 Oct 96 10:00:07 pst Message-Id: <9609018441.AA844188812@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org, stds.dasc.sc@ieee.org Subject: VHDL Mathematical Packages (1076.2) I am glad to announce that the proposal for IEEE P1076.2 (VHDL Mathematical Packages) was approved by the IEEE Standards Board during their meeting on September 19, 1996. Work to put in place the final documentation is on its way. Thanks a lot to all of you who contributed to make it happen. Regards, Jose A. Torres Chair IEEE P1076.2 From owner-math Thu Oct 3 12:12:34 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id MAA08246 for ; Thu, 3 Oct 1996 12:12:31 -0700 (PDT) From: jtorres@ccmail-fremont.VAS.viewlogic.com Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA19606; Thu, 3 Oct 1996 15:01:27 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA27217; Thu, 3 Oct 96 12:01:22 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.10.08) id AA844368276; Thu, 03 Oct 96 11:50:48 pst Date: Thu, 03 Oct 96 11:50:48 pst Message-Id: <9609038443.AA844368276@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: Future of VHDL Workshop FYI, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: Future of VHDL Workshop Author: Victor Berman at Unix Date: 10/3/96 11:32 AM Dear WG Chairs, Please pass this invitation on to your working groups or other interested parties. thanks, Victor ---------------------------------------------------------------------------- ---------------- Invitation to the Future of VHDL Workshop October 31, November 1, 1996 Following the Fall '69 VIUF The Arts council - Adaron Hall Durham NC This invitation is extended to all people who are interested in working on and influencing the future of VHDL. VHDL is soon to be re-standardized for the second time. During the period of VHDL's existence the world of electronic design has changed dramatically. In the interest of seeing that VHDL continues to be a central part of electronic design, we must ensure that VHDL keeps pace with the industry and moves in relevant directions. This workshop is aimed at determining how best to do this and setting in place the organizational structural to support the needed growth. The workshop will begin on Thursday morning with presentations by leaders in the field on there perspectives of the future of VHDL. On the afternoon we will have discussion and breakout groups to focus on near terma and long term plans for VHDL. Presentations will include a perspective on system level design coming out of the recent workshop held in Dallas on this topic. This will provide a focused view on how VHDL can best support system level design in the future. Other presentations will cover issues of language complexity, object oriented paradigms, and growth in related areas such as analog, mixed signal. Other topics of interest are the relationship of the language to initiatives such as VSI, OMF, and RASSP. The second day of the workshop will be spent honing the ideas generated on the first day and mapping out an organizational structure to support the re-standardization efforts. If you are interested in attending and are willing to work on these topics please return the enclosed registration form. To keep this session workable, attendance will be limited to approximatley forty people. Victor Berman DASC Chair ----------------------------------------------------------------- REGISTRATION FORM: Future of VHDL Workshop October 31, November 1, 1996 Sponsored by IEEE VASG and VI Please reply to beman@cadence.com *** No phone registrations, please *** Confirmation will be sent via email or Fax NAME: ________________________________________________________ TITLE: _______________________________________________________ AFFILIATION: _________________________________________________ ADDRESS: _____________________________________________________ _____________________________________________________ CITY/STATE/ZIP: ______________________________________________ COUNTRY: ____________________ PHONE: ______________________ FAX: _______________________ EMAIL ADDRESS: _______________________________ I Will Attend: ___Both Days ___1st Day Only ___2nd Day Only Any Special Needs: ___________________________________________ Victor Berman tel: 508 446 6276 Cadence Design Systems, Inc. fax: 508 446 6665 270 Billerica Road e-mail: berman@cadence.com Chelmsford MA 01824 Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.10.08) ; Thu, 03 Oct 96 11:31:47 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA27005; Thu, 3 Oct 96 11:41:11 PDT Received: from vhdl.vhdl.org by mailhost.viewlogic.com (5.0/SMI-4.1) id AA19155; Thu, 3 Oct 1996 14:41:08 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id LAA08101; Thu, 3 Oct 1996 11:51:31 -0700 (PDT) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.6.9/8.6.9) with ESMTP id OAA07308 for ; Thu, 3 Oct 1996 14:07:24 -0400 Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id NAA29517 for stds-dasc-sc-list; Thu, 3 Oct 1996 13:58:30 -0400 (EDT) Message-Id: <2.2.32.19961003175433.00713cdc@gda> X-Sender: berman@gda X-Mailer: Windows Eudora Pro Version 2.2 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Thu, 03 Oct 1996 13:54:33 -0400 To: stds.dasc.sc@ieee.org From: Victor Berman Subject: Future of VHDL Workshop Sender: owner-stds-dasc-sc@mail.ieee.org Precedence: bulk Reply-To: Victor Berman X-Resent-To: Multiple Recipients X-Listname: stds-dasc-sc X-List-Description: Mailing-List: stds-dasc-sc X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org Content-Length: 3430 From owner-math Fri Oct 4 16:57:00 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id QAA07931 for ; Fri, 4 Oct 1996 16:56:59 -0700 (PDT) From: jtorres@ccmail-fremont.VAS.viewlogic.com Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA12208; Fri, 4 Oct 1996 19:45:54 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA11825; Fri, 4 Oct 96 16:45:51 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.10.08) id AA844472181; Fri, 04 Oct 96 16:37:40 pst Date: Fri, 04 Oct 96 16:37:40 pst Message-Id: <9609048444.AA844472181@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: VIUF FAll '96 FYI, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: VIUF FAll '96 Author: Victor Berman at Unix Date: 10/4/96 8:08 AM As most of you probably know the Fall 1996 VHDL International User's Forum will be taking place in Durham NC during the week of Oct 27. For details, see the web page at http://vhdl.org/vi/viuf/brochure_fall96.html Please pass this information on to all interested groups including the DASC WGs and SGs. thanks, Victor PS: if people cannot access the web site let me know - I can send ASCII version of the program. Victor Berman tel: 508 446 6276 Cadence Design Systems, Inc. fax: 508 446 6665 270 Billerica Road e-mail: berman@cadence.com Chelmsford MA 01824 Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.10.08) ; Fri, 04 Oct 96 08:07:30 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA06741; Fri, 4 Oct 96 08:16:46 PDT Received: from vhdl.vhdl.org by mailhost.viewlogic.com (5.0/SMI-4.1) id AA02806; Fri, 4 Oct 1996 11:16:44 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id IAA03647; Fri, 4 Oct 1996 08:26:38 -0700 (PDT) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.6.9/8.6.9) with ESMTP id KAA07868 for ; Fri, 4 Oct 1996 10:48:34 -0400 Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id KAA04733 for stds-dasc-list; Fri, 4 Oct 1996 10:41:11 -0400 (EDT) Message-Id: <2.2.32.19961004143812.006da440@gda> X-Sender: berman@gda X-Mailer: Windows Eudora Pro Version 2.2 (32) Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Date: Fri, 04 Oct 1996 10:38:12 -0400 To: stds.dasc@ieee.org From: Victor Berman Subject: VIUF FAll '96 Sender: owner-stds-dasc@mail.ieee.org Precedence: bulk Reply-To: Victor Berman X-Resent-To: Multiple Recipients X-Listname: stds-dasc X-List-Description: Mailing-List: stds-dasc X-Info: Help requests to stds-dasc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-approval@majordomo.ieee.org Content-Length: 601 From owner-math Mon Nov 4 20:44:30 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id UAA04293 for ; Mon, 4 Nov 1996 20:44:29 -0800 (PST) Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA23667; Mon, 4 Nov 1996 23:33:07 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA03221; Mon, 4 Nov 96 20:33:02 PST Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA847168355; Mon, 04 Nov 96 20:24:00 pst Date: Mon, 04 Nov 96 20:24:00 pst From: "Jose Torres" Message-Id: <9610048471.AA847168355@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: DASC membership FYI, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: DASC membership Author: Victor Berman at Unix Date: 11/4/96 2:20 PM ---------- X-Sun-Data-Type: text X-Sun-Data-Description: text X-Sun-Data-Name: text X-Sun-Charset: us-ascii X-Sun-Content-Lines: 5 Plese pass on this message about joining the DASC for the next year to you working group. thanks, Victor ---------- X-Sun-Data-Type: default X-Sun-Data-Description: default X-Sun-Data-Name: 97-app-form X-Sun-Content-Lines: 81 X-Sun-Charset: us-ascii DASC APPLICATION FOR MEMBERSHIP The Design Automation Standards Committee is moving into its fourth year under its new charter. This group is responsible for the standardization of work related to design automation in the electronics industry, one of the fastest growing technology areas of the 1990s. The group began with the successful development of the VHDL standard and is now working on related standards in the logic synthesis, analog simulation, timing verification, and mathematical areas for design verification. The group has also undertaken the standardization of Verilog. Membership in the DASC is the fundamental way in which to support these activities. Membership is a requirement for voting privileges in any of the working or study groups under the DASC as well as for DASC officers. Highlights of the DASC Membership Membership is on a subscription basis. The yearly dues has been reduced to $50. This fee will cover membership for all of calendar year 1967. Minutes/ Meeting minutes and technical documents will be distributed Mailing electronically and hard copy mailing will be kept to a minimum. Elections All DASC officers, including the DASC Chair and Working and Study Group Chairs are elected by the DASC membership. Administration of the DASC is now being handled directly by IEEE. Please send completed application forms and payment to: DASC C/O Tracy Woods IEEE Computer Society 1730 Massachusetts Avenue, NW Washington, DC 20036-1992 FAX: 202-728-0884 (for credit card payment) Complete and Return by mail or fax with dues of $50.00 US (checks must be payable on a US bank) to "IEEE Computer Society DASC": Name: _______________________________________________________________ Affiliation: _______________________________________________________________ Address: _______________________________________________________________ _______________________________________________________________ City: ______________________________________________ State: ________ Postal Code: _____________________ Country: ______________________________ Telephone: _____________________ Fax: ______________________________ EMail: _______________________________________________________________ For Credit Card Orders Only: Name on Card: _______________________________________________________________ Type of Card: _________________ (American Express, Visa, MasterCard only) Card Number: _______________________________________________________________ Expiration: ______ Signature: ____________________________________________ Optional Information: IEEE Member Number: _______________________________________ Other Professional Affiliations: _______________________________________ Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Mon, 04 Nov 96 14:20:24 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA00455; Mon, 4 Nov 96 14:20:47 PST Received: from vhdl.vhdl.org by mailhost.viewlogic.com (5.0/SMI-4.1) id AA19340; Mon, 4 Nov 1996 17:20:43 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id OAA01135; Mon, 4 Nov 1996 14:30:54 -0800 (PST) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.6.9/8.6.9) with ESMTP id QAA02612 for ; Mon, 4 Nov 1996 16:55:33 -0500 Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id QAA10092 for stds-dasc-sc-list; Mon, 4 Nov 1996 16:49:45 -0500 (EST) Date: Mon, 4 Nov 1996 16:02:57 -0500 From: Victor Berman Message-Id: <199611042102.QAA00111@pebbles> To: stds.dasc.sc@ieee.org Subject: DASC membership Content-Type: X-sun-attachment Sender: owner-stds-dasc-sc@majordomo.ieee.org Precedence: bulk Reply-To: Victor Berman X-Resent-To: Multiple Recipients X-Listname: stds-dasc-sc X-List-Description: Mailing-List: stds-dasc-sc X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org Content-Length: 3222 From owner-math Tue Nov 5 17:35:05 1996 Received: from newsgw.mentorg.com (newsgw.mentorg.com [137.202.128.5]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id RAA29844; Tue, 5 Nov 1996 17:34:58 -0800 (PST) Received: from wv.wv.mentorg.com by newsgw.mentorg.com (8.6.8.1/CF5.22R) id RAA15346; Tue, 5 Nov 1996 17:14:50 -0800 Received: from em-wv03.wv.mentorg.com by wv.wv.mentorg.com (8.6.8.1/CF5.22R) id RAA27272; Tue, 5 Nov 1996 17:14:48 -0800 Received: from hpmos.wv.mentorg.com by em-wv03.wv.mentorg.com (8.6.8.1/CF5.23H) id RAA20174; Tue, 5 Nov 1996 17:16:21 -0800 Received: from wv133dyn93.wv.mentorg.com by hpmos.wv.mentorg.com (1.37.109.4/CF5.18L) id AA03764; Tue, 5 Nov 96 17:08:26 -0800 Message-Id: <9611060108.AA03764@hpmos.wv.mentorg.com> Date: Tue, 05 Nov 1996 17:16:05 -0800 From: dennisb@vhdl.org (Dennis Brophy) Reply-To: dennisb@vhdl.org Subject: IEEE Delay & Power Calculation Standard Newsgroups: comp.sys.mentor,comp.cad.cadence,comp.cad.compass,comp.cad.synthesis,comp.lsi.cad Organization: VHDL International Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: <1364core@galazy.nsc.com> Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: Apparently-To: NOTE: Please excuse multiple deliveries of this message. You are self-identified as a person interested in design automation standards, or lower power design. In keeping with IEEE goals to ensure broad user, academic and producer participation, this message is being sent once to special interest groups. *** *** *** ANNOUNCEMENT IEEE Delay & Power Calculation Standard Formation *** *** *** The IEEE Design Automation Standards Committee (DASC) has recently formed a study group to standardize the OVI/CFI Delay Calculation System (DCS) which includes the Delay Calculation Language (DCL). The group is authorized under IEEE Project Authorization Request P1481 to develop a delay and power calculation standard. You are invited to monitor or participate in this activity. If you have concerns about how nano-meter integrated circuit geometries impact the modeling of timing for integrated circuits, the creation of tools which facilitate low-power design, design verification or layout tools which share coherent timing and power information, then you may wish to monitor or participate in this effort. If you support, use or develop static timing analysis tools, floorplanners, dynamic timing simulators, power estimators and analyzers, synthesis tools, delay calculators or synthesis optimizers (and more!) the delay and power calculation methods will have an impact on you. This standard will truly benefit designers, semiconductor suppliers and EDA software suppliers. IEEE Delay and Power Calculation Scope: Delay and power calculation for integrated circuit design. IEEE Delay and Power Calculation Scope: To provide a standard system for integrated circuit designers to consistently calculate chip delay and power across Electronic Design Automation (EDA) applications and for integrated circuit vendors to express delay and power information only once per technology while enabling sufficient EDA application accuracy. To monitor the group9s activities, you can subscribe to the IEEE Delay and Power Calculation (DPC) special interest group email exploder. To subscribe, send a message to majordomo@vhdl.org. In the body of the message enter the following: subscribe dpc The delay and power calculation study group is comprised of four subgroup: o Architecture dpcwg-arch@vhdl.org o Language dpcwg-lang@vhdl.org o Parasitics and Clustering dpcwg-pandc@vhdl.org o Power dpcwg-pwr@vhdl.org For more information, visit our web site at: http://vhdl.org/vi/dpc Or, if you would like to discuss this in more detail, you can reply to this message or contact me at the numbers listed below. Regards, Dennis Brophy Chair, IEEE P1481 -- Dennis B. Brophy Phone: +1-503-685-1415 Mentor Graphics Corporation FAX: +1-503-685-1268 8005 SW Boeckman Rd Email: dennis_brophy@mentorg.com Wilsonville, OR 97070-7777 dennisb@vhdl.org From owner-math Wed Nov 6 00:38:26 1996 Received: from newsgw.mentorg.com (newsgw.mentorg.com [137.202.128.5]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id AAA04349; Wed, 6 Nov 1996 00:38:24 -0800 (PST) Received: from wv.wv.mentorg.com by newsgw.mentorg.com (8.6.8.1/CF5.22R) id AAA01656; Wed, 6 Nov 1996 00:24:13 -0800 Received: from em-wv03.wv.mentorg.com by wv.wv.mentorg.com (8.6.8.1/CF5.22R) id AAA02816; Wed, 6 Nov 1996 00:24:12 -0800 Received: from hpmos.wv.mentorg.com by em-wv03.wv.mentorg.com (8.6.8.1/CF5.23H) id AAA02541; Wed, 6 Nov 1996 00:25:45 -0800 Received: from wv133dyn100.wv.mentorg.com by hpmos.wv.mentorg.com (1.37.109.4/CF5.18L) id AA05402; Wed, 6 Nov 96 00:17:36 -0800 Message-Id: <9611060817.AA05402@hpmos.wv.mentorg.com> Date: Wed, 06 Nov 1996 00:25:15 -0800 From: dennisb@vhdl.org (Dennis Brophy) To: dennisb@vhdl.org Reply-To: dennisb@vhdl.org Subject: [Correction] IEEE Delay & Power Calculation Standard Newsgroups: comp.sys.mentor,comp.cad.cadence,comp.cad.compass,comp.cad.synthesis,comp.lsi.cad Organization: VHDL International The subscription list name given in the previous message regarding the IEEE Delay and Power Calculation (P1481) standardization effort was incorrect. To subscribe, send the following command in the body of an email message to majordomo@vhdl.org: subscribe dpc-list Regards, Dennis -- Dennis B. Brophy Phone: +1-503-685-1415 Mentor Graphics Corporation FAX: +1-503-685-1268 8005 SW Boeckman Rd Email: dennis_brophy@mentorg.com Wilsonville, OR 97070-7777 dennisb@vhdl.org From owner-math Tue Nov 12 12:37:08 1996 Received: from europa.fae.ub.es (europa.fae.ub.es [161.116.79.225]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id MAA14281 for ; Tue, 12 Nov 1996 12:37:06 -0800 (PST) Received: from europa (europa.fae.ub.es) by europa.fae.ub.es (4.1/SMI-4.1) id AA05990; Tue, 12 Nov 96 21:25:38 +0100 Sender: chema@europa.fae.ub.es Message-Id: <3288DD41.794BDF32@europa.fae.ub.es> Date: Tue, 12 Nov 1996 21:25:37 +0100 From: Jose =?iso-8859-1?Q?M=AA?= Gomez Organization: Universitat de Barcelona X-Mailer: Mozilla 3.0Gold (X11; I; SunOS 4.1.3 sun4m) Mime-Version: 1.0 To: math@vhdl.org Subject: Package and Body files Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear sir, I am designing an IC for Analog to Digital Conversion. As I can not work with the VHDL-A standard, I am making some tricky things to simulate my sistem. For this reason I need real functions, and also, some information about how to convert form the IEEE 745 standard to the real standard and viceversa. I want to know if it is possible to get this files and information. Yours sincerely, J.M. Gomez From owner-math Thu Dec 19 10:02:45 1996 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id KAA20839 for ; Thu, 19 Dec 1996 10:02:39 -0800 (PST) Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA05749; Thu, 19 Dec 1996 12:50:47 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA05523; Thu, 19 Dec 96 09:50:35 PST Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA851017833; Thu, 19 Dec 96 09:28:08 pst Date: Thu, 19 Dec 96 09:28:08 pst From: "Jose Torres" Message-Id: <9611198510.AA851017833@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: VASG For your information, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: VASG Author: "Stephen A. Bailey" at Unix Date: 12/18/96 10:57 PM Study Group and Working Group Chairs, please forward this message to members of your group. I have two VASG announcements: 1. The VASG will be meeting at ASP-DAC. Victor has scheduled us for Wednesday morning. An exact agenda will be distributed later, but I wanted to give everyone sufficient advance notice for travel planning purposes. You can safely assume that VHDL '98 and the future of VHDL beyond the '98 restandardization will have slots in the agenda. 2. I am starting a new email reflector for the VASG with the IEEE. Apparently, it will take a week or two before it is ready. I will send more information about the reflector when I have it. Meanwhile, I will be sending any VASG messages to the DASC and DASC steering committee reflectors with requests that group chairs forward the message to their groups (sorry for duplicate messages). ================================================================= Stephen A. Bailey 303-652-1578 (voice) 6664 Cherokee Ct. 303-652-1578 (fax) Niwot, CO 80503 mailto:stephen@srbailey.com http://www.srbailey.com ================================================================= Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Wed, 18 Dec 96 22:57:13 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA02707; Wed, 18 Dec 96 22:57:20 PST Received: from vhdl.vhdl.org by mailhost.viewlogic.com (5.0/SMI-4.1) id AA04620; Thu, 19 Dec 1996 01:57:18 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.7.3/8.7.3) with SMTP id XAA29534; Wed, 18 Dec 1996 23:08:30 -0800 (PST) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.6.9/8.6.9) with ESMTP id BAA24870 for ; Thu, 19 Dec 1996 01:55:09 -0500 Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id BAA10516 for stds-dasc-sc-list; Thu, 19 Dec 1996 01:53:58 -0500 (EST) Message-Id: <199612190746.AAA20103@pooh.pageplus.com> Comments: Authenticated sender is From: "Stephen A. Bailey" To: stds.dasc@ieee.org, stds.dasc.sc@ieee.org, svwg@vhdl.org Date: Wed, 18 Dec 1996 23:48:47 -1100 Subject: VASG Priority: normal X-Mailer: Pegasus Mail for Win32 (v2.42) Sender: owner-stds-dasc-sc@majordomo.ieee.org Precedence: bulk Reply-To: "Stephen A. Bailey" X-Resent-To: Multiple Recipients X-Listname: stds-dasc-sc X-List-Description: Mailing-List: stds-dasc-sc X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org Content-Length: 1164 From owner-math Tue Jan 14 10:38:26 1997 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by vhdl.vhdl.org (8.8.4/8.8.3) with SMTP id KAA02020 for ; Tue, 14 Jan 1997 10:38:21 -0800 (PST) Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA25030; Tue, 14 Jan 1997 13:36:33 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA04346; Tue, 14 Jan 97 10:36:29 PST Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA853266999; Tue, 14 Jan 97 09:59:31 pst Date: Tue, 14 Jan 97 09:59:31 pst From: "Jose Torres" Message-Id: <9700148532.AA853266999@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: vhdl.org is back For your information, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: vhdl.org is back Author: Randy Harr at Unix Date: 1/14/97 12:18 AM Please inform your interested parties. Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Tue, 14 Jan 97 00:18:53 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA01567; Tue, 14 Jan 97 00:10:25 PST Received: from vhdl.vhdl.org by mailhost.viewlogic.com (5.0/SMI-4.1) id AA15201; Tue, 14 Jan 1997 03:10:24 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by vhdl.vhdl.org (8.8.4/8.8.3) with SMTP id AAA01174; Tue, 14 Jan 1997 00:11:30 -0800 (PST) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.6.9/8.6.9) with ESMTP id CAA13307 for ; Tue, 14 Jan 1997 02:47:17 -0500 Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id CAA26951 for stds-dasc-list; Tue, 14 Jan 1997 02:43:12 -0500 (EST) Date: Mon, 13 Jan 1997 23:39:35 -0800 (PST) From: Randy Harr Message-Id: <199701140739.XAA01036@vhdl.vhdl.org> To: lee_wood@hdlcon.org, patti@eia.org, stds.dasc@ieee.org Subject: vhdl.org is back Sender: owner-stds-dasc@majordomo.ieee.org Precedence: bulk Reply-To: Randy Harr X-Resent-To: Multiple Recipients X-Listname: stds-dasc X-List-Description: Mailing-List: stds-dasc X-Info: Help requests to stds-dasc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-approval@majordomo.ieee.org Content-Length: 39 From owner-math Sat Mar 8 20:32:25 1997 Received: from ns1.win.net (ns1.win.net [204.215.209.3]) by vhdl.vhdl.org (8.8.5/8.8.3) with SMTP id UAA07949; Sat, 8 Mar 1997 20:32:23 -0800 (PST) Received: (from nobody@localhost) by ns1.win.net (8.6.12/8.6.9) id XAA22831; Sat, 8 Mar 1997 23:30:28 -0500 Received: from dial-32.win.net(204.215.209.132) by ns1.win.net via smap (V1.3) id sma022784; Sat Mar 8 23:30:21 1997 Message-Id: <3.0.32.19970308192040.0069a290@win.net> X-Sender: sevatech@win.net X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Sat, 08 Mar 1997 20:30:58 -0800 To: math-info@vhdl.org, math@vhdl.org From: Larry Saunders Subject: copy of math package Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Where can I get a copy of the VHDL code for the math package? ----------------------------------------------------------- Larry Saunders SEVA Technologies, Inc., (O) 619-538-6283, (F) 619-538-4271 lfs@seva.com From owner-math Tue May 6 12:07:49 1997 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id MAA10611 for ; Tue, 6 May 1997 12:07:43 -0700 (PDT) Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA29562; Tue, 6 May 1997 15:06:24 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA07074; Tue, 6 May 97 12:06:20 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA862945718; Tue, 06 May 97 12:06:21 pst Date: Tue, 06 May 97 12:06:21 pst From: "Jose Torres" Message-Id: <9704068629.AA862945718@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: Future of VHDL Workshop 2 -- Call for Participation FYI, Jose ______________________________ Forward Header __________________________________ Subject: Future of VHDL Workshop 2 -- Call for Participation Author: "Bailey, Stephen A (Steve)" at Unix Date: 5/6/97 11:36 AM DASC Group Chairs, please forward this message to your group members if you believe it will be of interest to them. VASG and SVWG members, attached is a Call for Participation for the 2nd Future of VHDL Workshop to held in Paris, France July 2nd and 3rd. I would like to encourage all members who would like to participate to take the time to apply. Also, the re-distribution of this Call for Participation is not only granted, but highly encouraged! Stephen Bailey VeriBest Inc. 6101 Lookout Rd., Suite A Boulder, CO 80301 mailto:sbailey@veribest.com http://www.veribest.com voice: 303-581-2467 fax: 303-581-9972 SECOND WORKSHOP on « the FUTURE of VHDL » Organized by ECSI and IEEE VASG On July 2nd and 3rd, 1997 At the Hotel IBIS Roissy, Charles de Gaulle Airport, Paris, France The Workshop: ------------- The purpose of the workshop is to gather information from the large community of current and future VHDL users about their design needs, processes and issues that they are experiencing today or anticipate in the next 5-10 years with respect to the use of VHDL and VHDL-related standards (such as VHDL-AMS, standard logic 1164, VITAL, etc.). Each workshop attendee will be expected to describe one or more design issue and how that issue is related to VHDL or how VHDL-based design impacts their design processes and flows. Attendees will organize related design issues and processes looking for commonality and synthesizing broader, more general design issues and processes where appropriate. Attendees will also assess the relative priority of design issues. Workshop Results: ----------------- The output of the workshop will serve as input for the IEEE VHDL standards working groups as well as all other interested parties, in determining how VHDL and VHDL-related standards, tools and processes should evolve over the next several years to better meet designers’ needs. Attendance: ----------- Workshop attendance will be by invitation. Anyone interested in participating and/or attending the workshop may submit a request for invitation. The request for invitation should document the qualifications or information that the requestor can bring to the workshop. Examples of the types of attendees the Workshop organizers encourage: - VHDL designers with wish lists for capabilities they find lacking in VHDL. - Corporate CAD/EDA Support Group personnel who think VHDL and VHDL tools could be better integrated into design processes and flows if only .... - VHDL implementors who have experience implementing VHDL tools and some understanding of what users need. - Academics doing research on future design needs and processes and how they impact HDL (VHDL) based design. - Potential users who would use VHDL if only it .... Requests for invitation should include informal white paper(s) (i.e., relatively coherent notes suitable for sharing with other attendees) that document specific design issues and/or problems in such a way that the problem is the focus and not the solution. We would like to identify first needs, not language requirements. The following examples are for illustrative purposes. Do not interpret these examples as constraints on the issues/problems we seek. Do: Show a need for parameterizing models beyond simple generic values. Do NOT: Ask for object-oriented extensions to VHDL. Do: Show that VHDL could be used in a new domain if a few new capabilities are provided. Do NOT: Ask that VHDL be extended to control system or system-level modeling domains. Do: Show a need to access signals inside the design hierarchy for verification purposes. Do NOT: Ask for a C language PLI.......................etc. Participation without Attending: -------------------------------- While participants are strongly encouraged to attend the workshop, the organizers realize that scheduling and resource conflicts may prevent an interested person from physically attending. Anyone who, despite their best efforts, cannot physically attend but has information which they would like to contribute to the workshop, may contact the workshop organizers via the mechanisms described below. VHDL DESIGNERS AND CAD/EDA SUPPORT ENGINEERS ARE HIGHLY ENCOURAGED TO APPLY! ***************** Additional IEEE Working Group Meetings -------------------------------------- Additional IEEE Working and Study Groups are planning on holding meetings either before or after the Workshop: VHDL analog & mixed signal - Vachoux RT synthesisable subset - Berman OMI - Moretti Shared variables - Bailey Circuit delay & power calculation - Brophy Object oriented extensions - Nebel HW/SW co-design - Peterson ************* Workshop Facilities and Costs ----------------------------- The Hotel IBIS « PARIS-CHARLES DE GAULLE » has extended the workshop excellent facilities that are convenient to de Gaulle airport at a fair price. The cost will be around 550 FF (100$) per attendee per day. The cost includes bedroom, breakfast, workshop meeting rooms, coffee and lunch. Attendees will be responsible for making their own reservations with the hotel. As soon as you are invited ECSI will give you all necessary information for your registration. ****************************************************************** Name: Affiliation: Address: Phone: Fax: E-mail: I would like to participate in the workshop because: (join additional pages when necessary) I would like to attend the following IEEE Working Group meetings: _________________________________________________________________ How to Apply? Due to the limited number of participants that can be accomodated, please submit your request for invitation ASAP to : ECSI Parc Equation 2 avenue de Vignate 38610 Gičres, France or Fax this form to : +33 (0)4 76 42 87 87 or mail it to: office@ecsi.alpes-net.fr www.ecsi.org/ecsi/vhdl.html Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Tue, 06 May 97 11:36:53 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA06317; Tue, 6 May 97 11:34:26 PDT Received: from server.vhdl.org (vhdl.vhdl.org) by mailhost.viewlogic.com (5.0/SMI-4.1) id AA28742; Tue, 6 May 1997 14:34:19 +0500 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id LAA10051; Tue, 6 May 1997 11:34:57 -0700 (PDT) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.8.5/8.8.4) with ESMTP id OAA17584 for ; Tue, 6 May 1997 14:29:05 -0400 (EDT) Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id OAA19575 for stds-dasc-sc-list; Tue, 6 May 1997 14:24:19 -0400 (EDT) Message-Id: From: "Bailey, Stephen A (Steve)" To: "'stds-vasg@majordomo.ieee.org'" , "'stds.dasc.sc@ieee.org'" , "'svwg@vhdl.org'" Subject: Future of VHDL Workshop 2 -- Call for Participation Date: Tue, 6 May 1997 13:28:59 -0500 X-Mailer: Microsoft Exchange Server Internet Mail Connector Version 4.0.994.63 Encoding: 18 TEXT, 129 UUENCODE X-Ms-Attachment: vhdl200x_2.txt 0 00-00-1980 00:00 Sender: owner-stds-dasc-sc@majordomo.ieee.org Precedence: bulk Reply-To: "Bailey, Stephen A (Steve)" X-Resent-To: Multiple Recipients X-Listname: stds-dasc-sc X-List-Description: Mailing-List: stds-dasc-sc X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org Content-Length: 8496 From owner-math Tue May 6 13:18:49 1997 Received: from dfw-ix6.ix.netcom.com (dfw-ix6.ix.netcom.com [206.214.98.6]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id NAA12024 for ; Tue, 6 May 1997 13:18:48 -0700 (PDT) Received: (from smap@localhost) by dfw-ix6.ix.netcom.com (8.8.4/8.8.4) id PAA27944 for ; Tue, 6 May 1997 15:17:36 -0500 (CDT) Date: Tue, 6 May 1997 15:17:36 -0500 (CDT) Message-Id: <199705062017.PAA27944@dfw-ix6.ix.netcom.com> Received: from tam-fl10-04.ix.netcom.com(207.93.39.68) by dfw-ix6.ix.netcom.com via smap (V1.3) id sma027925; Tue May 6 15:17:20 1997 From: jcimbak@ix.netcom.com (Joe J Cimbak) Subject: The Search is ON!! To: math@vhdl.org Good Day! I am a search recruiter and I am doing a MAJOR search for a very large US based company. I am trying to find 150 qualified ASIC engineers for this client. If you know of anyone who is interested in ASIC design employment please have them contact me via email at jcimbak@ix.netcom.com or directly at 813-659-2239 (ofc.), 813-719-3869 (fax), 813-289-1588 (fax, alternate). Skills sought are: Custom circuit design specification, architecture, behavioral modeling, synthesis, floor planning and layout. I am also interested in people skilled in wafer fabrication and packaging. Specific skills: Serial/parallel communication cores and chips FPGA's RF design environment Signal integrity issues A/D interface verification HDL/Verilog SONET physical layer technology Signal processing algorithms Simulation tools Test tools Timing analyis tools C/C++/Visual C UNIX Lan/Wan, Ethernet, ATM, ISDN, HDLC Any other ASIC specialties All interested parties with any experience are encouraged to apply. Applicants from outside of the US can be assured of being sponsored for an H1 visa if hired. Salary ranges from mid $50k (for only college laboratory e xperience) to $130k+ for very qualified and experienced candidates. All applicants should submit resumes which include a section that describes specific ASIC design projects that they participated in and what their role was in these projects. Please forward this email freely!!! Cordially...and at your service! Joe Cimbak From owner-math Tue May 6 14:21:51 1997 Received: from newsgw.mentorg.com (newsgw.mentorg.com [137.202.128.5]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id OAA13505; Tue, 6 May 1997 14:21:49 -0700 (PDT) Received: from em-wv03.wv.mentorg.com by newsgw.mentorg.com (8.6.8.1/CF5.22R) id OAA15937; Tue, 6 May 1997 14:21:03 -0700 Received: from generic by em-wv03.wv.mentorg.com (8.7.5/CF5.36R) id OAA27184; Tue, 6 May 1997 14:21:10 -0700 (PDT) From: "Dennis Brophy" Message-Id: <970506141742.ZM3662@generic> Date: Tue, 6 May 1997 14:17:37 -0700 X-Mailer: Z-Mail 4.0.1 (4.0.1 Apr 9 1996) To: rharr@darpa.mil Subject: Email Abuse Cc: support@ix.netcom.com X-Zm-Priority: High Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Randy, I have registered a complaint of email abuse directly with the offender via email and a telephone message and have reported it to the online service provider via email and a telephone conversation. Many others have registered a complaint with the person in question but he has NOT heeded our requests to cease using the email reflectors on vhdl.org and has continued to post messages to those groups he has not yet posted to. As System Administrator of vhdl.org, would you please forward a request to Netcom to have them cure the email abuse? NETCOM On-Line Communication Services, Inc. Two North Second Street, Plaza A San Jose, CA 95113 (408) 881-1815, (800) NETCOM1 support@ix.netcom.com Thanks, Dennis ----------------------------------------------------------------------------------- > Date: Tue, 6 May 1997 15:17:36 -0500 (CDT) > From: jcimbak@ix.netcom.com (Joe J Cimbak) > Subject: The Search is ON!! > > Good Day! > > I am a search recruiter and I am doing a MAJOR search for a very large US based company. I am trying to find 150 qualified ASIC engineers for this client. If you know of anyone who is interested in ASIC design employment > please have them contact me via email at jcimbak@ix.netcom.com or directly at 813-659-2239 (ofc.), 813-719-3869 (fax), 813-289-1588 (fax, alternate). > > Skills sought are: > Custom circuit design specification, architecture, behavioral modeling, synthesis, floor planning and layout. I am also interested in people skilled in wafer fabrication and packaging. > > Specific skills: > Serial/parallel communication cores and chips > FPGA's > RF design environment > Signal integrity issues > A/D interface verification > HDL/Verilog > SONET physical layer technology > Signal processing algorithms > Simulation tools > Test tools > Timing analyis tools > C/C++/Visual C > UNIX > Lan/Wan, Ethernet, ATM, ISDN, HDLC > Any other ASIC specialties > > All interested parties with any experience are encouraged to apply. Applicants from outside of the US can be assured of being sponsored for an H1 visa if hired. Salary ranges from mid $50k (for only college laboratory e > xperience) to $130k+ for very qualified and experienced candidates. All applicants should submit resumes which include a section that describes specific ASIC design projects that they participated in and what their role > was in these projects. > > Please forward this email freely!!! > > Cordially...and at your service! > Joe Cimbak > From owner-math Tue May 6 14:31:55 1997 Received: from mail.virginia.edu (mail.Virginia.EDU [128.143.2.9]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id OAA13744 for ; Tue, 6 May 1997 14:31:55 -0700 (PDT) Received: from hal.ee.virginia.edu by mail.virginia.edu id aa29789; 6 May 97 16:58 EDT Received: (from rw6x@localhost) by hal.ee.Virginia.EDU (8.7.1/8.6.6) id QAA27072; Tue, 6 May 1997 16:58:11 -0400 (EDT) From: Ronald Waxman Message-Id: <199705062058.QAA27072@hal.ee.Virginia.EDU> Subject: Re: The Search is ON!! To: Joe J Cimbak Date: Tue, 6 May 1997 16:58:11 -0400 (EDT) Cc: math@vhdl.org In-Reply-To: <199705062017.PAA27944@dfw-ix6.ix.netcom.com> from "Joe J Cimbak" at May 6, 97 03:17:36 pm X-Mailer: ELM [version 2.4 PL25] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Joe, The vhdl.org reflectors exist for the purpose of exchange of information related to EDA standards development. They are not to be used for other general purposes. Please stop using them for recruiting. Ron Waxman Design Automation Standards Committee Steering Committee /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ Ronald Waxman ronwax@pipeline.com (preferred) OR Principal Scientist ronw@virginia.edu OR University of Virginia rw6x@virginia.edu Dept of EE, Thornton Hall tel. 1:(+1) (703) 620-2117 (Work #1) Charlottesville, Virginia 22903-2442 tel. 2:(+1) (804) 924-6086 (Work #2) USA fax 1: (+1) (703) 620-6716 (Work #1) for fax 1, call tel. 1 number first to ask for manual setup - otherwise fax 2: (+1) (804) 924-8818 (Work #2) tel. secretary: (+1) (804) 924-6097 (Robbie Burton, rmb@virginia.edu) \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ "Open standards ensure superior technology by enabling innovation, and lay the foundation for..." enhanced productivity. Quote from Netscape home page. From owner-math Fri May 23 16:18:28 1997 Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by server.vhdl.org (8.8.5/8.8.3) with SMTP id QAA14086 for ; Fri, 23 May 1997 16:18:27 -0700 (PDT) Received: from mailhost.vas.viewlogic.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA02347; Fri, 23 May 1997 19:17:04 +0500 Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA10630; Fri, 23 May 97 16:17:05 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA864429575; Fri, 23 May 97 12:42:23 pst Date: Fri, 23 May 97 12:42:23 pst From: "Jose Torres" Message-Id: <9704238644.AA864429575@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: DAC'97 Birds-of-a-Feather Session: The Emerging VHDL "PLI" s FYI, Jose A. Torres -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- DAC'97 Birds-of-a-Feather Session: Topic: The Emerging VHDL "PLI" standard When : Wed, June 11 6-7:30pm Where: Anahiem Marriott, room Organizers: Francoise Martinolle, Cadence Design Systems [fm@cadence.com] John Bartholomew, Viewlogic Systems-Software Group (formerly Eagle Design Automation) [jbartholomew@viewlogic.com] Alex Zamfirescu, Veribest, inc. [AZamfires@VeriBest.com or A.Zamfirescu@IEEE.Org] In the past two years, many parties have expressed an interest in the development of a standard procedural interface for VHDL, along the lines of the Verilog PLI standard. Many EDA vendors have already implemented their own VHDL procedural interfaces. In this session, we will discuss the possibility of joining these diverse efforts in order to converge on an IEEE VHDL procedural interface standard. VHDL designers and tool developers alike are encouraged to attend this DAC'97 birds-of-a-feather session on the ongoing effort to establish a C language VHDL procedural interface. This session's agenda will include: o Welcome and introductions (John Bartholomew) o Standard VHDL PLI rationale (Alex Zamfirescu) (10 minutes) o A presentation of the existing "VHPI" (VHDL Procedural Interface) effort, led by Cadence Design Systems (15 minutes) o A presentation by IKOS Systems on their VHPI effort (15 minutes) o Open discussion on the essential features of a VHDL procedural interface (40 minutes) o Discussion/proposals for further development of an official standard, possibly including the formation of an IEEE Working Group to pursue a VHDL procedural interface standard (Alex Zamfirescu) (15 minutes) o Conclusions and wrap-up (5 minutes) Please fill up the survey before June 9 and mail it to fm@cadence.com -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- 1. Name: Title: Phone number: Email address: Company name and address: 2. What is your company's main development area: - simulation tools - synthesis tools - verification tools - other EDA/CAE/CAD applications software (please specify:) - hardware design - other (please specify:) 3. Have you developed a VHDL procedural interface? 4. Are you using a VHDL procedural interface provided by an EDA tool company? If yes, which one? for what purpose? 5. What are the main features that you would like to see in a VHDL interface? a) complete structural access 1. to the uninstantiated model? 2. to the instantiated model? b) complete behavioral access c) runtime simulator interaction d) simulation control capabilities (breakpoints, callbacks for example) e) others? (please specify:) 6. Which type of applications would you develop using a VHDL procedural interface? a) design traversals b) delay calculators, connectivity extraction c) co-simulation interface d) behavioral modeling e) debugging environments f) simulation testbench and verification g) VHDL code profiler and coverage tools g) others? (please specify:) 7. Is your company providing one of the Verilog PLI/VPI procedural interfaces? 8. Have you used one of the Verilog PLI/VPI procedural interfaces or OMI interface? 9. Would it be desirable for you to have a standard VHDL interface supported by all VHDL simulators? If yes why? If you object to the existence of a standard VHDL interface, please explain why: 10. Would you be interested in participating in a VHDL procedural interface standard effort: by serving on a committee? by reviewing and voting on the standard? 11. Do you think that the VHDL procedural interface should be a. part of the VHDL Language Reference Manual (part of 1076) b. a standard by itself? - with reference to a specific base 1076 standard and synchronized balloting c. an annex to the 1076 LRM that is not required to be implemented? d. part of a PLI standard which will combine various procedural interfaces For example, the PLI standard should be made out of parts such as: 1 Verilog specific PLI set 2 VHDL specific PLI set 3 Common PLI 3.1 OMF subset of common PLI set 3.2 Non OMF Language independent PLI set 12. How do you think the OMI procedural interface would fit in the VHDL procedural interface? Received: from mailhost.vas.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Thu, 22 May 97 14:35:08 pst Return-Path: Received: from mailhost.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA01663; Thu, 22 May 97 14:32:26 PDT Received: from mailgate.cadence.com by mailhost.viewlogic.com (5.0/SMI-4.1) id AA03562; Thu, 22 May 1997 17:32:09 +0500 Received: (from smap@localhost) by mailgate.cadence.com (8.8.5/8.6.8) id OAA14523; Thu, 22 May 1997 14:31:53 -0700 (PDT) Received: from otis.cadence.com(158.140.104.148) by mailgate.cadence.com via smap (V1.0mjr) id sma864336710.014470; Thu May 22 14:31:50 1997 Received: (from fm@localhost) by otis.Cadence.COM (8.7.3/8.7.3) id RAA05967; Thu, 22 May 1997 17:30:44 -0400 (EDT) Date: Thu, 22 May 1997 17:30:44 -0400 (EDT) From: Francoise Martinolle Message-Id: <199705222130.RAA05967@otis.Cadence.COM> To: johns@ikos.com, paulag@ikos.com, frankg@ikos.com, manjit@synopsys.com, radha@synopsys.com, farhad@synopsys.com, sbailey@veribest.com, azamfire@ingr.com, jitlal@asic.sc.ti.com, swite@0-in.com, shawn@systems.com, venky@precedence.com, dennis_brophy@mentorg.com, andrew_guyler@mentorg.com, bgriffin@model.com, gregs@model.com, jbartholomew@viewlogic.com, jtorres@viewlogic.com, skotni@viewlogic.com, gbunza@viewlogic.com, zpaz@sd.com, guym@sd.com, yosiv@sd.com, ramir@sd.com, haimk@sd.com, el@sd.co.il, johnd@sd.com, bhatt@sd.com, dave@sd.com, goeke@kodak.com, bcohen@ccgate.hac.com, gdp@aa.wpafb.af.mil, mermet@imag.fr, iachetta@vnet.ibm.com, janick@qualis.com, dackley@intel.com, m197653@mdc.com, bening@mailhost.rsn.hp.com, sanjay@netcom.com, imai@ics.es.osaka-u.ac.jp, dunlop@altagroup.com, asherer@cadence.com, donnar@cadence.com, manu@cadence.com, cdebra@cadence.com, davek@cadence.com, men ch@mench.com, gabe@veribest.com, vhberman@worldnet.att.net Subject: DAC'97 Birds-of-a-Feather Session: The Emerging VHDL "PLI" standard Cc: fm@cadence.com Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-Md5: FssbUCg9IXqwfBT4OOzVBA== Content-Length: 4918 From owner-math Mon Sep 15 15:39:56 1997 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id PAA22123 for ; Mon, 15 Sep 1997 15:39:55 -0700 (PDT) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.6/VL-1.0) with ESMTP id SAA00831 for ; Mon, 15 Sep 1997 18:36:09 -0400 (EDT) Received: from mailhost.vas.viewlogic.com (mailhost.vas.viewlogic.com [139.181.253.202]) by mailhost.viewlogic.com (8.8.6/VL-1.0) with SMTP id SAA04408 for ; Mon, 15 Sep 1997 18:37:55 -0400 (EDT) Received: from ccmail-fremont.vas.viewlogic.com by mailhost.vas.viewlogic.com (4.1/SMI-4.1) id AA22418; Mon, 15 Sep 97 15:37:48 PDT Received: from ccMail by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) id AA874362934; Mon, 15 Sep 97 15:03:37 pst Date: Mon, 15 Sep 97 15:03:37 pst From: "Jose Torres" Message-Id: <9708158743.AA874362934@ccmail-fremont.vas.viewlogic.com> To: math@vhdl.org Subject: Balloting group for P1499 (OMF) FYI, Jose A. Torres ______________________________ Forward Header __________________________________ Subject: Balloting group for P1499 (OMF) Author: "Moretti, Gabe" at Unix Date: 9/9/97 5:19 PM Dear Colleagues, I am starting the process of establishing the balloting group for the Open Models Forum (P1499) standard. To that end, I would appreciate it very much if you could send this announcement to your respective working groups and other interested parties. I have also posted this notice to comp.lang.vhdl and comp.lang.verilog. Thank you for your help, Gabe You are invited to participate in the balloting of the P1499 Standard, the Open Models Standard. The scope of the Working Group 1499 is the development of a standard simulation and related tools interface for component models written in VHDL, Verilog, C, and other description languages. The purpose is to provide a standard method for interfacing and managing complex electronic models to design automation tools. This method is aimed at providing efficient, accurate, and tool independent interfaces suitable for large designs such as systems on a chip. More information about the Working Group and the proposed standard can be found at http://www.vhdl.org/omf/. If you would like to be included in the balloting group please send email to: gmoretti@vhdl.org. The email should contain the following information: Name, Affiliation, Complete Street Address, Your phone number, your fax number, and your email address, Whether or not you are a member of the IEEE and if so your membership number, Whether you are: a producer of tools using this standard, a user of such tools, or you have a general interest in the standard. The above classifications are important since the IEEE would like a balanced voting constituency made up of representatives from all three classes. Thank you for your interest, Gabe Moretti, Chair of WG 1499. ++++++++++++++++++++++++++++++++++++++ Gabe Moretti Vice President Engineering VeriBest Incorporated 6101 Lookout Road, Suite A Boulder, CO 80301 Phone: 303-581-2324 Fax: 303-581-9143 email: gmoretti@veribest.com http://www.veribest.com Received: from mailhost.viewlogic.com by ccmail-fremont.vas.viewlogic.com (SMTPLINK V2.11.01) ; Tue, 09 Sep 97 17:18:59 pst Return-Path: Received: from server.vhdl.org (server.vhdl.org [198.31.14.3]) by mailhost.viewlogic.com (8.8.6/VL-1.0) with ESMTP id UAA22045 for ; Tue, 9 Sep 1997 20:20:58 -0400 (EDT) Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA01323; Tue, 9 Sep 1997 17:22:17 -0700 (PDT) Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) by mench.mench.com (8.8.5/8.8.4) with ESMTP id UAA23335 for ; Tue, 9 Sep 1997 20:17:12 -0400 (EDT) Received: (from daemon@localhost) by ruebert.ieee.org (8.7.5/8.7.3) id TAA13431; Tue, 9 Sep 1997 19:51:56 -0400 (EDT) Message-ID: From: "Moretti, Gabe" To: stds.dasc.sc@ieee.org Subject: Balloting group for P1499 (OMF) Date: Tue, 9 Sep 1997 18:05:49 -0500 X-Priority: 3 X-Mailer: Internet Mail Service (5.0.1458.49) Sender: owner-stds-dasc-sc@majordomo.ieee.org Precedence: bulk Reply-To: "Moretti, Gabe" X-Resent-To: Multiple Recipients X-Listname: stds-dasc-sc X-List-Description: Mailing-List: stds-dasc-sc X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org From owner-math Mon Sep 22 10:52:42 1997 Received: from alterdial.UU.NET (alterdial.UU.NET [192.48.96.22]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA07440 for ; Mon, 22 Sep 1997 10:52:41 -0700 (PDT) Received: from [153.35.229.208] by alterdial.UU.NET with SMTP (peer crosschecked as: 1Cust80.max9.phoenix.az.ms.uu.net [153.35.229.208]) id QQdidb11656; Mon, 22 Sep 1997 13:50:51 -0400 (EDT) Date: Mon, 22 Sep 1997 13:50:51 -0400 (EDT) X-Sender: mail22316@alterdial.uu.net Message-Id: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" To: "Jose Torres" , gmoretti@veribest.com From: ritag@edat.com (Rita Glover) Subject: Re: Balloting group for P1499 (OMF) Cc: math@vhdl.org Jose and Gabe: I would be interested in joining the OMF balloting group. I'm a "general interest" type of member. My IEEE membership number is 03094331. My contact info is in my signature below. Thanks, Rita Glover President & Principal Analyst At 3:03 PM 9/15/97, Jose Torres wrote: > > FYI, > > Jose A. Torres > >______________________________ Forward Header >__________________________________ >Subject: Balloting group for P1499 (OMF) >Author: "Moretti, Gabe" at Unix >Date: 9/9/97 5:19 PM > > >Dear Colleagues, >I am starting the process of establishing the balloting group for the >Open Models Forum (P1499) standard. >To that end, I would appreciate it very much if you could send this >announcement to your respective working groups and other interested >parties. >I have also posted this notice to comp.lang.vhdl and comp.lang.verilog. >Thank you for your help, >Gabe > > >You are invited to participate in the balloting of the P1499 Standard, >the Open Models >Standard. > >The scope of the Working Group 1499 is the development of a standard >simulation and related >tools interface for component models written in VHDL, Verilog, C, and >other description >languages. > >The purpose is to provide a standard method for interfacing and managing >complex >electronic models to design automation tools. This method is aimed at >providing >efficient, accurate, and tool independent interfaces suitable for large >designs such as >systems on a chip. >More information about the Working Group and the proposed standard can >be found at >http://www.vhdl.org/omf/. > >If you would like to be included in the balloting group please send >email to: >gmoretti@vhdl.org. > >The email should contain the following information: >Name, Affiliation, Complete Street Address, >Your phone number, your fax number, and your email address, >Whether or not you are a member of the IEEE and if so your membership >number, >Whether you are: a producer of tools using this standard, a user of such >tools, or you have a general >interest in the standard. >The above classifications are important since the IEEE would like a >balanced >voting constituency made up of representatives from all three classes. > >Thank you for your interest, >Gabe Moretti, >Chair of WG 1499. >++++++++++++++++++++++++++++++++++++++ >Gabe Moretti >Vice President Engineering >VeriBest Incorporated >6101 Lookout Road, Suite A >Boulder, CO 80301 >Phone: 303-581-2324 Fax: 303-581-9143 >email: gmoretti@veribest.com > http://www.veribest.com > >Received: from mailhost.viewlogic.com by ccmail-fremont.vas.viewlogic.com >(SMTPLINK V2.11.01) > ; Tue, 09 Sep 97 17:18:59 pst >Return-Path: >Received: from server.vhdl.org (server.vhdl.org [198.31.14.3]) by >mailhost.viewlogic.com (8.8.6/VL-1.0) with ESMTP id UAA22045 for >; Tue, 9 Sep 1997 20:20:58 -0400 (EDT) >Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by >server.vhdl.org (8.8.5/8.8.3) with ESMTP id RAA01323; Tue, 9 Sep 1997 >17:22:17 -0700 (PDT) >Received: from ruebert.ieee.org (ruebert.ieee.org [199.172.136.3]) > by mench.mench.com (8.8.5/8.8.4) with ESMTP > id UAA23335 for ; Tue, 9 Sep 1997 20:17:12 -0400 (EDT) >Received: (from daemon@localhost) > by ruebert.ieee.org (8.7.5/8.7.3) > id TAA13431; Tue, 9 Sep 1997 19:51:56 -0400 (EDT) >Message-ID: >From: "Moretti, Gabe" >To: stds.dasc.sc@ieee.org >Subject: Balloting group for P1499 (OMF) >Date: Tue, 9 Sep 1997 18:05:49 -0500 >X-Priority: 3 >X-Mailer: Internet Mail Service (5.0.1458.49) >Sender: owner-stds-dasc-sc@majordomo.ieee.org >Precedence: bulk >Reply-To: "Moretti, Gabe" >X-Resent-To: Multiple Recipients >X-Listname: stds-dasc-sc >X-List-Description: Mailing-List: stds-dasc-sc >X-Info: Help requests to stds-dasc-sc-request@majordomo.ieee.org >X-Info: [Un]Subscribe requests to majordomo@majordomo.ieee.org >X-Moderator-Address: stds-dasc-sc-approval@majordomo.ieee.org EDA Today Web: www.edat.com 10645 N. Tatum, Suite 200-609 Phone: 602-443-9209 Phoenix, AZ 85028 Fax: 602-443-9211 Market Research in Electronic Design Automation From owner-math Thu Jan 8 10:12:33 1998 Received: from intermailhost.viewlogic.com (intermailhost.viewlogic.com [139.181.6.17]) by server.vhdl.org (8.8.5/8.8.3) with ESMTP id KAA05627 for ; Thu, 8 Jan 1998 10:12:32 -0800 (PST) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id NAA01100 for ; Thu, 8 Jan 1998 13:06:12 -0500 (EST) Received: from mailhost.fremont.viewlogic.com (mhf.fremont.viewlogic.com [139.181.214.211]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id NAA13725 for ; Thu, 8 Jan 1998 13:09:41 -0500 (EST) Received: from pc-jtorres.vas.viewlogic.com (pc-jtorres.vas.viewlogic.com [139.181.254.42]) by mailhost.fremont.viewlogic.com (8.8.6/8.8.7) with SMTP id KAA19521 for ; Thu, 8 Jan 1998 10:05:18 -0800 (PST) Message-Id: <3.0.32.19980108100456.006ba228@mailhost.fremont.viewlogic.com> X-Sender: jtorres@mailhost.fremont.viewlogic.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Thu, 08 Jan 1998 10:04:59 -0800 To: math@vhdl.org From: Jose Torres Subject: Application for DASC membership Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=====================_884311499==_" --=====================_884311499==_ Content-Type: text/enriched; charset="us-ascii" For your information, Regards and best wishes for 1998, Jose A. Torres DASC APPLICATION FOR MEMBERSHIP The Design Automation Standards Committee is moving into its fifth year under its new charter. This group is responsible for the standardization of work related to design automation in the electronics industry, one of the fastest growing technology areas of the 1990s. The group began with the successful development of the VHDL standard and is now working on related standards in the logic synthesis, analog simulation, timing verification, and mathematical areas for design verification. The group has also undertaken the standardization of Verilog. Membership in the DASC is the fundamental way in which to support these activities. Membership is a requirement for voting privileges in any of the working or study groups under the DASC as well as for DASC officers. Highlights of the DASC Membership Membership is on a subscription basis. The yearly dues has been reduced to $50. This fee will include membership for all of calendar year 1998 and will include membership in the IEEE SA (for members of the IEEE or CS) for balloting on IEEE standards. Minutes/ Meeting minutes and technical documents will be distributed Mailing electronically and hard copy mailing will be kept to a minimum. Elections All DASC officers, including the DASC Chair and Working and Study Group Chairs are elected by the DASC membership. Administration of the DASC is now being handled directly by IEEE. Please send completed application forms and payment to: DASC C/O Tracy Woods IEEE Computer Society 1730 Massachusetts Avenue, NW Washington, DC 20036-1992 FAX: 202-728-0884 (for credit card payment) Complete and Return by mail or fax with dues of $50.00 US (checks must be payable on a US bank) to "IEEE Computer Society DASC": Name: _______________________________________________________________ Affiliation: _______________________________________________________________ Address: _______________________________________________________________ _______________________________________________________________ City: ______________________________________________ State: ________ Postal Code: _____________________ Country: ______________________________ Telephone: _____________________ Fax: ______________________________ EMail: _______________________________________________________________ For Credit Card Orders Only: Name on Card: _______________________________________________________________ Type of Card: _________________ (American Express, Visa, MasterCard only) Card Number: _______________________________________________________________ Expiration: ______ Signature: ____________________________________________ Optional Information: IEEE Member Number: _______________________________________ Other Professional Affiliations: _______________________________________ Attachment Converted: "c:\eudora\attach\98-app-form1.txt" --=====================_884311499==_ Content-Type: text/plain; name="98-app-form1.txt"; x-mac-type="42494E41"; x-mac-creator="74747874" Content-Transfer-Encoding: x-uuencode Content-Disposition: attachment; filename="98-app-form1.txt" begin 600 98-app-form1.txt MT,\1X*&Q&N$`````````````````````/@`#`/[_"0`&```````````````! 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M5$E/3B!&3U(@345-0D524TA)4`T-#51H92!$97-I9VX@075T;VUA=&EO;B!3 M=&%N9&%R9',@0V]M;6ET=&5E(&ES(&UO=FEN9R!I;G1O(&ET2P@;VYE(&]F('1H92!F87-T97-T#6=R;W=I;F<@=&5C:&YO;&]G M>2!AF%T:6]N(&]F(%9E2!7;V]D0T) M"3$W,S`@36%S#H@("`@(%]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]? M7PT-14UA:6PZ"0E?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]? M7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U\-#0U&;W(@0W)E9&ET($-A M2D-#4-A2P@;VYE(&]F('1H92!F87-T97-T#6=R;W=I;F<@=&5C:&YO;&]G>2!A MF%T:6]N(&]F(%9E2!7;V]D0T)"3$W M,S`@36%S#H@("`@(%]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7PT- M14UA:6PZ"0E?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]? M7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U]?7U\-#0U&;W(@0W)E9&ET($-A2D-#4-A6UB;VP`"R:0`0``07)I86P`(@`$``$( MB!@``-`"``!H`0````"L,R$&6SHA9@`````"``,````````````````````` M``0`@Q```````````````````````````````````"0#+@`````````-=FEC M=&]R(&)E; Fri, 30 Jan 1998 11:40:22 -0800 (PST) Received: from mailhost.viewlogic.com (mailhost.viewlogic.com [139.181.3.35]) by intermailhost.viewlogic.com (8.8.8/8.8.7) with ESMTP id OAA09536 for ; Fri, 30 Jan 1998 14:33:27 -0500 (EST) Received: from mailhost.fremont.viewlogic.com (mhf.fremont.viewlogic.com [139.181.214.211]) by mailhost.viewlogic.com (8.8.6/8.8.7) with ESMTP id OAA28538 for ; Fri, 30 Jan 1998 14:37:17 -0500 (EST) Received: from pc-jtorres.vas.viewlogic.com (pc-jtorres.vas.viewlogic.com [139.181.254.42]) by mailhost.fremont.viewlogic.com (8.8.6/8.8.7) with SMTP id LAA19839 for ; Fri, 30 Jan 1998 11:32:11 -0800 (PST) Message-Id: <3.0.32.19980130113100.006dc518@mailhost.fremont.viewlogic.com> X-Sender: jtorres@mailhost.fremont.viewlogic.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Fri, 30 Jan 1998 11:31:02 -0800 To: math@vhdl.org From: Jose Torres Subject: Invitation to ballot: IEEE P1510 - CHDStd Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" FYI, Jose A. Torres >Date: Fri, 30 Jan 1998 13:24:01 -0600 (CST) >From: Steve Grout >Subject: Invitation to ballot: IEEE P1510 - CHDStd >To: chdstd@vhdl.org >To: dpc-list@vhdl.org, vhdlsynth@vhdl.org, siwg@vhdl.org, viuf-all@vhdl.org >To: vital@vhdl.org >To: tc93-all@eeel.nist.gov >To: tc93-usa-all@eeel.nist.gov >Cc: stds.dasc@ieee.org >Cc: imai@ics.es.osaka-u.ac.jp >Cc: stds.dasc.sc@ieee.org >Cc: cottrell@si2.org (Don Cottrell 342-2244x22) >Cc: Greg.Ledenbach@sematech.org >Cc: grouts@bootskut.eng.sematech.org (512-356-7071) >Reply-to: grouts@bootskut.eng.sematech.org >X-Resent-To: stds-dasc-sc > >To other Working Group Chairs: > - Could you please forward this to your respective working > group reflectors? Thank you. > >--Steve Grout, P1510 Chair >----------- > >Dear Colleague: > >The Design Automation Standards Committee of the IEEE Computer Society >invites you to become a member of the balloting group for IEEE P1510, Draft >Standard for Chip Hierarchical Design System Technical Data (CHDStd) Design >Automation > >SCOPE AND PURPOSE > >The Design Automation Standard for Chip Hierarchical Design System >Technical Data (CHDStd) is an EDA representation of an EE product or >portion of an EE product implemented as an integrated circuit (IC) chip, >including the hierarchical information for logical and physical >design. CHDStd will include the interface to cell, macro, and chip-core >library information; physical chip internal design, manufacturing >properties and design aids; and interface to packaging (physical chip and >higher level chip integration packaging such as MCM and PCA/PCB). CHDStd >will be interoperable with current EDA chip design and implementation >standards. > >The purpose of CHDStd standard is to provide an interoperable comprehensive >electronic design automation (EDA) standard for information supporting >design, synthesis, verification, and integration with manufacturing for >integrated-circuit based electrical and electronic (EE) products. Complex >ICs require greater design productivity and a more reliable, integrated, >and interoperable EDA standard than provided by today's EDA standards. >This method is aimed at providing efficient, accurate, and tool independent >IC product information suitable for large complex chip designs such as >structured custom microprocessors. > > >------------------------------------------------------------------------ > >Name: > >Company/Organization: > >Address: > > > >Phone: > >Fax: > >Email: > >Classification type: (U-User, P-Producer, G-General): > >IEEE Membership number (optional): >(If you are not IEEE member, you can still be part of the balloting >group and provide comments on the draft but your vote is not counted) > > >BALLOTER'S RESPONSIBILITY >If you choose to be part of the balloting group, you will have 60 days >to review and respond to the draft. In order for the sponsor ballot to >be valid, at least 75% of the ballots sent must be returned by the >specified date. For that reason, voters have an obligation to respond. > >BALLOTING PERIOD >At the current time, the working group plans to have a draft prepared >for ballot by the end of the first quarter 1998. The balloting period >will occur approximately one month after this date and last for a >60-day period. Please supply the correct mailing address for this >time. Please do not join the balloting group if you will be >unavailable during this period. > >Signature: > >Date: > >------------------------------------------------------------------------ > >EMAIL/FAX/POST THIS FORM WITH THE ABOVE INFORMATION FILLED OUT TO: > >---Steve Grout - Chair P1510 > SEMATECH > 2706 Montopolis Dr, Austin, TX 78717-6499 > Phone: (512)356-7071 Fax: (512)356-7080 > email: grouts@bootskut.eng.sematech.org or Steve.Grout@SEMATECH.Org > >--Don Cottrell - Co-Chair P1510 > SI2 > Phone: (512)342-2244, X22 FAX: (512)342-2037 > Email: cottrell@si2.org > >COMPLETED INVITATIONS MUST BE RECEIVED BY MARCH 15, 1998. >Invitations received will be forwarded to IEEE. > >Should you have any questions, please contact me or Don Cottrell at your >convenience. Note that this balloting will be conducted in parallel with >a similiar CHDStd activity within IEC TC93 WG3. > >Sincerely, > >Steve Grout, P1510 (CHDStd) Chair >Don Cottrell, P1510 Co-Chair > From owner-math Mon Aug 3 09:25:15 1998 Received: from hamachi.synopsys.com (hamachi.synopsys.com [146.225.8.26]) by server.eda.org (8.8.5/8.8.3) with ESMTP id JAA11618 for ; Mon, 3 Aug 1998 09:25:15 -0700 (PDT) Received: from marathon.synopsys.com (marathon.synopsys.com [146.225.100.41]) by hamachi.synopsys.com (8.8.8/8.8.5) with ESMTP id JAA11730 for ; Mon, 3 Aug 1998 09:20:38 -0700 (PDT) Received: from epic.com ([146.225.124.86]) by marathon.synopsys.com (8.8.8/8.8.8) with SMTP id JAA02703 for ; Mon, 3 Aug 1998 09:20:39 -0700 (PDT) Received: from chip.EPIC by epic.com (SMI-8.6/SMI-SVR4) id JAA09765; Mon, 3 Aug 1998 09:18:52 -0700 X-organization: EPIC Technology Group - Division of Synopsys Inc. Received: from jose-pc.epic.com by chip.EPIC (SMI-8.6/SMI-SVR4) id JAA08703; Mon, 3 Aug 1998 09:18:52 -0700 Message-Id: <3.0.32.19980803092302.00b70f0c@chip.epic.com> X-Sender: jose@chip.epic.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Mon, 03 Aug 1998 09:23:03 -0700 To: math@vhdl.org From: Jose Torres Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" FYI, Jose A. Torres ============== Editorial Alert For more information, contact: April Mitchell (619) 538-6283 april@sd.seva.com VHDL INTERNATIONAL USERS' FORUM TO HOST FALL EVENT "VHDL for Power Users" Workshop Headed to Orlando in October ORLANDO, Fla. -- August 3, 1998 -- The VHDL International Users' Forum (VIUF) will host "Workshops '98: VHDL for Power Users" October 26-28 at the Adam's Mark Hotel here. Workshops '98 replaces VIUF's traditional Fall Conference and is designed to promote interactive exchange of ideas and experiences among attendees. In an informal workshop and tutorial format, presentations and discussions will address moderate- to advanced-level topics to appeal to experienced VHDL users. The program will also include the BMAS '98 Workshop for analog and mixed-signal designers. For more information, contact VIUF Fall Conference Chair Yvonne Ryan, director of DesignBook engineering at Escalade Corp. in Santa Clara, Calif. She can be reached at (408) 654-1600, or email her at yryan@vhdl.org. Information on VHDL International and VIUF's Workshops '98 program and registration can be accessed through the We Site at http://www.vhdl.org/viuf. From owner-math Tue Sep 1 17:06:50 1998 Received: from hamachi.synopsys.com (hamachi.synopsys.com [146.225.8.26]) by server.eda.org (8.8.5/8.8.3) with ESMTP id RAA29996 for ; Tue, 1 Sep 1998 17:06:50 -0700 (PDT) Received: from marathon.synopsys.com (marathon.synopsys.com [146.225.100.41]) by hamachi.synopsys.com (8.8.8/8.8.5) with ESMTP id RAA02539 for ; Tue, 1 Sep 1998 17:02:36 -0700 (PDT) Received: from gate ([146.225.124.86]) by marathon.synopsys.com (8.8.8/8.8.8) with SMTP id RAA24364 for ; Tue, 1 Sep 1998 17:02:00 -0700 (PDT) Received: from chip.EPIC by gate (SMI-8.6/SMI-SVR4) id RAA12875; Tue, 1 Sep 1998 17:00:14 -0700 X-organization: EPIC Technology Group - Division of Synopsys Inc. Received: from jose-pc.epic.com by chip.EPIC (SMI-8.6/SMI-SVR4) id RAA25212; Tue, 1 Sep 1998 17:00:11 -0700 Message-Id: <3.0.32.19980901170452.0156fdb8@chip.epic.com> X-Sender: jose@chip.epic.com X-Mailer: Windows Eudora Pro Version 3.0 (32) Date: Tue, 01 Sep 1998 17:04:55 -0700 To: math@vhdl.org From: Jose Torres Subject: Fall VIUF Workshops '98 Round-robin - pssssttttt! pass it on! Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by server.eda.org id RAA29997 FYI, Jose >Return-Path: >X-organization: EPIC Technology Group - Division of Synopsys Inc. >X-Sender: "April Mitchell" >Date: Tue, 01 Sep 1998 15:57:38 -0700 >To: Peter Ashenden , > Yvonne Ryan , Jose Torres , > Jim Goeke , > Mike McCollough , > Matt Hsu , Nanette Collins , > Karen Miller , Philip Wilsey , > John Willis , > Greg Peterson , > John Hillawi , > Serafin Olcoz , Paul Menchini , > Wolfgang Ecker , > Michael McKinney , > Jarayam Bhasker , > Dennis Brophy , > Todd DeLong , Steve Drager , > Darrell Gibson , > Bill Hanna , > Gabe Moretti , > Wolfgang Nebel , > Mark Ronan , Lance Thompson >From: "April Mitchell" >Subject: Fall VIUF Workshops '98 Round-robin - pssssttttt! pass it on! > > >Do You Consider Yourself to be a VHDL-Based Power User? Yes? Then, Read On … >This Email is For You … > >Please join us for the VHDL International Users’ Forum (VIUF) “Workshops ’98: >VHDL for Power Users” October 26-28 at the Adam’s Mark Hotel in sunny Orlando, >Florida. We’re planning three full days of tutorials and workshops for you, >the seasoned VHDL-based user. >Workshops ’98 will feature moderate- to advanced-level topics to appeal to >you, >the experienced VHDL user. Workshops will focus on design for reuse, >testbenches and testing, modeling enhancements, and design and synthesis for >FPGAs and reconfigurable logic. The program includes numerous tutorials for >advanced VHDL users, one of which will detail the new VHDL Standard Procedural >Interface. A special paper session will highlight work being done with >VHDL in >the academic community. A parallel track, called BMAS ’98 Workshop, is geared >to analog and mixed-signal designers. > Workshop and/or tutorial registration varies from $250 for a one-day, >tutorial only registration, to $600 for both tutorial and workshops. > For more information, contact VIUF Fall Chair Yvonne Ryan, director of >DesignBook Engineering at Escalade Corp. She can be reached at (408) >654-1682, >or email her at yryan@vhdl.org or yvonne@escalade.com. Information on VHDL >International and VIUF’s Workshops ’98 program and registration can be >accessed >through the We Site at http://www.vhdl.org/viuf. > Now, could we ask you to do us a favor? Please forward this email to >your colleagues, and ask them to forward it to their colleagues in the VHDL >community. After all, isn’t word of mouth the best form of publicity? Thanks >for your help … And, see you in Orlando! > >----------------------------------------------------------- >April Mitchell (O) 619-538-6283 >SEVA Technologies, Inc., (F) 619-538-4271 >9330 Carmel Mtn Rd, STE H >San Diego, CA 92129 >april@sd.seva.com > > > >http://www.seva.com > > From owner-math Thu Oct 8 16:12:11 1998 Received: from mx-a.qnet.com (mx-a.qnet.com [207.155.33.13]) by server.eda.org (8.8.5/8.8.3) with ESMTP id QAA19707 for ; Thu, 8 Oct 1998 16:12:09 -0700 (PDT) Received: from chrislin.UUCP (uucp@localhost) by mx-a.qnet.com (8.9.1a/8.9.1) with UUCP id QAA18047 for math@vhdl.org; Thu, 8 Oct 1998 16:05:54 -0700 (PDT) Message-Id: <199810082305.QAA18047@mx-a.qnet.com> Received: by chrislin (MG PM3->Waf 3.40), Thu, 8 Oct 98 15:43:01 PDT From: RON@chrislin.com (Ron Seese) To: math@vhdl.org Date: Thu, 8 Oct 1998 15:11:49 -0700 MIME-Version: 1.0 Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7BIT Subject: Int to IEEE 754 Reply-to: ron@chrislin.com Priority: normal X-mailer: Pegasus Mail for Win32 (v3.01b) I need to produce a piece of hardware that will convert Integers to IEEE 754 fp numbers. Is there vhdl code available to do this? Best Regards, Ron Seese Chrislin Industries 818-991-2254 voice 818-991-3490 fax http://www.chrislin.com From owner-math Tue Nov 23 07:23:47 1999 Received: from ns.arrowuk.com (firewall-user@ns.arrowuk.com [194.130.140.2]) by server.eda.org (8.8.5/8.8.3) with ESMTP id HAA28529 for ; Tue, 23 Nov 1999 07:23:45 -0800 (PST) Received: by ns.arrowuk.com; id QAA11427; Tue, 23 Nov 1999 16:19:07 GMT Received: from notesgw.arrowitaly.com(10.156.0.18) by ns.arrowuk.com via smap (V4.2) id xma011216; Tue, 23 Nov 99 16:18:34 GMT Received: by notesgw.arrowitaly.com(Lotus SMTP MTA v4.6.2 (693.3 8-11-1998)) id 41256832.00543A4F ; Tue, 23 Nov 1999 16:19:59 +0100 X-Lotus-FromDomain: ARROW-ITALY From: "Massimo Torresin" To: math@vhdl.org Message-ID: <41256832.00543A43.00@notesgw.arrowitaly.com> Date: Tue, 23 Nov 1999 16:18:44 +0100 Subject: Request Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Hello, I'm Massimo Torresin from Italy. I'm a FAE of ALTERA. Could you send me the files about math pakage? My e-mail size is not over 2Mbyte. Thank you Best Regards. Massimo From owner-math Fri Nov 26 09:03:55 1999 Received: from ns.arrowuk.com (firewall-user@ns.arrowuk.com [194.130.140.2]) by server.eda.org (8.8.5/8.8.3) with ESMTP id JAA18626 for ; Fri, 26 Nov 1999 09:03:51 -0800 (PST) Received: by ns.arrowuk.com; id RAA00256; Fri, 26 Nov 1999 17:59:04 GMT Received: from notesgw.arrowitaly.com(10.156.0.18) by ns.arrowuk.com via smap (V4.2) id xmap17255; Fri, 26 Nov 99 17:58:53 GMT Received: by notesgw.arrowitaly.com(Lotus SMTP MTA v4.6.2 (693.3 8-11-1998)) id 41256835.005177B6 ; Fri, 26 Nov 1999 15:49:50 +0100 X-Lotus-FromDomain: ARROW-ITALY From: "Massimo Torresin" To: math@vhdl.org Message-ID: <41256835.00517688.00@notesgw.arrowitaly.com> Date: Fri, 26 Nov 1999 15:48:26 +0100 Subject: Request Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Hello, I'm Massimo Torresin from Italy. I'm a FAE of ALTERA. Could you send me the files about math pakage? My e-mail size is up to 2Mbyte. Thank you Best Regards. Massimo From owner-math Fri Nov 26 09:03:55 1999 Received: from ns.arrowuk.com (firewall-user@ns.arrowuk.com [194.130.140.2]) by server.eda.org (8.8.5/8.8.3) with ESMTP id JAA18625 for ; Fri, 26 Nov 1999 09:03:50 -0800 (PST) Received: by ns.arrowuk.com; id RAA00258; Fri, 26 Nov 1999 17:59:04 GMT Received: from notesgw.arrowitaly.com(10.156.0.18) by ns.arrowuk.com via smap (V4.2) id xmao17255; Fri, 26 Nov 99 17:58:47 GMT Received: by notesgw.arrowitaly.com(Lotus SMTP MTA v4.6.2 (693.3 8-11-1998)) id 41256835.00517DEE ; Fri, 26 Nov 1999 15:50:06 +0100 X-Lotus-FromDomain: ARROW-ITALY From: "Massimo Torresin" To: math@vhdl.org Message-ID: <41256835.00517DD5.00@notesgw.arrowitaly.com> Date: Fri, 26 Nov 1999 15:48:44 +0100 Subject: Request Mime-Version: 1.0 Content-type: text/plain; charset=us-ascii Content-Disposition: inline Hello, I'm Massimo Torresin from Italy. I'm a FAE of ALTERA. Could you send me the files about math pakage? My e-mail size is not over 2Mbyte. Thank you Best Regards. Massimo From owner-math Sun Nov 28 17:23:57 1999 Received: from tigger.cs.adelaide.edu.au (tigger.cs.adelaide.edu.au [129.127.8.65]) by server.eda.org (8.8.5/8.8.3) with ESMTP id RAA25977 for ; Sun, 28 Nov 1999 17:23:54 -0800 (PST) Received: from chook.cs.adelaide.edu.au (root@chook [129.127.8.8]) by tigger.cs.adelaide.edu.au (8.9.1/8.9.1) with ESMTP id LAA03537 return ; Mon, 29 Nov 1999 11:55:15 +1030 (CST) Received: from cs.adelaide.edu.au (wol [129.127.8.62]) by chook.cs.adelaide.edu.au (8.9.1/8.9.1) with ESMTP id LAA15864 return ; Mon, 29 Nov 1999 11:55:07 +1030 (CST) Message-ID: <3841D5E9.77EE887C@cs.adelaide.edu.au> Date: Mon, 29 Nov 1999 11:54:57 +1030 From: "Peter J. Ashenden" Organization: University of Adelaide, Dept Computer Science X-Mailer: Mozilla 4.7 [en] (WinNT; I) X-Accept-Language: en MIME-Version: 1.0 To: Massimo Torresin CC: math@vhdl.org Subject: Re: Request References: <41256835.00517DD5.00@notesgw.arrowitaly.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Massimo, > Hello, I'm Massimo Torresin from Italy. > I'm a FAE of ALTERA. > Could you send me the files about math pakage? > My e-mail size is not over 2Mbyte. Are you referring to the VHDL package source files? If so, they are unfortunately not available for free. They are copyright by the IEEE, and are obtainable wen you buy a copy of the standard (Std 1076.2-1996), which you can order from http://standards.ieee.org/. Note: I'm not supporting the IEEE's marketing position in any way, just pointing out the way things are. Cheers, PA -- Dr. Peter J. Ashenden Email: petera@cs.adelaide.edu.au Dept. Computer Science peter.ashenden@acm.org University of Adelaide peter.ashenden@computer.org Adelaide, SA 5005 Phone: +61 8 8303 4477 Australia Fax: +61 8 8303 4366 WWW: http://www.cs.adelaide.edu.au/~petera (includes PGP public key) From owner-math Sun Sep 17 22:15:57 2000 Received: from mailserver-ng.cs.umbc.edu (mailserver-ng.cs.umbc.edu [130.85.100.230]) by server.eda.org (8.11.0/8.11.0) with ESMTP id e8I5FtX09403 for ; Sun, 17 Sep 2000 22:15:56 -0700 (PDT) Received: from sunserver1.cs.umbc.edu (actaeon.cs.umbc.edu [130.85.99.51]) by mailserver-ng.cs.umbc.edu (8.9.3/8.9.3) with ESMTP id BAA03295 for ; Mon, 18 Sep 2000 01:13:10 -0400 (EDT) Received: from localhost (squire@localhost) by sunserver1.cs.umbc.edu (8.9.3/8.9.3) with SMTP id BAA05676 for ; Mon, 18 Sep 2000 01:13:10 -0400 (EDT) X-Authentication-Warning: sunserver1.cs.umbc.edu: squire owned process doing -bs Date: Mon, 18 Sep 2000 01:13:10 -0400 (EDT) From: "Jon S. Squire." To: math@vhdl.org Subject: ftp.vhdl.org/pub/math/packages can't read Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Please set the permissions so files can be read on ftp.vhdl.org/pub/math/packages The permissions are OK on ftp.vhdl.org/pub/math/testbench Same problem using www.vhdl.org/vi/math/packages Thank you, Jon squire@csee.umbc.edu www.csee.umbc.edu/~squire From owner-math Mon Sep 18 09:00:13 2000 Received: from mench.mench.com (mench.mench.com [199.72.53.1]) by server.eda.org (8.11.0/8.11.0) with ESMTP id e8IG0AX11735 for ; Mon, 18 Sep 2000 09:00:12 -0700 (PDT) Received: (from mench@localhost) by mench.mench.com (8.11.0/8.11.0) id e8IFxwF08626; Mon, 18 Sep 2000 11:59:58 -0400 (EDT) From: "Paul J. Menchini" Message-Id: <200009181559.e8IFxwF08626@mench.mench.com> Subject: Re: ftp.vhdl.org/pub/math/packages can't read To: squire@csee.umbc.edu (Jon S. Squire.) Date: Mon, 18 Sep 2000 11:59:56 -0400 (EDT) Cc: math@vhdl.org In-Reply-To: from "Jon S. Squire." at Sep 18, 2000 01:13:10 AM X-Mailer: ELM [version 2.5 PL2] MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear Mr. Squire, > Please set the permissions so files can be read on > ftp.vhdl.org/pub/math/packages I'm sorry, but we're unable to comply with your request. These packages are copyrighted by the IEEE and they do not allow unlicensed electronic access to them once balloting for a standard commences. Please contact me directly if I can assist you in contacting the IEEE to obtain a license for electronic copies. Regards, Paul Menchini Chair, IEEE DASC From owner-math Thu Mar 8 10:22:15 2001 Received: from smtp10.atl.mindspring.net (smtp10.atl.mindspring.net [207.69.200.246]) by server.eda.org (8.11.0/8.11.0) with ESMTP id f28IM3113822; Thu, 8 Mar 2001 10:22:04 -0800 (PST) Received: from GREG.lanta.com (user-38lcptc.dialup.mindspring.com [209.86.103.172]) by smtp10.atl.mindspring.net (8.9.3/8.8.5) with ESMTP id NAA10702; Thu, 8 Mar 2001 13:16:58 -0500 (EST) Message-Id: <4.3.0.20010308130249.00a829d0@pop.mindspring.com> X-Sender: jimmystroud@mindspring.com@pop.mindspring.com (Unverified) X-Mailer: QUALCOMM Windows Eudora Version 4.3 Date: Thu, 08 Mar 2001 13:15:09 -0500 To: jstroud@lanta.com From: Jim Stroud Subject: Can you help me with VHDL? Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; format=flowed Hi, I was doing some research on VHDL and was hoping you can help me? I am looking for some techs for a client in FLORIDA/CALIFORNIA. Specifically, VERIFICATION ENGINEERS, SR APPLICATION ENGINEERS (HARDWARE) and SR ENGINEERS OF DIGITAL IC DESIGN. The client operates in powerline networking technology over residential powerlines. If you can point me in the direction of someone who would be interested in learning more, I would appreciate it. If by chance you are interested, please forward a WORD version of your resume and a good time for me to contact you. Thanks! Jim Stroud Account Executive Lanta Technology Group http://lanta.com