Tested with Xilinx M12.4i (updated)

After building your project, Select one of your source files after clicking
"Implementation".
Under the "Project" pulldown, select "new VHDL library".
Clock on the "..." at the end of "library location"
Use the "create" button to create a new directory, name it "ieee_proposed".
(hint, put this directory in your project directory)
Enter IEEE_PROPOSED in the New VHDL library name.
OK the form.
Right click "Adding Source..." windows comes up, add the files
"fixed_float_types_c.vhdl", "fixed_pkg_c.vhdl" and "float_pkg_c.vhdl".
Use the pull down under the "Library" tab to select the "ieee_porposed"
library you just created.

Click on "Synthesis" and select "Run".

I had to really fight to get these packages to synthesize in this tool. I
could not check everything, so "use at your own risk".  For a real Xilinx
project I would use Synplicity or Leonardo.

Things Xilinx m11.1i didn't like about these packages:
1) 'instance_name showed as a syntax error, replace with package name
2) "to_stdlogicvector(to_suv(arg))" shows as a type conversion error, replace
with casting "std_logic_vector()"
3) Did not like any of the fixed point division routines,
had to comment them out.
4) Had to comment out the "?=" routines, XST could not deal with that syntax.