Current (Standards) Groups on the VIUF / eda.org System
                      18 Nov 2003, ver 2.4

Name                                                     code-name
-------------------------------------------------        ------------
Accellera Architecture Language Committee - C++ WG	 alc-cwg
Accellera Designers' Forum				 adf
Accellera OpenKit Tech Committee                         openkit
Accellera System Level Design Standard			 slds
EDA Benchmark Group					 benchmrk
EIA DAD IBIS Open Forum (I/O Buffer Info Spec)           ibis
EIA DAD Rule Augmented Interconnect Layout Specification rail
Free Model Foundation                                    fmf
IEC TC93 Design Automation - USA TAG Activity            tc93ustag
IEC TC93 Design Automation - WG 1 on Interoperability    tc93wg1
IEEE CSS Computer-Aided Network Design Workshop          cande
IEEE Design Automation Standards Committee               dasc
IEEE DASC Chip Hierarchical Design System tech. data WG  chdstd
IEEE DASC Circuit Delay and Power Calculation System     dpc
IEEE DASC Floating-Point HDL Packages Group		 fphdl
IEEE DASC Open Modeling Forum WG                         omf
IEEE DASC Standard Delay Format SG                       sdf
IEEE DASC Timing (VHDL Intiative Towards ASIC Libraries) vital
IEEE DASC Verilog Synthesis Subset WG                    vlog-synth
IEEE DASC Verilog Analog Mixed-Signal WG                 verilog-ams, vlog-ams
IEEE DASC VHDL Analysis and Standardization Group        vasg
IEEE DASC VASG ISAC (VHDL)                               isac
IEEE DASC VHDL Analog and Mixed Signal WG                vhdl-ams
IEEE DASC VHDL Library "library ieee;" WG                libieee
IEEE DASC VHDL Math Package WG                           math
IEEE DASC VHDL Object Oriented SG                        oovhdl
IEEE DASC VHDL PLI Task Force                            vhdlpli
IEEE DASC VHDL Shared Variable WG                        svwg
IEEE DASC VHDL Synthesis WG                              vhdlsynth
IEEE DASC VHDL Synthesis Interoperability WG             siwg
IEEE DATC Electronic Design Processes Subcommittee       edps
OVI/VI Design Constraints WG                             dcwg
OVI Advanced Library Format                              alf
OVI [Integrated Circuit] Architectural Language Committee arch
OVI Verilog Formal Verification WG                       vfv
VI System Level Design Language comittee                 sldl

(note: You can substitute verilog.org, vhdl.org or dasc.org for eda.org)

To find out more info about a group, send an email request to:

        <code-name>-info@eda.org

To get added to an email exploder and be made aware of the groups
activities, send your email address to:

        <code-name>-request@eda.org

To submit a message to an email exploder, email the message to:

        <code-name>@eda.org

Most of these groups have active file repositories also (including an
archive of all email discussion traffic).  Check either the "pub"
directory for the group of interest.

In addition, there are repositories for the following topics / ad-hoc groups:

Misc. submissions (from VUG/VIUF meetings, etc.)        misc
VHDL Users' Group RBBS PC Machine (1988-1991)           vug_bbs
Useful public domain tools for UNIX, Macintosh, and     tools
  PC (DOS and Windows)

Happy Internetting!

docs/groups.txt